2 * (C) Copyright 2013 ADVANSEE
3 * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
5 * Based on Dirk Behme's
6 * https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c,
7 * which is based on Freescale's
8 * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6,
10 * Copyright (C) 2011 Freescale Semiconductor, Inc.
12 * SPDX-License-Identifier: GPL-2.0+
17 #include <linux/errno.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/imx-regs.h>
21 #include <asm/mach-imx/sys_proto.h>
23 #define BO_CTRL_WR_UNLOCK 16
24 #define BM_CTRL_WR_UNLOCK 0xffff0000
25 #define BV_CTRL_WR_UNLOCK_KEY 0x3e77
26 #define BM_CTRL_ERROR 0x00000200
27 #define BM_CTRL_BUSY 0x00000100
28 #define BO_CTRL_ADDR 0
30 #define BM_CTRL_ADDR 0x0000000f
31 #define BM_CTRL_RELOAD 0x00000400
32 #elif defined(CONFIG_MX7ULP)
33 #define BM_CTRL_ADDR 0x000000FF
34 #define BM_CTRL_RELOAD 0x00000400
35 #define BM_OUT_STATUS_DED 0x00000400
36 #define BM_OUT_STATUS_LOCKED 0x00000800
37 #define BM_OUT_STATUS_PROGFAIL 0x00001000
39 #define BM_CTRL_ADDR 0x0000007f
43 #define BO_TIMING_FSOURCE 12
44 #define BM_TIMING_FSOURCE 0x0007f000
45 #define BV_TIMING_FSOURCE_NS 1001
46 #define BO_TIMING_PROG 0
47 #define BM_TIMING_PROG 0x00000fff
48 #define BV_TIMING_PROG_US 10
50 #define BO_TIMING_STROBE_READ 16
51 #define BM_TIMING_STROBE_READ 0x003f0000
52 #define BV_TIMING_STROBE_READ_NS 37
53 #define BO_TIMING_RELAX 12
54 #define BM_TIMING_RELAX 0x0000f000
55 #define BV_TIMING_RELAX_NS 17
56 #define BO_TIMING_STROBE_PROG 0
57 #define BM_TIMING_STROBE_PROG 0x00000fff
58 #define BV_TIMING_STROBE_PROG_US 10
61 #define BM_READ_CTRL_READ_FUSE 0x00000001
63 #define BF(value, field) (((value) << BO_##field) & BM_##field)
65 #define WRITE_POSTAMBLE_US 2
67 #if defined(CONFIG_MX6) || defined(CONFIG_VF610)
68 #define FUSE_BANK_SIZE 0x80
71 #elif defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL)
76 #elif defined CONFIG_MX7
77 #define FUSE_BANK_SIZE 0x40
79 #elif defined(CONFIG_MX7ULP)
80 #define FUSE_BANK_SIZE 0x80
83 #error "Unsupported architecture\n"
86 #if defined(CONFIG_MX6)
89 * There is a hole in shadow registers address map of size 0x100
90 * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX,
91 * iMX6UL, i.MX6ULL and i.MX6SLL.
92 * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
93 * we should account for this hole in address space.
95 * Similar hole exists between bank 14 and bank 15 of size
96 * 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX.
97 * Note: iMX6SL has only 0-7 banks and there is no hole.
98 * Note: iMX6UL doesn't have this one.
100 * This function is to covert user input to physical bank index.
101 * Only needed when read fuse, because we use register offset, so
102 * need to calculate real register offset.
103 * When write, no need to consider hole, always use the bank/word
104 * index from fuse map.
106 u32 fuse_bank_physical(int index)
110 if (is_mx6sl() || is_mx7ulp()) {
112 } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
113 if ((is_mx6ull() || is_mx6sll()) && index == 8)
117 phy_index = fuse_bank_physical(5) + (index - 6) + 3;
122 phy_index = fuse_bank_physical(14) + (index - 15) + 2;
124 phy_index = fuse_bank_physical(5) + (index - 6) + 3;
131 u32 fuse_word_physical(u32 bank, u32 word_index)
133 if (is_mx6ull() || is_mx6sll()) {
135 word_index = word_index + 4;
141 u32 fuse_bank_physical(int index)
146 u32 fuse_word_physical(u32 bank, u32 word_index)
153 static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
155 while (readl(®s->ctrl) & BM_CTRL_BUSY)
159 static void clear_error(struct ocotp_regs *regs)
161 writel(BM_CTRL_ERROR, ®s->ctrl_clr);
164 static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word,
165 int assert, const char *caller)
167 *regs = (struct ocotp_regs *)OCOTP_BASE_ADDR;
169 if (bank >= FUSE_BANKS ||
170 word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 ||
172 printf("mxc_ocotp %s(): Invalid argument\n", caller);
176 if (is_mx6ull() || is_mx6sll()) {
177 if ((bank == 7 || bank == 8) &&
178 word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 3) {
179 printf("mxc_ocotp %s(): Invalid argument\n", caller);
192 static int finish_access(struct ocotp_regs *regs, const char *caller)
196 err = !!(readl(®s->ctrl) & BM_CTRL_ERROR);
200 /* Need to power down the OTP memory */
201 writel(1, ®s->pdn);
204 printf("mxc_ocotp %s(): Access protect error\n", caller);
211 static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val,
214 return prepare_access(regs, bank, word, val != NULL, caller);
217 int fuse_read(u32 bank, u32 word, u32 *val)
219 struct ocotp_regs *regs;
224 ret = prepare_read(®s, bank, word, val, __func__);
228 phy_bank = fuse_bank_physical(bank);
229 phy_word = fuse_word_physical(bank, word);
231 *val = readl(®s->bank[phy_bank].fuse_regs[phy_word << 2]);
234 if (readl(®s->out_status) & BM_OUT_STATUS_DED) {
235 writel(BM_OUT_STATUS_DED, ®s->out_status_clr);
236 printf("mxc_ocotp %s(): fuse read wrong\n", __func__);
240 return finish_access(regs, __func__);
244 static void set_timing(struct ocotp_regs *regs)
250 ipg_clk = mxc_get_clock(MXC_IPG_CLK);
252 fsource = DIV_ROUND_UP((ipg_clk / 1000) * BV_TIMING_FSOURCE_NS,
254 prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_PROG_US, 1000000) + 1;
256 timing = BF(fsource, TIMING_FSOURCE) | BF(prog, TIMING_PROG);
258 clrsetbits_le32(®s->timing, BM_TIMING_FSOURCE | BM_TIMING_PROG,
261 #elif defined(CONFIG_MX7ULP)
262 static void set_timing(struct ocotp_regs *regs)
264 /* No timing set for MX7ULP */
268 static void set_timing(struct ocotp_regs *regs)
271 u32 relax, strobe_read, strobe_prog;
274 ipg_clk = mxc_get_clock(MXC_IPG_CLK);
276 relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1;
277 strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS,
278 1000000000) + 2 * (relax + 1) - 1;
279 strobe_prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_STROBE_PROG_US,
280 1000000) + 2 * (relax + 1) - 1;
282 timing = BF(strobe_read, TIMING_STROBE_READ) |
283 BF(relax, TIMING_RELAX) |
284 BF(strobe_prog, TIMING_STROBE_PROG);
286 clrsetbits_le32(®s->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX |
287 BM_TIMING_STROBE_PROG, timing);
291 static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
294 u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
299 /* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */
300 if ((is_mx6ull() || is_mx6sll()) && (bank > 7)) {
304 addr = bank << 3 | word;
308 clrsetbits_le32(®s->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR,
309 BF(wr_unlock, CTRL_WR_UNLOCK) |
310 BF(addr, CTRL_ADDR));
313 int fuse_sense(u32 bank, u32 word, u32 *val)
315 struct ocotp_regs *regs;
318 ret = prepare_read(®s, bank, word, val, __func__);
322 setup_direct_access(regs, bank, word, false);
323 writel(BM_READ_CTRL_READ_FUSE, ®s->read_ctrl);
326 *val = readl((®s->read_fuse_data0) + (word << 2));
328 *val = readl(®s->read_fuse_data);
332 if (readl(®s->out_status) & BM_OUT_STATUS_DED) {
333 writel(BM_OUT_STATUS_DED, ®s->out_status_clr);
334 printf("mxc_ocotp %s(): fuse read wrong\n", __func__);
339 return finish_access(regs, __func__);
342 static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
345 return prepare_access(regs, bank, word, true, caller);
348 int fuse_prog(u32 bank, u32 word, u32 val)
350 struct ocotp_regs *regs;
353 ret = prepare_write(®s, bank, word, __func__);
357 setup_direct_access(regs, bank, word, true);
361 writel(0, ®s->data1);
362 writel(0, ®s->data2);
363 writel(0, ®s->data3);
364 writel(val, ®s->data0);
367 writel(val, ®s->data1);
368 writel(0, ®s->data2);
369 writel(0, ®s->data3);
370 writel(0, ®s->data0);
373 writel(0, ®s->data1);
374 writel(val, ®s->data2);
375 writel(0, ®s->data3);
376 writel(0, ®s->data0);
379 writel(0, ®s->data1);
380 writel(0, ®s->data2);
381 writel(val, ®s->data3);
382 writel(0, ®s->data0);
385 wait_busy(regs, BV_TIMING_PROG_US);
387 writel(val, ®s->data);
388 wait_busy(regs, BV_TIMING_STROBE_PROG_US);
390 udelay(WRITE_POSTAMBLE_US);
393 if (readl(®s->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) {
394 writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), ®s->out_status_clr);
395 printf("mxc_ocotp %s(): fuse write is failed\n", __func__);
400 return finish_access(regs, __func__);
403 int fuse_override(u32 bank, u32 word, u32 val)
405 struct ocotp_regs *regs;
410 ret = prepare_write(®s, bank, word, __func__);
414 phy_bank = fuse_bank_physical(bank);
415 phy_word = fuse_word_physical(bank, word);
417 writel(val, ®s->bank[phy_bank].fuse_regs[phy_word << 2]);
420 if (readl(®s->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) {
421 writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), ®s->out_status_clr);
422 printf("mxc_ocotp %s(): fuse write is failed\n", __func__);
427 return finish_access(regs, __func__);