1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013 ADVANSEE
4 * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
6 * Based on Dirk Behme's
7 * https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c,
8 * which is based on Freescale's
9 * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6,
11 * Copyright (C) 2011 Freescale Semiconductor, Inc.
16 #include <linux/errno.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/imx-regs.h>
20 #include <asm/mach-imx/sys_proto.h>
22 #define BO_CTRL_WR_UNLOCK 16
23 #define BM_CTRL_WR_UNLOCK 0xffff0000
24 #define BV_CTRL_WR_UNLOCK_KEY 0x3e77
25 #define BM_CTRL_ERROR 0x00000200
26 #define BM_CTRL_BUSY 0x00000100
27 #define BO_CTRL_ADDR 0
29 #define BM_CTRL_ADDR 0x0000000f
30 #define BM_CTRL_RELOAD 0x00000400
31 #elif defined(CONFIG_MX7ULP)
32 #define BM_CTRL_ADDR 0x000000FF
33 #define BM_CTRL_RELOAD 0x00000400
34 #define BM_OUT_STATUS_DED 0x00000400
35 #define BM_OUT_STATUS_LOCKED 0x00000800
36 #define BM_OUT_STATUS_PROGFAIL 0x00001000
37 #elif defined(CONFIG_IMX8M)
42 #define BM_CTRL_ADDR 0x000001ff
43 #define BM_CTRL_ERROR 0x00000400
44 #define BM_CTRL_BUSY 0x00000200
46 #define BM_CTRL_ADDR 0x000000ff
49 #define BM_CTRL_ADDR 0x0000007f
53 #define BO_TIMING_FSOURCE 12
54 #define BM_TIMING_FSOURCE 0x0007f000
55 #define BV_TIMING_FSOURCE_NS 1001
56 #define BO_TIMING_PROG 0
57 #define BM_TIMING_PROG 0x00000fff
58 #define BV_TIMING_PROG_US 10
60 #define BO_TIMING_STROBE_READ 16
61 #define BM_TIMING_STROBE_READ 0x003f0000
62 #define BV_TIMING_STROBE_READ_NS 37
63 #define BO_TIMING_RELAX 12
64 #define BM_TIMING_RELAX 0x0000f000
65 #define BV_TIMING_RELAX_NS 17
66 #define BO_TIMING_STROBE_PROG 0
67 #define BM_TIMING_STROBE_PROG 0x00000fff
68 #define BV_TIMING_STROBE_PROG_US 10
71 #define BM_READ_CTRL_READ_FUSE 0x00000001
73 #define BF(value, field) (((value) << BO_##field) & BM_##field)
75 #define WRITE_POSTAMBLE_US 2
77 #if defined(CONFIG_MX6) || defined(CONFIG_VF610)
78 #define FUSE_BANK_SIZE 0x80
81 #elif defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL)
86 #elif defined CONFIG_MX7
87 #define FUSE_BANK_SIZE 0x40
89 #elif defined(CONFIG_MX7ULP)
90 #define FUSE_BANK_SIZE 0x80
92 #elif defined(CONFIG_IMX8M)
93 #define FUSE_BANK_SIZE 0x40
100 #error "Unsupported architecture\n"
103 #if defined(CONFIG_MX6)
106 * There is a hole in shadow registers address map of size 0x100
107 * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX,
108 * iMX6UL, i.MX6ULL and i.MX6SLL.
109 * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
110 * we should account for this hole in address space.
112 * Similar hole exists between bank 14 and bank 15 of size
113 * 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX.
114 * Note: iMX6SL has only 0-7 banks and there is no hole.
115 * Note: iMX6UL doesn't have this one.
117 * This function is to covert user input to physical bank index.
118 * Only needed when read fuse, because we use register offset, so
119 * need to calculate real register offset.
120 * When write, no need to consider hole, always use the bank/word
121 * index from fuse map.
123 u32 fuse_bank_physical(int index)
127 if (is_mx6sl() || is_mx7ulp()) {
129 } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
130 if ((is_mx6ull() || is_mx6sll()) && index == 8)
134 phy_index = fuse_bank_physical(5) + (index - 6) + 3;
139 phy_index = fuse_bank_physical(14) + (index - 15) + 2;
141 phy_index = fuse_bank_physical(5) + (index - 6) + 3;
148 u32 fuse_word_physical(u32 bank, u32 word_index)
150 if (is_mx6ull() || is_mx6sll()) {
152 word_index = word_index + 4;
158 u32 fuse_bank_physical(int index)
163 u32 fuse_word_physical(u32 bank, u32 word_index)
170 static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
172 while (readl(®s->ctrl) & BM_CTRL_BUSY)
176 static void clear_error(struct ocotp_regs *regs)
178 writel(BM_CTRL_ERROR, ®s->ctrl_clr);
181 static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word,
182 int assert, const char *caller)
184 *regs = (struct ocotp_regs *)OCOTP_BASE_ADDR;
186 if (bank >= FUSE_BANKS ||
187 word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 ||
189 printf("mxc_ocotp %s(): Invalid argument\n", caller);
193 if (is_mx6ull() || is_mx6sll()) {
194 if ((bank == 7 || bank == 8) &&
195 word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 3) {
196 printf("mxc_ocotp %s(): Invalid argument\n", caller);
209 static int finish_access(struct ocotp_regs *regs, const char *caller)
213 err = !!(readl(®s->ctrl) & BM_CTRL_ERROR);
217 /* Need to power down the OTP memory */
218 writel(1, ®s->pdn);
221 printf("mxc_ocotp %s(): Access protect error\n", caller);
228 static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val,
231 return prepare_access(regs, bank, word, val != NULL, caller);
234 int fuse_read(u32 bank, u32 word, u32 *val)
236 struct ocotp_regs *regs;
241 ret = prepare_read(®s, bank, word, val, __func__);
245 phy_bank = fuse_bank_physical(bank);
246 phy_word = fuse_word_physical(bank, word);
248 *val = readl(®s->bank[phy_bank].fuse_regs[phy_word << 2]);
251 if (readl(®s->out_status) & BM_OUT_STATUS_DED) {
252 writel(BM_OUT_STATUS_DED, ®s->out_status_clr);
253 printf("mxc_ocotp %s(): fuse read wrong\n", __func__);
257 return finish_access(regs, __func__);
261 static void set_timing(struct ocotp_regs *regs)
267 ipg_clk = mxc_get_clock(MXC_IPG_CLK);
269 fsource = DIV_ROUND_UP((ipg_clk / 1000) * BV_TIMING_FSOURCE_NS,
271 prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_PROG_US, 1000000) + 1;
273 timing = BF(fsource, TIMING_FSOURCE) | BF(prog, TIMING_PROG);
275 clrsetbits_le32(®s->timing, BM_TIMING_FSOURCE | BM_TIMING_PROG,
278 #elif defined(CONFIG_MX7ULP)
279 static void set_timing(struct ocotp_regs *regs)
281 /* No timing set for MX7ULP */
285 static void set_timing(struct ocotp_regs *regs)
288 u32 relax, strobe_read, strobe_prog;
291 ipg_clk = mxc_get_clock(MXC_IPG_CLK);
293 relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1;
294 strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS,
295 1000000000) + 2 * (relax + 1) - 1;
296 strobe_prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_STROBE_PROG_US,
297 1000000) + 2 * (relax + 1) - 1;
299 timing = BF(strobe_read, TIMING_STROBE_READ) |
300 BF(relax, TIMING_RELAX) |
301 BF(strobe_prog, TIMING_STROBE_PROG);
303 clrsetbits_le32(®s->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX |
304 BM_TIMING_STROBE_PROG, timing);
308 static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
311 u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
314 #elif defined CONFIG_IMX8M
315 u32 addr = bank << 2 | word;
318 /* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */
319 if ((is_mx6ull() || is_mx6sll()) && (bank > 7)) {
323 addr = bank << 3 | word;
327 clrsetbits_le32(®s->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR,
328 BF(wr_unlock, CTRL_WR_UNLOCK) |
329 BF(addr, CTRL_ADDR));
332 int fuse_sense(u32 bank, u32 word, u32 *val)
334 struct ocotp_regs *regs;
337 if (is_imx8mq() && is_soc_rev(CHIP_REV_2_1)) {
338 printf("mxc_ocotp %s(): fuse sense is disabled\n", __func__);
342 ret = prepare_read(®s, bank, word, val, __func__);
346 setup_direct_access(regs, bank, word, false);
347 writel(BM_READ_CTRL_READ_FUSE, ®s->read_ctrl);
350 *val = readl((®s->read_fuse_data0) + (word << 2));
352 *val = readl(®s->read_fuse_data);
356 if (readl(®s->out_status) & BM_OUT_STATUS_DED) {
357 writel(BM_OUT_STATUS_DED, ®s->out_status_clr);
358 printf("mxc_ocotp %s(): fuse read wrong\n", __func__);
363 return finish_access(regs, __func__);
366 static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
373 /* Only bank 0 and 1 are redundancy mode, others are ECC mode */
374 if (bank != 0 && bank != 1) {
375 if ((soc_rev() < CHIP_REV_2_0) ||
376 ((soc_rev() >= CHIP_REV_2_0) &&
377 bank != 9 && bank != 10 && bank != 28)) {
378 ret = fuse_sense(bank, word, &val);
383 printf("mxc_ocotp: The word has been programmed, no more write\n");
390 return prepare_access(regs, bank, word, true, caller);
393 int fuse_prog(u32 bank, u32 word, u32 val)
395 struct ocotp_regs *regs;
398 ret = prepare_write(®s, bank, word, __func__);
402 setup_direct_access(regs, bank, word, true);
406 writel(0, ®s->data1);
407 writel(0, ®s->data2);
408 writel(0, ®s->data3);
409 writel(val, ®s->data0);
412 writel(val, ®s->data1);
413 writel(0, ®s->data2);
414 writel(0, ®s->data3);
415 writel(0, ®s->data0);
418 writel(0, ®s->data1);
419 writel(val, ®s->data2);
420 writel(0, ®s->data3);
421 writel(0, ®s->data0);
424 writel(0, ®s->data1);
425 writel(0, ®s->data2);
426 writel(val, ®s->data3);
427 writel(0, ®s->data0);
430 wait_busy(regs, BV_TIMING_PROG_US);
432 writel(val, ®s->data);
433 wait_busy(regs, BV_TIMING_STROBE_PROG_US);
435 udelay(WRITE_POSTAMBLE_US);
438 if (readl(®s->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) {
439 writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), ®s->out_status_clr);
440 printf("mxc_ocotp %s(): fuse write is failed\n", __func__);
445 return finish_access(regs, __func__);
448 int fuse_override(u32 bank, u32 word, u32 val)
450 struct ocotp_regs *regs;
455 ret = prepare_write(®s, bank, word, __func__);
459 phy_bank = fuse_bank_physical(bank);
460 phy_word = fuse_word_physical(bank, word);
462 writel(val, ®s->bank[phy_bank].fuse_regs[phy_word << 2]);
465 if (readl(®s->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) {
466 writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), ®s->out_status_clr);
467 printf("mxc_ocotp %s(): fuse write is failed\n", __func__);
472 return finish_access(regs, __func__);