2 * (C) Copyright 2013 ADVANSEE
3 * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
5 * Based on Dirk Behme's
6 * https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c,
7 * which is based on Freescale's
8 * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6,
10 * Copyright (C) 2011 Freescale Semiconductor, Inc.
12 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/errno.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/imx-regs.h>
22 #define BO_CTRL_WR_UNLOCK 16
23 #define BM_CTRL_WR_UNLOCK 0xffff0000
24 #define BV_CTRL_WR_UNLOCK_KEY 0x3e77
25 #define BM_CTRL_ERROR 0x00000200
26 #define BM_CTRL_BUSY 0x00000100
27 #define BO_CTRL_ADDR 0
28 #define BM_CTRL_ADDR 0x0000007f
30 #define BO_TIMING_STROBE_READ 16
31 #define BM_TIMING_STROBE_READ 0x003f0000
32 #define BV_TIMING_STROBE_READ_NS 37
33 #define BO_TIMING_RELAX 12
34 #define BM_TIMING_RELAX 0x0000f000
35 #define BV_TIMING_RELAX_NS 17
36 #define BO_TIMING_STROBE_PROG 0
37 #define BM_TIMING_STROBE_PROG 0x00000fff
38 #define BV_TIMING_STROBE_PROG_US 10
40 #define BM_READ_CTRL_READ_FUSE 0x00000001
42 #define BF(value, field) (((value) << BO_##field) & BM_##field)
44 #define WRITE_POSTAMBLE_US 2
46 static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
48 while (readl(®s->ctrl) & BM_CTRL_BUSY)
52 static void clear_error(struct ocotp_regs *regs)
54 writel(BM_CTRL_ERROR, ®s->ctrl_clr);
57 static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word,
58 int assert, const char *caller)
60 *regs = (struct ocotp_regs *)OCOTP_BASE_ADDR;
62 if (bank >= ARRAY_SIZE((*regs)->bank) ||
63 word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 ||
65 printf("mxc_ocotp %s(): Invalid argument\n", caller);
77 static int finish_access(struct ocotp_regs *regs, const char *caller)
81 err = !!(readl(®s->ctrl) & BM_CTRL_ERROR);
87 printf("mxc_ocotp %s(): Access protect error\n", caller);
94 static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val,
97 return prepare_access(regs, bank, word, val != NULL, caller);
100 int fuse_read(u32 bank, u32 word, u32 *val)
102 struct ocotp_regs *regs;
105 ret = prepare_read(®s, bank, word, val, __func__);
109 *val = readl(®s->bank[bank].fuse_regs[word << 2]);
111 return finish_access(regs, __func__);
114 static void set_timing(struct ocotp_regs *regs)
117 u32 relax, strobe_read, strobe_prog;
120 ipg_clk = mxc_get_clock(MXC_IPG_CLK);
122 relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1;
123 strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS,
124 1000000000) + 2 * (relax + 1) - 1;
125 strobe_prog = DIV_ROUND(ipg_clk * BV_TIMING_STROBE_PROG_US, 1000000) +
128 timing = BF(strobe_read, TIMING_STROBE_READ) |
129 BF(relax, TIMING_RELAX) |
130 BF(strobe_prog, TIMING_STROBE_PROG);
132 clrsetbits_le32(®s->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX |
133 BM_TIMING_STROBE_PROG, timing);
136 static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
139 u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
140 u32 addr = bank << 3 | word;
143 clrsetbits_le32(®s->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR,
144 BF(wr_unlock, CTRL_WR_UNLOCK) |
145 BF(addr, CTRL_ADDR));
148 int fuse_sense(u32 bank, u32 word, u32 *val)
150 struct ocotp_regs *regs;
153 ret = prepare_read(®s, bank, word, val, __func__);
157 setup_direct_access(regs, bank, word, false);
158 writel(BM_READ_CTRL_READ_FUSE, ®s->read_ctrl);
160 *val = readl(®s->read_fuse_data);
162 return finish_access(regs, __func__);
165 static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
168 return prepare_access(regs, bank, word, true, caller);
171 int fuse_prog(u32 bank, u32 word, u32 val)
173 struct ocotp_regs *regs;
176 ret = prepare_write(®s, bank, word, __func__);
180 setup_direct_access(regs, bank, word, true);
181 writel(val, ®s->data);
182 wait_busy(regs, BV_TIMING_STROBE_PROG_US);
183 udelay(WRITE_POSTAMBLE_US);
185 return finish_access(regs, __func__);
188 int fuse_override(u32 bank, u32 word, u32 val)
190 struct ocotp_regs *regs;
193 ret = prepare_write(®s, bank, word, __func__);
197 writel(val, ®s->bank[bank].fuse_regs[word << 2]);
199 return finish_access(regs, __func__);