drivers/misc/mei/pci-me.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
   4  * Intel Management Engine Interface (Intel MEI) Linux driver
   5  */
   6
   7 #include <linux/module.h>
   8 #include <linux/kernel.h>
   9 #include <linux/device.h>
  10 #include <linux/errno.h>
  11 #include <linux/types.h>
  12 #include <linux/pci.h>
  13 #include <linux/sched.h>
  14 #include <linux/interrupt.h>
  15
  16 #include <linux/pm_domain.h>
  17 #include <linux/pm_runtime.h>
  18
  19 #include <linux/mei.h>
  20
  21 #include "mei_dev.h"
  22 #include "client.h"
  23 #include "hw-me-regs.h"
  24 #include "hw-me.h"
  25
  26 /* mei_pci_tbl - PCI Device ID Table */
  27 static const struct pci_device_id mei_me_pci_tbl[] = {
  28         {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
  29         {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
  30         {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
  31         {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
  32         {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
  33         {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
  34         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
  35         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
  36         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
  37         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
  38         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
  39
  40         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
  41         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
  42         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
  43         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
  44         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
  45         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
  46         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
  47         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
  48         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
  49
  50         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
  51         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
  52         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
  53         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
  54
  55         {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
  56         {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
  57         {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
  58         {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
  59         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
  60         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
  61         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
  62         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)},
  63         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)},
  64         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
  65         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)},
  66         {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
  67         {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
  68
  69         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
  70         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
  71         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)},
  72         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)},
  73         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)},
  74         {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)},
  75
  76         {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
  77         {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
  78
  79         {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
  80
  81         {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
  82
  83         {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
  84         {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
  85         {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)},
  86
  87         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
  88         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
  89         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)},
  90         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)},
  91
  92         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
  93         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
  94         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)},
  95         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)},
  96         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)},
  97
  98         {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
  99         {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_N, MEI_ME_PCH12_CFG)},
 100
 101         {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)},
 102         {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)},
 103
 104         {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)},
 105
 106         {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)},
 107         {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},
 108
 109         {MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)},
 110
 111         {MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)},
 112
 113         {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)},
 114         {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)},
 115         {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)},
 116         {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_N, MEI_ME_PCH15_CFG)},
 117
 118         {MEI_PCI_DEVICE(MEI_DEV_ID_RPL_S, MEI_ME_PCH15_CFG)},
 119
 120         /* required last entry */
 121         {0, }
 122 };
 123
 124 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
 125
 126 #ifdef CONFIG_PM
 127 static inline void mei_me_set_pm_domain(struct mei_device *dev);
 128 static inline void mei_me_unset_pm_domain(struct mei_device *dev);
 129 #else
 130 static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
 131 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
 132 #endif /* CONFIG_PM */
 133
 134 static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val)
 135 {
 136         struct pci_dev *pdev = to_pci_dev(dev->dev);
 137
 138         return pci_read_config_dword(pdev, where, val);
 139 }
 140
 141 /**
 142  * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
 143  *
 144  * @pdev: PCI device structure
 145  * @cfg: per generation config
 146  *
 147  * Return: true if ME Interface is valid, false otherwise
 148  */
 149 static bool mei_me_quirk_probe(struct pci_dev *pdev,
 150                                 const struct mei_cfg *cfg)
 151 {
 152         if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
 153                 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
 154                 return false;
 155         }
 156
 157         return true;
 158 }
 159
 160 /**
 161  * mei_me_probe - Device Initialization Routine
 162  *
 163  * @pdev: PCI device structure
 164  * @ent: entry in kcs_pci_tbl
 165  *
 166  * Return: 0 on success, <0 on failure.
 167  */
 168 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 169 {
 170         const struct mei_cfg *cfg;
 171         struct mei_device *dev;
 172         struct mei_me_hw *hw;
 173         unsigned int irqflags;
 174         int err;
 175
 176         cfg = mei_me_get_cfg(ent->driver_data);
 177         if (!cfg)
 178                 return -ENODEV;
 179
 180         if (!mei_me_quirk_probe(pdev, cfg))
 181                 return -ENODEV;
 182
 183         /* enable pci dev */
 184         err = pcim_enable_device(pdev);
 185         if (err) {
 186                 dev_err(&pdev->dev, "failed to enable pci device.\n");
 187                 goto end;
 188         }
 189         /* set PCI host mastering  */
 190         pci_set_master(pdev);
 191         /* pci request regions and mapping IO device memory for mei driver */
 192         err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
 193         if (err) {
 194                 dev_err(&pdev->dev, "failed to get pci regions.\n");
 195                 goto end;
 196         }
 197
 198         if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
 199             dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
 200
 201                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
 202                 if (err)
 203                         err = dma_set_coherent_mask(&pdev->dev,
 204                                                     DMA_BIT_MASK(32));
 205         }
 206         if (err) {
 207                 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
 208                 goto end;
 209         }
 210
 211         /* allocates and initializes the mei dev structure */
 212         dev = mei_me_dev_init(&pdev->dev, cfg);
 213         if (!dev) {
 214                 err = -ENOMEM;
 215                 goto end;
 216         }
 217         hw = to_me_hw(dev);
 218         hw->mem_addr = pcim_iomap_table(pdev)[0];
 219         hw->read_fws = mei_me_read_fws;
 220
 221         pci_enable_msi(pdev);
 222
 223         hw->irq = pdev->irq;
 224
 225          /* request and enable interrupt */
 226         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
 227
 228         err = request_threaded_irq(pdev->irq,
 229                         mei_me_irq_quick_handler,
 230                         mei_me_irq_thread_handler,
 231                         irqflags, KBUILD_MODNAME, dev);
 232         if (err) {
 233                 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
 234                        pdev->irq);
 235                 goto end;
 236         }
 237
 238         if (mei_start(dev)) {
 239                 dev_err(&pdev->dev, "init hw failure.\n");
 240                 err = -ENODEV;
 241                 goto release_irq;
 242         }
 243
 244         pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
 245         pm_runtime_use_autosuspend(&pdev->dev);
 246
 247         err = mei_register(dev, &pdev->dev);
 248         if (err)
 249                 goto stop;
 250
 251         pci_set_drvdata(pdev, dev);
 252
 253         /*
 254          * MEI requires to resume from runtime suspend mode
 255          * in order to perform link reset flow upon system suspend.
 256          */
 257         dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
 258
 259         /*
 260          * ME maps runtime suspend/resume to D0i states,
 261          * hence we need to go around native PCI runtime service which
 262          * eventually brings the device into D3cold/hot state,
 263          * but the mei device cannot wake up from D3 unlike from D0i3.
 264          * To get around the PCI device native runtime pm,
 265          * ME uses runtime pm domain handlers which take precedence
 266          * over the driver's pm handlers.
 267          */
 268         mei_me_set_pm_domain(dev);
 269
 270         if (mei_pg_is_enabled(dev)) {
 271                 pm_runtime_put_noidle(&pdev->dev);
 272                 if (hw->d0i3_supported)
 273                         pm_runtime_allow(&pdev->dev);
 274         }
 275
 276         dev_dbg(&pdev->dev, "initialization successful.\n");
 277
 278         return 0;
 279
 280 stop:
 281         mei_stop(dev);
 282 release_irq:
 283         mei_cancel_work(dev);
 284         mei_disable_interrupts(dev);
 285         free_irq(pdev->irq, dev);
 286 end:
 287         dev_err(&pdev->dev, "initialization failed.\n");
 288         return err;
 289 }
 290
 291 /**
 292  * mei_me_shutdown - Device Removal Routine
 293  *
 294  * @pdev: PCI device structure
 295  *
 296  * mei_me_shutdown is called from the reboot notifier
 297  * it's a simplified version of remove so we go down
 298  * faster.
 299  */
 300 static void mei_me_shutdown(struct pci_dev *pdev)
 301 {
 302         struct mei_device *dev;
 303
 304         dev = pci_get_drvdata(pdev);
 305         if (!dev)
 306                 return;
 307
 308         dev_dbg(&pdev->dev, "shutdown\n");
 309         mei_stop(dev);
 310
 311         mei_me_unset_pm_domain(dev);
 312
 313         mei_disable_interrupts(dev);
 314         free_irq(pdev->irq, dev);
 315 }
 316
 317 /**
 318  * mei_me_remove - Device Removal Routine
 319  *
 320  * @pdev: PCI device structure
 321  *
 322  * mei_me_remove is called by the PCI subsystem to alert the driver
 323  * that it should release a PCI device.
 324  */
 325 static void mei_me_remove(struct pci_dev *pdev)
 326 {
 327         struct mei_device *dev;
 328
 329         dev = pci_get_drvdata(pdev);
 330         if (!dev)
 331                 return;
 332
 333         if (mei_pg_is_enabled(dev))
 334                 pm_runtime_get_noresume(&pdev->dev);
 335
 336         dev_dbg(&pdev->dev, "stop\n");
 337         mei_stop(dev);
 338
 339         mei_me_unset_pm_domain(dev);
 340
 341         mei_disable_interrupts(dev);
 342
 343         free_irq(pdev->irq, dev);
 344
 345         mei_deregister(dev);
 346 }
 347
 348 #ifdef CONFIG_PM_SLEEP
 349 static int mei_me_pci_suspend(struct device *device)
 350 {
 351         struct pci_dev *pdev = to_pci_dev(device);
 352         struct mei_device *dev = pci_get_drvdata(pdev);
 353
 354         if (!dev)
 355                 return -ENODEV;
 356
 357         dev_dbg(&pdev->dev, "suspend\n");
 358
 359         mei_stop(dev);
 360
 361         mei_disable_interrupts(dev);
 362
 363         free_irq(pdev->irq, dev);
 364         pci_disable_msi(pdev);
 365
 366         return 0;
 367 }
 368
 369 static int mei_me_pci_resume(struct device *device)
 370 {
 371         struct pci_dev *pdev = to_pci_dev(device);
 372         struct mei_device *dev;
 373         unsigned int irqflags;
 374         int err;
 375
 376         dev = pci_get_drvdata(pdev);
 377         if (!dev)
 378                 return -ENODEV;
 379
 380         pci_enable_msi(pdev);
 381
 382         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
 383
 384         /* request and enable interrupt */
 385         err = request_threaded_irq(pdev->irq,
 386                         mei_me_irq_quick_handler,
 387                         mei_me_irq_thread_handler,
 388                         irqflags, KBUILD_MODNAME, dev);
 389
 390         if (err) {
 391                 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
 392                                 pdev->irq);
 393                 return err;
 394         }
 395
 396         err = mei_restart(dev);
 397         if (err)
 398                 return err;
 399
 400         /* Start timer if stopped in suspend */
 401         schedule_delayed_work(&dev->timer_work, HZ);
 402
 403         return 0;
 404 }
 405 #endif /* CONFIG_PM_SLEEP */
 406
 407 #ifdef CONFIG_PM
 408 static int mei_me_pm_runtime_idle(struct device *device)
 409 {
 410         struct mei_device *dev;
 411
 412         dev_dbg(device, "rpm: me: runtime_idle\n");
 413
 414         dev = dev_get_drvdata(device);
 415         if (!dev)
 416                 return -ENODEV;
 417         if (mei_write_is_idle(dev))
 418                 pm_runtime_autosuspend(device);
 419
 420         return -EBUSY;
 421 }
 422
 423 static int mei_me_pm_runtime_suspend(struct device *device)
 424 {
 425         struct mei_device *dev;
 426         int ret;
 427
 428         dev_dbg(device, "rpm: me: runtime suspend\n");
 429
 430         dev = dev_get_drvdata(device);
 431         if (!dev)
 432                 return -ENODEV;
 433
 434         mutex_lock(&dev->device_lock);
 435
 436         if (mei_write_is_idle(dev))
 437                 ret = mei_me_pg_enter_sync(dev);
 438         else
 439                 ret = -EAGAIN;
 440
 441         mutex_unlock(&dev->device_lock);
 442
 443         dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);
 444
 445         if (ret && ret != -EAGAIN)
 446                 schedule_work(&dev->reset_work);
 447
 448         return ret;
 449 }
 450
 451 static int mei_me_pm_runtime_resume(struct device *device)
 452 {
 453         struct mei_device *dev;
 454         int ret;
 455
 456         dev_dbg(device, "rpm: me: runtime resume\n");
 457
 458         dev = dev_get_drvdata(device);
 459         if (!dev)
 460                 return -ENODEV;
 461
 462         mutex_lock(&dev->device_lock);
 463
 464         ret = mei_me_pg_exit_sync(dev);
 465
 466         mutex_unlock(&dev->device_lock);
 467
 468         dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret);
 469
 470         if (ret)
 471                 schedule_work(&dev->reset_work);
 472
 473         return ret;
 474 }
 475
 476 /**
 477  * mei_me_set_pm_domain - fill and set pm domain structure for device
 478  *
 479  * @dev: mei_device
 480  */
 481 static inline void mei_me_set_pm_domain(struct mei_device *dev)
 482 {
 483         struct pci_dev *pdev  = to_pci_dev(dev->dev);
 484
 485         if (pdev->dev.bus && pdev->dev.bus->pm) {
 486                 dev->pg_domain.ops = *pdev->dev.bus->pm;
 487
 488                 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
 489                 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
 490                 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
 491
 492                 dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
 493         }
 494 }
 495
 496 /**
 497  * mei_me_unset_pm_domain - clean pm domain structure for device
 498  *
 499  * @dev: mei_device
 500  */
 501 static inline void mei_me_unset_pm_domain(struct mei_device *dev)
 502 {
 503         /* stop using pm callbacks if any */
 504         dev_pm_domain_set(dev->dev, NULL);
 505 }
 506
 507 static const struct dev_pm_ops mei_me_pm_ops = {
 508         SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
 509                                 mei_me_pci_resume)
 510         SET_RUNTIME_PM_OPS(
 511                 mei_me_pm_runtime_suspend,
 512                 mei_me_pm_runtime_resume,
 513                 mei_me_pm_runtime_idle)
 514 };
 515
 516 #define MEI_ME_PM_OPS   (&mei_me_pm_ops)
 517 #else
 518 #define MEI_ME_PM_OPS   NULL
 519 #endif /* CONFIG_PM */
 520 /*
 521  *  PCI driver structure
 522  */
 523 static struct pci_driver mei_me_driver = {
 524         .name = KBUILD_MODNAME,
 525         .id_table = mei_me_pci_tbl,
 526         .probe = mei_me_probe,
 527         .remove = mei_me_remove,
 528         .shutdown = mei_me_shutdown,
 529         .driver.pm = MEI_ME_PM_OPS,
 530         .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 531 };
 532
 533 module_pci_driver(mei_me_driver);
 534
 535 MODULE_AUTHOR("Intel Corporation");
 536 MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
 537 MODULE_LICENSE("GPL v2");