1 // SPDX-License-Identifier: GPL-2.0
5 * Peng Fan <peng.fan@nxp.com>
10 #include <asm/global_data.h>
15 #include <dm/device-internal.h>
16 #include <asm/arch/sci/sci.h>
17 #include <linux/bitops.h>
18 #include <linux/iopoll.h>
21 DECLARE_GLOBAL_DATA_PTR;
34 #define MU_CR_GIE_MASK 0xF0000000u
35 #define MU_CR_RIE_MASK 0xF000000u
36 #define MU_CR_GIR_MASK 0xF0000u
37 #define MU_CR_TIE_MASK 0xF00000u
38 #define MU_CR_F_MASK 0x7u
39 #define MU_SR_TE0_MASK BIT(23)
40 #define MU_SR_RF0_MASK BIT(27)
44 static inline void mu_hal_init(struct mu_type *base)
46 /* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */
47 clrbits_le32(&base->cr, MU_CR_GIE_MASK | MU_CR_RIE_MASK |
48 MU_CR_TIE_MASK | MU_CR_GIR_MASK | MU_CR_F_MASK);
51 static int mu_hal_sendmsg(struct mu_type *base, u32 reg_index, u32 msg)
53 u32 mask = MU_SR_TE0_MASK >> reg_index;
57 assert(reg_index < MU_TR_COUNT);
59 /* Wait TX register to be empty. */
60 ret = readl_poll_timeout(&base->sr, val, val & mask, 10000);
62 printf("%s timeout\n", __func__);
66 writel(msg, &base->tr[reg_index]);
71 static int mu_hal_receivemsg(struct mu_type *base, u32 reg_index, u32 *msg)
73 u32 mask = MU_SR_RF0_MASK >> reg_index;
77 assert(reg_index < MU_TR_COUNT);
79 /* Wait RX register to be full. */
80 ret = readl_poll_timeout(&base->sr, val, val & mask, 1000000);
82 printf("%s timeout\n", __func__);
86 *msg = readl(&base->rr[reg_index]);
91 static int sc_ipc_read(struct mu_type *base, void *data)
93 struct sc_rpc_msg_s *msg = (struct sc_rpc_msg_s *)data;
100 /* Read first word */
101 ret = mu_hal_receivemsg(base, 0, (u32 *)msg);
107 if (msg->size > SC_RPC_MAX_MSG) {
112 /* Read remaining words */
113 while (count < msg->size) {
114 ret = mu_hal_receivemsg(base, count % MU_RR_COUNT,
115 &msg->DATA.u32[count - 1]);
124 static int sc_ipc_write(struct mu_type *base, void *data)
126 struct sc_rpc_msg_s *msg = (struct sc_rpc_msg_s *)data;
134 if (msg->size > SC_RPC_MAX_MSG)
137 /* Write first word */
138 ret = mu_hal_sendmsg(base, 0, *((u32 *)msg));
143 /* Write remaining words */
144 while (count < msg->size) {
145 ret = mu_hal_sendmsg(base, count % MU_TR_COUNT,
146 msg->DATA.u32[count - 1]);
156 * Note the function prototype use msgid as the 2nd parameter, here
157 * we take it as no_resp.
159 static int imx8_scu_call(struct udevice *dev, int no_resp, void *tx_msg,
160 int tx_size, void *rx_msg, int rx_size)
162 struct imx8_scu *plat = dev_get_plat(dev);
166 /* Expect tx_msg, rx_msg are the same value */
167 if (rx_msg && tx_msg != rx_msg)
168 printf("tx_msg %p, rx_msg %p\n", tx_msg, rx_msg);
170 ret = sc_ipc_write(plat->base, tx_msg);
174 ret = sc_ipc_read(plat->base, rx_msg);
179 result = RPC_R8((struct sc_rpc_msg_s *)tx_msg);
181 return sc_err_to_linux(result);
184 static int imx8_scu_probe(struct udevice *dev)
186 struct imx8_scu *plat = dev_get_plat(dev);
189 debug("%s(dev=%p) (plat=%p)\n", __func__, dev, plat);
191 addr = dev_read_addr(dev);
192 if (addr == FDT_ADDR_T_NONE)
195 #ifdef CONFIG_SPL_BUILD
196 plat->base = (struct mu_type *)CONFIG_MU_BASE_SPL;
198 plat->base = (struct mu_type *)addr;
201 /* U-Boot not enable interrupts, so need to enable RX interrupts */
202 mu_hal_init(plat->base);
204 gd->arch.scu_dev = dev;
209 static int imx8_scu_remove(struct udevice *dev)
214 static int imx8_scu_bind(struct udevice *dev)
217 struct udevice *child;
220 debug("%s(dev=%p)\n", __func__, dev);
221 ofnode_for_each_subnode(node, dev_ofnode(dev)) {
222 ret = lists_bind_fdt(dev, node, &child, true);
225 debug("bind child dev %s\n", child->name);
231 static struct misc_ops imx8_scu_ops = {
232 .call = imx8_scu_call,
235 static const struct udevice_id imx8_scu_ids[] = {
236 { .compatible = "fsl,imx8qxp-mu" },
237 { .compatible = "fsl,imx8-mu" },
241 U_BOOT_DRIVER(imx8_scu) = {
244 .of_match = imx8_scu_ids,
245 .probe = imx8_scu_probe,
246 .bind = imx8_scu_bind,
247 .remove = imx8_scu_remove,
248 .ops = &imx8_scu_ops,
249 .plat_auto = sizeof(struct imx8_scu),
250 .flags = DM_FLAG_PRE_RELOC,