drivers/misc/ihs_fpga.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2017
   4  * Mario Six,  Guntermann & Drunck GmbH, mario.six@gdsys.cc
   5  *
   6  * based on the ioep-fpga driver, which is
   7  *
   8  * (C) Copyright 2014
   9  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
  10  */
  11
  12 #include <common.h>
  13 #include <dm.h>
  14 #include <log.h>
  15 #include <regmap.h>
  16 #include <asm/gpio.h>
  17
  18 #include "ihs_fpga.h"
  19
  20 /**
  21  * struct ihs_fpga_priv - Private data structure for IHS FPGA driver
  22  * @map:        Register map for the FPGA's own register space
  23  * @reset_gpio: GPIO to start FPGA reconfiguration
  24  * @done_gpio:  GPOI to read the 'ready' status of the FPGA
  25  */
  26 struct ihs_fpga_priv {
  27         struct regmap *map;
  28         struct gpio_desc reset_gpio;
  29         struct gpio_desc done_gpio;
  30 };
  31
  32 /* Test pattern for reflection test */
  33 const u16 REFLECTION_TESTPATTERN = 0xdead;
  34 /* Delay (in ms) for each round in the reflection test */
  35 const uint REFLECTION_TEST_DELAY = 100;
  36 /* Maximum number of rounds in the reflection test */
  37 const uint REFLECTION_TEST_ROUNDS = 5;
  38 /* Delay (in ms) for each round waiting for the FPGA's done GPIO */
  39 const uint FPGA_DONE_WAIT_DELAY = 100;
  40 /* Maximum number of rounds for waiting for the FPGA's done GPIO */
  41 const uint FPGA_DONE_WAIT_ROUND = 5;
  42
  43 /**
  44  * enum pcb_video_type - Video type of the PCB
  45  * @PCB_DVI_SL:     Video type is DVI single-link
  46  * @PCB_DP_165MPIX: Video type is DisplayPort (165Mpix)
  47  * @PCB_DP_300MPIX: Video type is DisplayPort (300Mpix)
  48  * @PCB_HDMI:       Video type is HDMI
  49  * @PCB_DP_1_2:     Video type is DisplayPort 1.2
  50  * @PCB_HDMI_2_0:   Video type is HDMI 2.0
  51  */
  52 enum pcb_video_type {
  53         PCB_DVI_SL,
  54         PCB_DP_165MPIX,
  55         PCB_DP_300MPIX,
  56         PCB_HDMI,
  57         PCB_DP_1_2,
  58         PCB_HDMI_2_0,
  59 };
  60
  61 /**
  62  * enum pcb_transmission_type - Transmission type of the PCB
  63  * @PCB_CAT_1G:    Transmission type is 1G Ethernet
  64  * @PCB_FIBER_3G:  Transmission type is 3G Fiber
  65  * @PCB_CAT_10G:   Transmission type is 10G Ethernet
  66  * @PCB_FIBER_10G: Transmission type is 10G Fiber
  67  */
  68 enum pcb_transmission_type {
  69         PCB_CAT_1G,
  70         PCB_FIBER_3G,
  71         PCB_CAT_10G,
  72         PCB_FIBER_10G,
  73 };
  74
  75 /**
  76  * enum carrier_speed - Speed of the FPGA's carrier
  77  * @CARRIER_SPEED_1G:   The carrier speed is 1G
  78  * @CARRIER_SPEED_2_5G: The carrier speed is 2.5G
  79  * @CARRIER_SPEED_3G:   The carrier speed is 3G
  80  * @CARRIER_SPEED_10G:  The carrier speed is 10G
  81  */
  82 enum carrier_speed {
  83         CARRIER_SPEED_1G,
  84         CARRIER_SPEED_3G,
  85         CARRIER_SPEED_2_5G = CARRIER_SPEED_3G,
  86         CARRIER_SPEED_10G,
  87 };
  88
  89 /**
  90  * enum ram_config - FPGA's RAM configuration
  91  * @RAM_DDR2_32BIT_295MBPS:  DDR2 32 bit at 295Mb/s
  92  * @RAM_DDR3_32BIT_590MBPS:  DDR3 32 bit at 590Mb/s
  93  * @RAM_DDR3_48BIT_590MBPS:  DDR3 48 bit at 590Mb/s
  94  * @RAM_DDR3_64BIT_1800MBPS: DDR3 64 bit at 1800Mb/s
  95  * @RAM_DDR3_48BIT_1800MBPS: DDR3 48 bit at 1800Mb/s
  96  */
  97 enum ram_config {
  98         RAM_DDR2_32BIT_295MBPS,
  99         RAM_DDR3_32BIT_590MBPS,
 100         RAM_DDR3_48BIT_590MBPS,
 101         RAM_DDR3_64BIT_1800MBPS,
 102         RAM_DDR3_48BIT_1800MBPS,
 103 };
 104
 105 /**
 106  * enum sysclock - Speed of the FPGA's system clock
 107  * @SYSCLK_147456: System clock is 147.456 MHz
 108  */
 109 enum sysclock {
 110         SYSCLK_147456,
 111 };
 112
 113 /**
 114  * struct fpga_versions - Data read from the versions register
 115  * @video_channel:         Is the FPGA for a video channel (true) or main
 116  *                         channel (false) device?
 117  * @con_side:              Is the FPGA for a CON (true) or a CPU (false) device?
 118  * @pcb_video_type:        Defines for whch video type the FPGA is configured
 119  * @pcb_transmission_type: Defines for which transmission type the FPGA is
 120  *                         configured
 121  * @hw_version:            Hardware version of the FPGA
 122  */
 123 struct fpga_versions {
 124         bool video_channel;
 125         bool con_side;
 126         enum pcb_video_type pcb_video_type;
 127         enum pcb_transmission_type pcb_transmission_type;
 128         unsigned int hw_version;
 129 };
 130
 131 /**
 132  * struct fpga_features - Data read from the features register
 133  * @video_channels:     Number of video channels supported
 134  * @carriers:           Number of carrier channels supported
 135  * @carrier_speed:      Speed of carriers
 136  * @ram_config:         RAM configuration of FPGA
 137  * @sysclock:           System clock speed of FPGA
 138  * @pcm_tx:             Support for PCM transmission
 139  * @pcm_rx:             Support for PCM reception
 140  * @spdif_tx:           Support for SPDIF audio transmission
 141  * @spdif_rx:           Support for SPDIF audio reception
 142  * @usb2:               Support for transparent USB2.0
 143  * @rs232:              Support for bidirectional RS232
 144  * @compression_type1:  Support for compression type 1
 145  * @compression_type2:  Support for compression type 2
 146  * @compression_type3:  Support for compression type 3
 147  * @interlace:          Support for interlace image formats
 148  * @osd:                Support for a OSD
 149  * @compression_pipes:  Number of compression pipes supported
 150  */
 151 struct fpga_features {
 152         u8 video_channels;
 153         u8 carriers;
 154         enum carrier_speed carrier_speed;
 155         enum ram_config ram_config;
 156         enum sysclock sysclock;
 157         bool pcm_tx;
 158         bool pcm_rx;
 159         bool spdif_tx;
 160         bool spdif_rx;
 161         bool usb2;
 162         bool rs232;
 163         bool compression_type1;
 164         bool compression_type2;
 165         bool compression_type3;
 166         bool interlace;
 167         bool osd;
 168         bool compression_pipes;
 169 };
 170
 171 #ifdef CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM
 172
 173 /**
 174  * get_versions() - Fill structure with info from version register.
 175  * @dev:      FPGA device to be queried for information
 176  * @versions: Pointer to the structure to fill with information from the
 177  *            versions register
 178  * Return: 0
 179  */
 180 static int get_versions(struct udevice *dev, struct fpga_versions *versions)
 181 {
 182         struct ihs_fpga_priv *priv = dev_get_priv(dev);
 183         enum {
 184                 VERSIONS_FPGA_VIDEO_CHANNEL = BIT(12),
 185                 VERSIONS_FPGA_CON_SIDE = BIT(13),
 186                 VERSIONS_FPGA_SC = BIT(14),
 187                 VERSIONS_PCB_CON = BIT(9),
 188                 VERSIONS_PCB_SC = BIT(8),
 189                 VERSIONS_PCB_VIDEO_MASK = 0x3 << 6,
 190                 VERSIONS_PCB_VIDEO_DP_1_2 = 0x0 << 6,
 191                 VERSIONS_PCB_VIDEO_HDMI_2_0 = 0x1 << 6,
 192                 VERSIONS_PCB_TRANSMISSION_MASK = 0x3 << 4,
 193                 VERSIONS_PCB_TRANSMISSION_FIBER_10G = 0x0 << 4,
 194                 VERSIONS_PCB_TRANSMISSION_CAT_10G = 0x1 << 4,
 195                 VERSIONS_PCB_TRANSMISSION_FIBER_3G = 0x2 << 4,
 196                 VERSIONS_PCB_TRANSMISSION_CAT_1G = 0x3 << 4,
 197                 VERSIONS_HW_VER_MASK = 0xf << 0,
 198         };
 199         u16 raw_versions;
 200
 201         memset(versions, 0, sizeof(struct fpga_versions));
 202
 203         ihs_fpga_get(priv->map, versions, &raw_versions);
 204
 205         versions->video_channel = raw_versions & VERSIONS_FPGA_VIDEO_CHANNEL;
 206         versions->con_side = raw_versions & VERSIONS_FPGA_CON_SIDE;
 207
 208         switch (raw_versions & VERSIONS_PCB_VIDEO_MASK) {
 209         case VERSIONS_PCB_VIDEO_DP_1_2:
 210                 versions->pcb_video_type = PCB_DP_1_2;
 211                 break;
 212
 213         case VERSIONS_PCB_VIDEO_HDMI_2_0:
 214                 versions->pcb_video_type = PCB_HDMI_2_0;
 215                 break;
 216         }
 217
 218         switch (raw_versions & VERSIONS_PCB_TRANSMISSION_MASK) {
 219         case VERSIONS_PCB_TRANSMISSION_FIBER_10G:
 220                 versions->pcb_transmission_type = PCB_FIBER_10G;
 221                 break;
 222
 223         case VERSIONS_PCB_TRANSMISSION_CAT_10G:
 224                 versions->pcb_transmission_type = PCB_CAT_10G;
 225                 break;
 226
 227         case VERSIONS_PCB_TRANSMISSION_FIBER_3G:
 228                 versions->pcb_transmission_type = PCB_FIBER_3G;
 229                 break;
 230
 231         case VERSIONS_PCB_TRANSMISSION_CAT_1G:
 232                 versions->pcb_transmission_type = PCB_CAT_1G;
 233                 break;
 234         }
 235
 236         versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
 237
 238         return 0;
 239 }
 240
 241 /**
 242  * get_features() - Fill structure with info from features register.
 243  * @dev:      FPGA device to be queried for information
 244  * @features: Pointer to the structure to fill with information from the
 245  *            features register
 246  * Return: 0
 247  */
 248 static int get_features(struct udevice *dev, struct fpga_features *features)
 249 {
 250         struct ihs_fpga_priv *priv = dev_get_priv(dev);
 251         enum {
 252                 FEATURE_SPDIF_RX = BIT(15),
 253                 FEATURE_SPDIF_TX = BIT(14),
 254                 FEATURE_PCM_RX = BIT(13),
 255                 FEATURE_PCM_TX = BIT(12),
 256                 FEATURE_RAM_MASK = GENMASK(11, 8),
 257                 FEATURE_RAM_DDR2_32BIT_295MBPS = 0x0 << 8,
 258                 FEATURE_RAM_DDR3_32BIT_590MBPS = 0x1 << 8,
 259                 FEATURE_RAM_DDR3_48BIT_590MBPS = 0x2 << 8,
 260                 FEATURE_RAM_DDR3_64BIT_1800MBPS = 0x3 << 8,
 261                 FEATURE_RAM_DDR3_48BIT_1800MBPS = 0x4 << 8,
 262                 FEATURE_CARRIER_SPEED_MASK = GENMASK(7, 6),
 263                 FEATURE_CARRIER_SPEED_1G = 0x0 << 6,
 264                 FEATURE_CARRIER_SPEED_2_5G = 0x1 << 6,
 265                 FEATURE_CARRIER_SPEED_10G = 0x2 << 6,
 266                 FEATURE_CARRIERS_MASK = GENMASK(5, 4),
 267                 FEATURE_CARRIERS_0 = 0x0 << 4,
 268                 FEATURE_CARRIERS_1 = 0x1 << 4,
 269                 FEATURE_CARRIERS_2 = 0x2 << 4,
 270                 FEATURE_CARRIERS_4 = 0x3 << 4,
 271                 FEATURE_USB2 = BIT(3),
 272                 FEATURE_VIDEOCHANNELS_MASK = GENMASK(2, 0),
 273                 FEATURE_VIDEOCHANNELS_0 = 0x0 << 0,
 274                 FEATURE_VIDEOCHANNELS_1 = 0x1 << 0,
 275                 FEATURE_VIDEOCHANNELS_1_1 = 0x2 << 0,
 276                 FEATURE_VIDEOCHANNELS_2 = 0x3 << 0,
 277         };
 278
 279         enum {
 280                 EXT_FEATURE_OSD = BIT(15),
 281                 EXT_FEATURE_ETHERNET = BIT(9),
 282                 EXT_FEATURE_INTERLACE = BIT(8),
 283                 EXT_FEATURE_RS232 = BIT(7),
 284                 EXT_FEATURE_COMPRESSION_PERF_MASK = GENMASK(6, 4),
 285                 EXT_FEATURE_COMPRESSION_PERF_1X = 0x0 << 4,
 286                 EXT_FEATURE_COMPRESSION_PERF_2X = 0x1 << 4,
 287                 EXT_FEATURE_COMPRESSION_PERF_4X = 0x2 << 4,
 288                 EXT_FEATURE_COMPRESSION_TYPE1 = BIT(0),
 289                 EXT_FEATURE_COMPRESSION_TYPE2 = BIT(1),
 290                 EXT_FEATURE_COMPRESSION_TYPE3 = BIT(2),
 291         };
 292
 293         u16 raw_features;
 294         u16 raw_extended_features;
 295
 296         memset(features, 0, sizeof(struct fpga_features));
 297
 298         ihs_fpga_get(priv->map, features, &raw_features);
 299         ihs_fpga_get(priv->map, extended_features, &raw_extended_features);
 300
 301         switch (raw_features & FEATURE_VIDEOCHANNELS_MASK) {
 302         case FEATURE_VIDEOCHANNELS_0:
 303                 features->video_channels = 0;
 304                 break;
 305
 306         case FEATURE_VIDEOCHANNELS_1:
 307                 features->video_channels = 1;
 308                 break;
 309
 310         case FEATURE_VIDEOCHANNELS_1_1:
 311         case FEATURE_VIDEOCHANNELS_2:
 312                 features->video_channels = 2;
 313                 break;
 314         };
 315
 316         switch (raw_features & FEATURE_CARRIERS_MASK) {
 317         case FEATURE_CARRIERS_0:
 318                 features->carriers = 0;
 319                 break;
 320
 321         case FEATURE_CARRIERS_1:
 322                 features->carriers = 1;
 323                 break;
 324
 325         case FEATURE_CARRIERS_2:
 326                 features->carriers = 2;
 327                 break;
 328
 329         case FEATURE_CARRIERS_4:
 330                 features->carriers = 4;
 331                 break;
 332         }
 333
 334         switch (raw_features & FEATURE_CARRIER_SPEED_MASK) {
 335         case FEATURE_CARRIER_SPEED_1G:
 336                 features->carrier_speed = CARRIER_SPEED_1G;
 337                 break;
 338         case FEATURE_CARRIER_SPEED_2_5G:
 339                 features->carrier_speed = CARRIER_SPEED_2_5G;
 340                 break;
 341         case FEATURE_CARRIER_SPEED_10G:
 342                 features->carrier_speed = CARRIER_SPEED_10G;
 343                 break;
 344         }
 345
 346         switch (raw_features & FEATURE_RAM_MASK) {
 347         case FEATURE_RAM_DDR2_32BIT_295MBPS:
 348                 features->ram_config = RAM_DDR2_32BIT_295MBPS;
 349                 break;
 350
 351         case FEATURE_RAM_DDR3_32BIT_590MBPS:
 352                 features->ram_config = RAM_DDR3_32BIT_590MBPS;
 353                 break;
 354
 355         case FEATURE_RAM_DDR3_48BIT_590MBPS:
 356                 features->ram_config = RAM_DDR3_48BIT_590MBPS;
 357                 break;
 358
 359         case FEATURE_RAM_DDR3_64BIT_1800MBPS:
 360                 features->ram_config = RAM_DDR3_64BIT_1800MBPS;
 361                 break;
 362
 363         case FEATURE_RAM_DDR3_48BIT_1800MBPS:
 364                 features->ram_config = RAM_DDR3_48BIT_1800MBPS;
 365                 break;
 366         }
 367
 368         features->pcm_tx = raw_features & FEATURE_PCM_TX;
 369         features->pcm_rx = raw_features & FEATURE_PCM_RX;
 370         features->spdif_tx = raw_features & FEATURE_SPDIF_TX;
 371         features->spdif_rx = raw_features & FEATURE_SPDIF_RX;
 372         features->usb2 = raw_features & FEATURE_USB2;
 373         features->rs232 = raw_extended_features & EXT_FEATURE_RS232;
 374         features->compression_type1 = raw_extended_features &
 375                                         EXT_FEATURE_COMPRESSION_TYPE1;
 376         features->compression_type2 = raw_extended_features &
 377                                         EXT_FEATURE_COMPRESSION_TYPE2;
 378         features->compression_type3 = raw_extended_features &
 379                                         EXT_FEATURE_COMPRESSION_TYPE3;
 380         features->interlace = raw_extended_features & EXT_FEATURE_INTERLACE;
 381         features->osd = raw_extended_features & EXT_FEATURE_OSD;
 382         features->compression_pipes = raw_extended_features &
 383                                         EXT_FEATURE_COMPRESSION_PERF_MASK;
 384
 385         return 0;
 386 }
 387
 388 #else
 389
 390 /**
 391  * get_versions() - Fill structure with info from version register.
 392  * @fpga:     Identifier of the FPGA device to be queried for information
 393  * @versions: Pointer to the structure to fill with information from the
 394  *            versions register
 395  *
 396  * This is the legacy version and should be considered deprecated for new
 397  * devices.
 398  *
 399  * Return: 0
 400  */
 401 static int get_versions(unsigned int fpga, struct fpga_versions *versions)
 402 {
 403         enum {
 404                 /* HW version encoding is a mess, leave it for the moment */
 405                 VERSIONS_HW_VER_MASK = 0xf << 0,
 406                 VERSIONS_PIX_CLOCK_GEN_IDT8N3QV01 = BIT(4),
 407                 VERSIONS_SFP = BIT(5),
 408                 VERSIONS_VIDEO_MASK = 0x7 << 6,
 409                 VERSIONS_VIDEO_DVI = 0x0 << 6,
 410                 VERSIONS_VIDEO_DP_165 = 0x1 << 6,
 411                 VERSIONS_VIDEO_DP_300 = 0x2 << 6,
 412                 VERSIONS_VIDEO_HDMI = 0x3 << 6,
 413                 VERSIONS_UT_MASK = 0xf << 12,
 414                 VERSIONS_UT_MAIN_SERVER = 0x0 << 12,
 415                 VERSIONS_UT_MAIN_USER = 0x1 << 12,
 416                 VERSIONS_UT_VIDEO_SERVER = 0x2 << 12,
 417                 VERSIONS_UT_VIDEO_USER = 0x3 << 12,
 418         };
 419         u16 raw_versions;
 420
 421         memset(versions, 0, sizeof(struct fpga_versions));
 422
 423         FPGA_GET_REG(fpga, versions, &raw_versions);
 424
 425         switch (raw_versions & VERSIONS_UT_MASK) {
 426         case VERSIONS_UT_MAIN_SERVER:
 427                 versions->video_channel = false;
 428                 versions->con_side = false;
 429                 break;
 430
 431         case VERSIONS_UT_MAIN_USER:
 432                 versions->video_channel = false;
 433                 versions->con_side = true;
 434                 break;
 435
 436         case VERSIONS_UT_VIDEO_SERVER:
 437                 versions->video_channel = true;
 438                 versions->con_side = false;
 439                 break;
 440
 441         case VERSIONS_UT_VIDEO_USER:
 442                 versions->video_channel = true;
 443                 versions->con_side = true;
 444                 break;
 445         }
 446
 447         switch (raw_versions & VERSIONS_VIDEO_MASK) {
 448         case VERSIONS_VIDEO_DVI:
 449                 versions->pcb_video_type = PCB_DVI_SL;
 450                 break;
 451
 452         case VERSIONS_VIDEO_DP_165:
 453                 versions->pcb_video_type = PCB_DP_165MPIX;
 454                 break;
 455
 456         case VERSIONS_VIDEO_DP_300:
 457                 versions->pcb_video_type = PCB_DP_300MPIX;
 458                 break;
 459
 460         case VERSIONS_VIDEO_HDMI:
 461                 versions->pcb_video_type = PCB_HDMI;
 462                 break;
 463         }
 464
 465         versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
 466
 467         if (raw_versions & VERSIONS_SFP)
 468                 versions->pcb_transmission_type = PCB_FIBER_3G;
 469         else
 470                 versions->pcb_transmission_type = PCB_CAT_1G;
 471
 472         return 0;
 473 }
 474
 475 /**
 476  * get_features() - Fill structure with info from features register.
 477  * @fpga:     Identifier of the FPGA device to be queried for information
 478  * @features: Pointer to the structure to fill with information from the
 479  *            features register
 480  *
 481  * This is the legacy version and should be considered deprecated for new
 482  * devices.
 483  *
 484  * Return: 0
 485  */
 486 static int get_features(unsigned int fpga, struct fpga_features *features)
 487 {
 488         enum {
 489                 FEATURE_CARRIER_SPEED_2_5 = BIT(4),
 490                 FEATURE_RAM_MASK = 0x7 << 5,
 491                 FEATURE_RAM_DDR2_32BIT = 0x0 << 5,
 492                 FEATURE_RAM_DDR3_32BIT = 0x1 << 5,
 493                 FEATURE_RAM_DDR3_48BIT = 0x2 << 5,
 494                 FEATURE_PCM_AUDIO_TX = BIT(9),
 495                 FEATURE_PCM_AUDIO_RX = BIT(10),
 496                 FEATURE_OSD = BIT(11),
 497                 FEATURE_USB20 = BIT(12),
 498                 FEATURE_COMPRESSION_MASK = 7 << 13,
 499                 FEATURE_COMPRESSION_TYPE1 = 0x1 << 13,
 500                 FEATURE_COMPRESSION_TYPE1_TYPE2 = 0x3 << 13,
 501                 FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3 = 0x7 << 13,
 502         };
 503
 504         enum {
 505                 EXTENDED_FEATURE_SPDIF_AUDIO_TX = BIT(0),
 506                 EXTENDED_FEATURE_SPDIF_AUDIO_RX = BIT(1),
 507                 EXTENDED_FEATURE_RS232 = BIT(2),
 508                 EXTENDED_FEATURE_COMPRESSION_PIPES = BIT(3),
 509                 EXTENDED_FEATURE_INTERLACE = BIT(4),
 510         };
 511
 512         u16 raw_features;
 513         u16 raw_extended_features;
 514
 515         memset(features, 0, sizeof(struct fpga_features));
 516
 517         FPGA_GET_REG(fpga, fpga_features, &raw_features);
 518         FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features);
 519
 520         features->video_channels = raw_features & 0x3;
 521         features->carriers = (raw_features >> 2) & 0x3;
 522
 523         features->carrier_speed = (raw_features & FEATURE_CARRIER_SPEED_2_5)
 524                 ? CARRIER_SPEED_2_5G : CARRIER_SPEED_1G;
 525
 526         switch (raw_features & FEATURE_RAM_MASK) {
 527         case FEATURE_RAM_DDR2_32BIT:
 528                 features->ram_config = RAM_DDR2_32BIT_295MBPS;
 529                 break;
 530
 531         case FEATURE_RAM_DDR3_32BIT:
 532                 features->ram_config = RAM_DDR3_32BIT_590MBPS;
 533                 break;
 534
 535         case FEATURE_RAM_DDR3_48BIT:
 536                 features->ram_config = RAM_DDR3_48BIT_590MBPS;
 537                 break;
 538         }
 539
 540         features->pcm_tx = raw_features & FEATURE_PCM_AUDIO_TX;
 541         features->pcm_rx = raw_features & FEATURE_PCM_AUDIO_RX;
 542         features->spdif_tx = raw_extended_features &
 543                                 EXTENDED_FEATURE_SPDIF_AUDIO_TX;
 544         features->spdif_rx = raw_extended_features &
 545                                 EXTENDED_FEATURE_SPDIF_AUDIO_RX;
 546
 547         features->usb2 = raw_features & FEATURE_USB20;
 548         features->rs232 = raw_extended_features & EXTENDED_FEATURE_RS232;
 549
 550         features->compression_type1 = false;
 551         features->compression_type2 = false;
 552         features->compression_type3 = false;
 553         switch (raw_features & FEATURE_COMPRESSION_MASK) {
 554         case FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3:
 555                 features->compression_type3 = true;
 556                 /* fall-through */
 557         case FEATURE_COMPRESSION_TYPE1_TYPE2:
 558                 features->compression_type2 = true;
 559                 /* fall-through */
 560         case FEATURE_COMPRESSION_TYPE1:
 561                 features->compression_type1 = true;
 562                 break;
 563         }
 564
 565         features->interlace = raw_extended_features &
 566                                 EXTENDED_FEATURE_INTERLACE;
 567         features->osd = raw_features & FEATURE_OSD;
 568         features->compression_pipes = raw_extended_features &
 569                                         EXTENDED_FEATURE_COMPRESSION_PIPES;
 570
 571         return 0;
 572 }
 573
 574 #endif
 575
 576 /**
 577  * fpga_print_info() - Print information about FPGA device
 578  * @dev: FPGA device to print information about
 579  */
 580 static void fpga_print_info(struct udevice *dev)
 581 {
 582         struct ihs_fpga_priv *priv = dev_get_priv(dev);
 583         u16 fpga_version;
 584         struct fpga_versions versions;
 585         struct fpga_features features;
 586
 587         ihs_fpga_get(priv->map, fpga_version, &fpga_version);
 588         get_versions(dev, &versions);
 589         get_features(dev, &features);
 590
 591         if (versions.video_channel)
 592                 printf("Videochannel");
 593         else
 594                 printf("Mainchannel");
 595
 596         if (versions.con_side)
 597                 printf(" User");
 598         else
 599                 printf(" Server");
 600
 601         switch (versions.pcb_transmission_type) {
 602         case PCB_CAT_1G:
 603         case PCB_CAT_10G:
 604                 printf(" CAT");
 605                 break;
 606         case PCB_FIBER_3G:
 607         case PCB_FIBER_10G:
 608                 printf(" Fiber");
 609                 break;
 610         };
 611
 612         switch (versions.pcb_video_type) {
 613         case PCB_DVI_SL:
 614                 printf(" DVI,");
 615                 break;
 616         case PCB_DP_165MPIX:
 617                 printf(" DP 165MPix/s,");
 618                 break;
 619         case PCB_DP_300MPIX:
 620                 printf(" DP 300MPix/s,");
 621                 break;
 622         case PCB_HDMI:
 623                 printf(" HDMI,");
 624                 break;
 625         case PCB_DP_1_2:
 626                 printf(" DP 1.2,");
 627                 break;
 628         case PCB_HDMI_2_0:
 629                 printf(" HDMI 2.0,");
 630                 break;
 631         }
 632
 633         printf(" FPGA V %d.%02d\n       features: ",
 634                fpga_version / 100, fpga_version % 100);
 635
 636         if (!features.compression_type1 &&
 637             !features.compression_type2 &&
 638             !features.compression_type3)
 639                 printf("no compression, ");
 640
 641         if (features.compression_type1)
 642                 printf("type1, ");
 643
 644         if (features.compression_type2)
 645                 printf("type2, ");
 646
 647         if (features.compression_type3)
 648                 printf("type3, ");
 649
 650         printf("%sosd", features.osd ? "" : "no ");
 651
 652         if (features.pcm_rx && features.pcm_tx)
 653                 printf(", pcm rx+tx");
 654         else if (features.pcm_rx)
 655                 printf(", pcm rx");
 656         else if (features.pcm_tx)
 657                 printf(", pcm tx");
 658
 659         if (features.spdif_rx && features.spdif_tx)
 660                 printf(", spdif rx+tx");
 661         else if (features.spdif_rx)
 662                 printf(", spdif rx");
 663         else if (features.spdif_tx)
 664                 printf(", spdif tx");
 665
 666         puts(",\n       ");
 667
 668         switch (features.sysclock) {
 669         case SYSCLK_147456:
 670                 printf("clock 147.456 MHz");
 671                 break;
 672         }
 673
 674         switch (features.ram_config) {
 675         case RAM_DDR2_32BIT_295MBPS:
 676                 printf(", RAM 32 bit DDR2");
 677                 break;
 678         case RAM_DDR3_32BIT_590MBPS:
 679                 printf(", RAM 32 bit DDR3");
 680                 break;
 681         case RAM_DDR3_48BIT_590MBPS:
 682         case RAM_DDR3_48BIT_1800MBPS:
 683                 printf(", RAM 48 bit DDR3");
 684                 break;
 685         case RAM_DDR3_64BIT_1800MBPS:
 686                 printf(", RAM 64 bit DDR3");
 687                 break;
 688         }
 689
 690         printf(", %d carrier(s)", features.carriers);
 691
 692         switch (features.carrier_speed) {
 693         case CARRIER_SPEED_1G:
 694                 printf(", 1Gbit/s");
 695                 break;
 696         case CARRIER_SPEED_3G:
 697                 printf(", 3Gbit/s");
 698                 break;
 699         case CARRIER_SPEED_10G:
 700                 printf(", 10Gbit/s");
 701                 break;
 702         }
 703
 704         printf(", %d video channel(s)\n", features.video_channels);
 705 }
 706
 707 /**
 708  * do_reflection_test() - Run reflection test on a FPGA device
 709  * @dev: FPGA device to run reflection test on
 710  *
 711  * Return: 0 if reflection test succeeded, -ve on error
 712  */
 713 static int do_reflection_test(struct udevice *dev)
 714 {
 715         struct ihs_fpga_priv *priv = dev_get_priv(dev);
 716         int ctr = 0;
 717
 718         while (1) {
 719                 u16 val;
 720
 721                 ihs_fpga_set(priv->map, reflection_low, REFLECTION_TESTPATTERN);
 722
 723                 ihs_fpga_get(priv->map, reflection_low, &val);
 724                 if (val == (~REFLECTION_TESTPATTERN & 0xffff))
 725                         return -EIO;
 726
 727                 mdelay(REFLECTION_TEST_DELAY);
 728                 if (ctr++ > REFLECTION_TEST_ROUNDS)
 729                         return 0;
 730         }
 731 }
 732
 733 /**
 734  * wait_for_fpga_done() - Wait until 'done'-flag is set for FPGA device
 735  * @dev: FPGA device whose done flag to wait for
 736  *
 737  * This function waits until it detects that the done-GPIO's value was changed
 738  * to 1 by the FPGA, which indicates that the device is configured and ready to
 739  * use.
 740  *
 741  * Return: 0 if done flag was detected, -ve on error
 742  */
 743 static int wait_for_fpga_done(struct udevice *dev)
 744 {
 745         struct ihs_fpga_priv *priv = dev_get_priv(dev);
 746         int ctr = 0;
 747         int done_val;
 748
 749         while (1) {
 750                 done_val = dm_gpio_get_value(&priv->done_gpio);
 751                 if (done_val < 0) {
 752                         debug("%s: Error while reading done-GPIO (err = %d)\n",
 753                               dev->name, done_val);
 754                         return done_val;
 755                 }
 756
 757                 if (done_val)
 758                         return 0;
 759
 760                 mdelay(FPGA_DONE_WAIT_DELAY);
 761                 if (ctr++ > FPGA_DONE_WAIT_ROUND) {
 762                         debug("%s: FPGA init failed (done not detected)\n",
 763                               dev->name);
 764                         return -EIO;
 765                 }
 766         }
 767 }
 768
 769 static int ihs_fpga_probe(struct udevice *dev)
 770 {
 771         struct ihs_fpga_priv *priv = dev_get_priv(dev);
 772         int ret;
 773
 774         /* TODO(mario.six@gdsys.cc): Case of FPGA attached to MCLink bus */
 775
 776         ret = regmap_init_mem(dev_ofnode(dev), &priv->map);
 777         if (ret) {
 778                 debug("%s: Could not initialize regmap (err = %d)",
 779                       dev->name, ret);
 780                 return ret;
 781         }
 782
 783         ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio,
 784                                    GPIOD_IS_OUT);
 785         if (ret) {
 786                 debug("%s: Could not get reset-GPIO (err = %d)\n",
 787                       dev->name, ret);
 788                 return ret;
 789         }
 790
 791         if (!priv->reset_gpio.dev) {
 792                 debug("%s: Could not get reset-GPIO\n", dev->name);
 793                 return -ENOENT;
 794         }
 795
 796         ret = gpio_request_by_name(dev, "done-gpios", 0, &priv->done_gpio,
 797                                    GPIOD_IS_IN);
 798         if (ret) {
 799                 debug("%s: Could not get done-GPIO (err = %d)\n",
 800                       dev->name, ret);
 801                 return ret;
 802         }
 803
 804         if (!priv->done_gpio.dev) {
 805                 debug("%s: Could not get done-GPIO\n", dev->name);
 806                 return -ENOENT;
 807         }
 808
 809         ret = dm_gpio_set_value(&priv->reset_gpio, 1);
 810         if (ret) {
 811                 debug("%s: Error while setting reset-GPIO (err = %d)\n",
 812                       dev->name, ret);
 813                 return ret;
 814         }
 815
 816         /* If FPGA already runs, don't initialize again */
 817         if (do_reflection_test(dev))
 818                 goto reflection_ok;
 819
 820         ret = dm_gpio_set_value(&priv->reset_gpio, 0);
 821         if (ret) {
 822                 debug("%s: Error while setting reset-GPIO (err = %d)\n",
 823                       dev->name, ret);
 824                 return ret;
 825         }
 826
 827         ret = wait_for_fpga_done(dev);
 828         if (ret) {
 829                 debug("%s: Error while waiting for FPGA done (err = %d)\n",
 830                       dev->name, ret);
 831                 return ret;
 832         }
 833
 834         udelay(10);
 835
 836         ret = dm_gpio_set_value(&priv->reset_gpio, 1);
 837         if (ret) {
 838                 debug("%s: Error while setting reset-GPIO (err = %d)\n",
 839                       dev->name, ret);
 840                 return ret;
 841         }
 842
 843         if (!do_reflection_test(dev)) {
 844                 debug("%s: Reflection test FAILED\n", dev->name);
 845                 return -EIO;
 846         }
 847
 848 reflection_ok:
 849         printf("%s: Reflection test passed.\n", dev->name);
 850
 851         fpga_print_info(dev);
 852
 853         return 0;
 854 }
 855
 856 static const struct udevice_id ihs_fpga_ids[] = {
 857         { .compatible = "gdsys,iocon_fpga" },
 858         { .compatible = "gdsys,iocpu_fpga" },
 859         { }
 860 };
 861
 862 U_BOOT_DRIVER(ihs_fpga_bus) = {
 863         .name           = "ihs_fpga_bus",
 864         .id             = UCLASS_MISC,
 865         .of_match       = ihs_fpga_ids,
 866         .probe          = ihs_fpga_probe,
 867         .priv_auto_alloc_size = sizeof(struct ihs_fpga_priv),
 868 };