drivers/misc/ihs_fpga.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2017
   4  * Mario Six,  Guntermann & Drunck GmbH, mario.six@gdsys.cc
   5  *
   6  * based on the ioep-fpga driver, which is
   7  *
   8  * (C) Copyright 2014
   9  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
  10  */
  11
  12 #include <dm.h>
  13 #include <log.h>
  14 #include <regmap.h>
  15 #include <asm/gpio.h>
  16 #include <linux/bitops.h>
  17 #include <linux/delay.h>
  18
  19 #include "ihs_fpga.h"
  20
  21 /**
  22  * struct ihs_fpga_priv - Private data structure for IHS FPGA driver
  23  * @map:        Register map for the FPGA's own register space
  24  * @reset_gpio: GPIO to start FPGA reconfiguration
  25  * @done_gpio:  GPOI to read the 'ready' status of the FPGA
  26  */
  27 struct ihs_fpga_priv {
  28         struct regmap *map;
  29         struct gpio_desc reset_gpio;
  30         struct gpio_desc done_gpio;
  31 };
  32
  33 /* Test pattern for reflection test */
  34 const u16 REFLECTION_TESTPATTERN = 0xdead;
  35 /* Delay (in ms) for each round in the reflection test */
  36 const uint REFLECTION_TEST_DELAY = 100;
  37 /* Maximum number of rounds in the reflection test */
  38 const uint REFLECTION_TEST_ROUNDS = 5;
  39 /* Delay (in ms) for each round waiting for the FPGA's done GPIO */
  40 const uint FPGA_DONE_WAIT_DELAY = 100;
  41 /* Maximum number of rounds for waiting for the FPGA's done GPIO */
  42 const uint FPGA_DONE_WAIT_ROUND = 5;
  43
  44 /**
  45  * enum pcb_video_type - Video type of the PCB
  46  * @PCB_DVI_SL:     Video type is DVI single-link
  47  * @PCB_DP_165MPIX: Video type is DisplayPort (165Mpix)
  48  * @PCB_DP_300MPIX: Video type is DisplayPort (300Mpix)
  49  * @PCB_HDMI:       Video type is HDMI
  50  * @PCB_DP_1_2:     Video type is DisplayPort 1.2
  51  * @PCB_HDMI_2_0:   Video type is HDMI 2.0
  52  */
  53 enum pcb_video_type {
  54         PCB_DVI_SL,
  55         PCB_DP_165MPIX,
  56         PCB_DP_300MPIX,
  57         PCB_HDMI,
  58         PCB_DP_1_2,
  59         PCB_HDMI_2_0,
  60 };
  61
  62 /**
  63  * enum pcb_transmission_type - Transmission type of the PCB
  64  * @PCB_CAT_1G:    Transmission type is 1G Ethernet
  65  * @PCB_FIBER_3G:  Transmission type is 3G Fiber
  66  * @PCB_CAT_10G:   Transmission type is 10G Ethernet
  67  * @PCB_FIBER_10G: Transmission type is 10G Fiber
  68  */
  69 enum pcb_transmission_type {
  70         PCB_CAT_1G,
  71         PCB_FIBER_3G,
  72         PCB_CAT_10G,
  73         PCB_FIBER_10G,
  74 };
  75
  76 /**
  77  * enum carrier_speed - Speed of the FPGA's carrier
  78  * @CARRIER_SPEED_1G:   The carrier speed is 1G
  79  * @CARRIER_SPEED_2_5G: The carrier speed is 2.5G
  80  * @CARRIER_SPEED_3G:   The carrier speed is 3G
  81  * @CARRIER_SPEED_10G:  The carrier speed is 10G
  82  */
  83 enum carrier_speed {
  84         CARRIER_SPEED_1G,
  85         CARRIER_SPEED_3G,
  86         CARRIER_SPEED_2_5G = CARRIER_SPEED_3G,
  87         CARRIER_SPEED_10G,
  88 };
  89
  90 /**
  91  * enum ram_config - FPGA's RAM configuration
  92  * @RAM_DDR2_32BIT_295MBPS:  DDR2 32 bit at 295Mb/s
  93  * @RAM_DDR3_32BIT_590MBPS:  DDR3 32 bit at 590Mb/s
  94  * @RAM_DDR3_48BIT_590MBPS:  DDR3 48 bit at 590Mb/s
  95  * @RAM_DDR3_64BIT_1800MBPS: DDR3 64 bit at 1800Mb/s
  96  * @RAM_DDR3_48BIT_1800MBPS: DDR3 48 bit at 1800Mb/s
  97  */
  98 enum ram_config {
  99         RAM_DDR2_32BIT_295MBPS,
 100         RAM_DDR3_32BIT_590MBPS,
 101         RAM_DDR3_48BIT_590MBPS,
 102         RAM_DDR3_64BIT_1800MBPS,
 103         RAM_DDR3_48BIT_1800MBPS,
 104 };
 105
 106 /**
 107  * enum sysclock - Speed of the FPGA's system clock
 108  * @SYSCLK_147456: System clock is 147.456 MHz
 109  */
 110 enum sysclock {
 111         SYSCLK_147456,
 112 };
 113
 114 /**
 115  * struct fpga_versions - Data read from the versions register
 116  * @video_channel:         Is the FPGA for a video channel (true) or main
 117  *                         channel (false) device?
 118  * @con_side:              Is the FPGA for a CON (true) or a CPU (false) device?
 119  * @pcb_video_type:        Defines for whch video type the FPGA is configured
 120  * @pcb_transmission_type: Defines for which transmission type the FPGA is
 121  *                         configured
 122  * @hw_version:            Hardware version of the FPGA
 123  */
 124 struct fpga_versions {
 125         bool video_channel;
 126         bool con_side;
 127         enum pcb_video_type pcb_video_type;
 128         enum pcb_transmission_type pcb_transmission_type;
 129         unsigned int hw_version;
 130 };
 131
 132 /**
 133  * struct fpga_features - Data read from the features register
 134  * @video_channels:     Number of video channels supported
 135  * @carriers:           Number of carrier channels supported
 136  * @carrier_speed:      Speed of carriers
 137  * @ram_config:         RAM configuration of FPGA
 138  * @sysclock:           System clock speed of FPGA
 139  * @pcm_tx:             Support for PCM transmission
 140  * @pcm_rx:             Support for PCM reception
 141  * @spdif_tx:           Support for SPDIF audio transmission
 142  * @spdif_rx:           Support for SPDIF audio reception
 143  * @usb2:               Support for transparent USB2.0
 144  * @rs232:              Support for bidirectional RS232
 145  * @compression_type1:  Support for compression type 1
 146  * @compression_type2:  Support for compression type 2
 147  * @compression_type3:  Support for compression type 3
 148  * @interlace:          Support for interlace image formats
 149  * @osd:                Support for a OSD
 150  * @compression_pipes:  Number of compression pipes supported
 151  */
 152 struct fpga_features {
 153         u8 video_channels;
 154         u8 carriers;
 155         enum carrier_speed carrier_speed;
 156         enum ram_config ram_config;
 157         enum sysclock sysclock;
 158         bool pcm_tx;
 159         bool pcm_rx;
 160         bool spdif_tx;
 161         bool spdif_rx;
 162         bool usb2;
 163         bool rs232;
 164         bool compression_type1;
 165         bool compression_type2;
 166         bool compression_type3;
 167         bool interlace;
 168         bool osd;
 169         bool compression_pipes;
 170 };
 171
 172 #ifdef CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM
 173
 174 /**
 175  * get_versions() - Fill structure with info from version register.
 176  * @dev:      FPGA device to be queried for information
 177  * @versions: Pointer to the structure to fill with information from the
 178  *            versions register
 179  * Return: 0
 180  */
 181 static int get_versions(struct udevice *dev, struct fpga_versions *versions)
 182 {
 183         struct ihs_fpga_priv *priv = dev_get_priv(dev);
 184         enum {
 185                 VERSIONS_FPGA_VIDEO_CHANNEL = BIT(12),
 186                 VERSIONS_FPGA_CON_SIDE = BIT(13),
 187                 VERSIONS_FPGA_SC = BIT(14),
 188                 VERSIONS_PCB_CON = BIT(9),
 189                 VERSIONS_PCB_SC = BIT(8),
 190                 VERSIONS_PCB_VIDEO_MASK = 0x3 << 6,
 191                 VERSIONS_PCB_VIDEO_DP_1_2 = 0x0 << 6,
 192                 VERSIONS_PCB_VIDEO_HDMI_2_0 = 0x1 << 6,
 193                 VERSIONS_PCB_TRANSMISSION_MASK = 0x3 << 4,
 194                 VERSIONS_PCB_TRANSMISSION_FIBER_10G = 0x0 << 4,
 195                 VERSIONS_PCB_TRANSMISSION_CAT_10G = 0x1 << 4,
 196                 VERSIONS_PCB_TRANSMISSION_FIBER_3G = 0x2 << 4,
 197                 VERSIONS_PCB_TRANSMISSION_CAT_1G = 0x3 << 4,
 198                 VERSIONS_HW_VER_MASK = 0xf << 0,
 199         };
 200         u16 raw_versions;
 201
 202         memset(versions, 0, sizeof(struct fpga_versions));
 203
 204         ihs_fpga_get(priv->map, versions, &raw_versions);
 205
 206         versions->video_channel = raw_versions & VERSIONS_FPGA_VIDEO_CHANNEL;
 207         versions->con_side = raw_versions & VERSIONS_FPGA_CON_SIDE;
 208
 209         switch (raw_versions & VERSIONS_PCB_VIDEO_MASK) {
 210         case VERSIONS_PCB_VIDEO_DP_1_2:
 211                 versions->pcb_video_type = PCB_DP_1_2;
 212                 break;
 213
 214         case VERSIONS_PCB_VIDEO_HDMI_2_0:
 215                 versions->pcb_video_type = PCB_HDMI_2_0;
 216                 break;
 217         }
 218
 219         switch (raw_versions & VERSIONS_PCB_TRANSMISSION_MASK) {
 220         case VERSIONS_PCB_TRANSMISSION_FIBER_10G:
 221                 versions->pcb_transmission_type = PCB_FIBER_10G;
 222                 break;
 223
 224         case VERSIONS_PCB_TRANSMISSION_CAT_10G:
 225                 versions->pcb_transmission_type = PCB_CAT_10G;
 226                 break;
 227
 228         case VERSIONS_PCB_TRANSMISSION_FIBER_3G:
 229                 versions->pcb_transmission_type = PCB_FIBER_3G;
 230                 break;
 231
 232         case VERSIONS_PCB_TRANSMISSION_CAT_1G:
 233                 versions->pcb_transmission_type = PCB_CAT_1G;
 234                 break;
 235         }
 236
 237         versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
 238
 239         return 0;
 240 }
 241
 242 /**
 243  * get_features() - Fill structure with info from features register.
 244  * @dev:      FPGA device to be queried for information
 245  * @features: Pointer to the structure to fill with information from the
 246  *            features register
 247  * Return: 0
 248  */
 249 static int get_features(struct udevice *dev, struct fpga_features *features)
 250 {
 251         struct ihs_fpga_priv *priv = dev_get_priv(dev);
 252         enum {
 253                 FEATURE_SPDIF_RX = BIT(15),
 254                 FEATURE_SPDIF_TX = BIT(14),
 255                 FEATURE_PCM_RX = BIT(13),
 256                 FEATURE_PCM_TX = BIT(12),
 257                 FEATURE_RAM_MASK = GENMASK(11, 8),
 258                 FEATURE_RAM_DDR2_32BIT_295MBPS = 0x0 << 8,
 259                 FEATURE_RAM_DDR3_32BIT_590MBPS = 0x1 << 8,
 260                 FEATURE_RAM_DDR3_48BIT_590MBPS = 0x2 << 8,
 261                 FEATURE_RAM_DDR3_64BIT_1800MBPS = 0x3 << 8,
 262                 FEATURE_RAM_DDR3_48BIT_1800MBPS = 0x4 << 8,
 263                 FEATURE_CARRIER_SPEED_MASK = GENMASK(7, 6),
 264                 FEATURE_CARRIER_SPEED_1G = 0x0 << 6,
 265                 FEATURE_CARRIER_SPEED_2_5G = 0x1 << 6,
 266                 FEATURE_CARRIER_SPEED_10G = 0x2 << 6,
 267                 FEATURE_CARRIERS_MASK = GENMASK(5, 4),
 268                 FEATURE_CARRIERS_0 = 0x0 << 4,
 269                 FEATURE_CARRIERS_1 = 0x1 << 4,
 270                 FEATURE_CARRIERS_2 = 0x2 << 4,
 271                 FEATURE_CARRIERS_4 = 0x3 << 4,
 272                 FEATURE_USB2 = BIT(3),
 273                 FEATURE_VIDEOCHANNELS_MASK = GENMASK(2, 0),
 274                 FEATURE_VIDEOCHANNELS_0 = 0x0 << 0,
 275                 FEATURE_VIDEOCHANNELS_1 = 0x1 << 0,
 276                 FEATURE_VIDEOCHANNELS_1_1 = 0x2 << 0,
 277                 FEATURE_VIDEOCHANNELS_2 = 0x3 << 0,
 278         };
 279
 280         enum {
 281                 EXT_FEATURE_OSD = BIT(15),
 282                 EXT_FEATURE_ETHERNET = BIT(9),
 283                 EXT_FEATURE_INTERLACE = BIT(8),
 284                 EXT_FEATURE_RS232 = BIT(7),
 285                 EXT_FEATURE_COMPRESSION_PERF_MASK = GENMASK(6, 4),
 286                 EXT_FEATURE_COMPRESSION_PERF_1X = 0x0 << 4,
 287                 EXT_FEATURE_COMPRESSION_PERF_2X = 0x1 << 4,
 288                 EXT_FEATURE_COMPRESSION_PERF_4X = 0x2 << 4,
 289                 EXT_FEATURE_COMPRESSION_TYPE1 = BIT(0),
 290                 EXT_FEATURE_COMPRESSION_TYPE2 = BIT(1),
 291                 EXT_FEATURE_COMPRESSION_TYPE3 = BIT(2),
 292         };
 293
 294         u16 raw_features;
 295         u16 raw_extended_features;
 296
 297         memset(features, 0, sizeof(struct fpga_features));
 298
 299         ihs_fpga_get(priv->map, features, &raw_features);
 300         ihs_fpga_get(priv->map, extended_features, &raw_extended_features);
 301
 302         switch (raw_features & FEATURE_VIDEOCHANNELS_MASK) {
 303         case FEATURE_VIDEOCHANNELS_0:
 304                 features->video_channels = 0;
 305                 break;
 306
 307         case FEATURE_VIDEOCHANNELS_1:
 308                 features->video_channels = 1;
 309                 break;
 310
 311         case FEATURE_VIDEOCHANNELS_1_1:
 312         case FEATURE_VIDEOCHANNELS_2:
 313                 features->video_channels = 2;
 314                 break;
 315         };
 316
 317         switch (raw_features & FEATURE_CARRIERS_MASK) {
 318         case FEATURE_CARRIERS_0:
 319                 features->carriers = 0;
 320                 break;
 321
 322         case FEATURE_CARRIERS_1:
 323                 features->carriers = 1;
 324                 break;
 325
 326         case FEATURE_CARRIERS_2:
 327                 features->carriers = 2;
 328                 break;
 329
 330         case FEATURE_CARRIERS_4:
 331                 features->carriers = 4;
 332                 break;
 333         }
 334
 335         switch (raw_features & FEATURE_CARRIER_SPEED_MASK) {
 336         case FEATURE_CARRIER_SPEED_1G:
 337                 features->carrier_speed = CARRIER_SPEED_1G;
 338                 break;
 339         case FEATURE_CARRIER_SPEED_2_5G:
 340                 features->carrier_speed = CARRIER_SPEED_2_5G;
 341                 break;
 342         case FEATURE_CARRIER_SPEED_10G:
 343                 features->carrier_speed = CARRIER_SPEED_10G;
 344                 break;
 345         }
 346
 347         switch (raw_features & FEATURE_RAM_MASK) {
 348         case FEATURE_RAM_DDR2_32BIT_295MBPS:
 349                 features->ram_config = RAM_DDR2_32BIT_295MBPS;
 350                 break;
 351
 352         case FEATURE_RAM_DDR3_32BIT_590MBPS:
 353                 features->ram_config = RAM_DDR3_32BIT_590MBPS;
 354                 break;
 355
 356         case FEATURE_RAM_DDR3_48BIT_590MBPS:
 357                 features->ram_config = RAM_DDR3_48BIT_590MBPS;
 358                 break;
 359
 360         case FEATURE_RAM_DDR3_64BIT_1800MBPS:
 361                 features->ram_config = RAM_DDR3_64BIT_1800MBPS;
 362                 break;
 363
 364         case FEATURE_RAM_DDR3_48BIT_1800MBPS:
 365                 features->ram_config = RAM_DDR3_48BIT_1800MBPS;
 366                 break;
 367         }
 368
 369         features->pcm_tx = raw_features & FEATURE_PCM_TX;
 370         features->pcm_rx = raw_features & FEATURE_PCM_RX;
 371         features->spdif_tx = raw_features & FEATURE_SPDIF_TX;
 372         features->spdif_rx = raw_features & FEATURE_SPDIF_RX;
 373         features->usb2 = raw_features & FEATURE_USB2;
 374         features->rs232 = raw_extended_features & EXT_FEATURE_RS232;
 375         features->compression_type1 = raw_extended_features &
 376                                         EXT_FEATURE_COMPRESSION_TYPE1;
 377         features->compression_type2 = raw_extended_features &
 378                                         EXT_FEATURE_COMPRESSION_TYPE2;
 379         features->compression_type3 = raw_extended_features &
 380                                         EXT_FEATURE_COMPRESSION_TYPE3;
 381         features->interlace = raw_extended_features & EXT_FEATURE_INTERLACE;
 382         features->osd = raw_extended_features & EXT_FEATURE_OSD;
 383         features->compression_pipes = raw_extended_features &
 384                                         EXT_FEATURE_COMPRESSION_PERF_MASK;
 385
 386         return 0;
 387 }
 388
 389 #else
 390
 391 /**
 392  * get_versions() - Fill structure with info from version register.
 393  * @fpga:     Identifier of the FPGA device to be queried for information
 394  * @versions: Pointer to the structure to fill with information from the
 395  *            versions register
 396  *
 397  * This is the legacy version and should be considered deprecated for new
 398  * devices.
 399  *
 400  * Return: 0
 401  */
 402 static int get_versions(unsigned int fpga, struct fpga_versions *versions)
 403 {
 404         enum {
 405                 /* HW version encoding is a mess, leave it for the moment */
 406                 VERSIONS_HW_VER_MASK = 0xf << 0,
 407                 VERSIONS_PIX_CLOCK_GEN_IDT8N3QV01 = BIT(4),
 408                 VERSIONS_SFP = BIT(5),
 409                 VERSIONS_VIDEO_MASK = 0x7 << 6,
 410                 VERSIONS_VIDEO_DVI = 0x0 << 6,
 411                 VERSIONS_VIDEO_DP_165 = 0x1 << 6,
 412                 VERSIONS_VIDEO_DP_300 = 0x2 << 6,
 413                 VERSIONS_VIDEO_HDMI = 0x3 << 6,
 414                 VERSIONS_UT_MASK = 0xf << 12,
 415                 VERSIONS_UT_MAIN_SERVER = 0x0 << 12,
 416                 VERSIONS_UT_MAIN_USER = 0x1 << 12,
 417                 VERSIONS_UT_VIDEO_SERVER = 0x2 << 12,
 418                 VERSIONS_UT_VIDEO_USER = 0x3 << 12,
 419         };
 420         u16 raw_versions;
 421
 422         memset(versions, 0, sizeof(struct fpga_versions));
 423
 424         FPGA_GET_REG(fpga, versions, &raw_versions);
 425
 426         switch (raw_versions & VERSIONS_UT_MASK) {
 427         case VERSIONS_UT_MAIN_SERVER:
 428                 versions->video_channel = false;
 429                 versions->con_side = false;
 430                 break;
 431
 432         case VERSIONS_UT_MAIN_USER:
 433                 versions->video_channel = false;
 434                 versions->con_side = true;
 435                 break;
 436
 437         case VERSIONS_UT_VIDEO_SERVER:
 438                 versions->video_channel = true;
 439                 versions->con_side = false;
 440                 break;
 441
 442         case VERSIONS_UT_VIDEO_USER:
 443                 versions->video_channel = true;
 444                 versions->con_side = true;
 445                 break;
 446         }
 447
 448         switch (raw_versions & VERSIONS_VIDEO_MASK) {
 449         case VERSIONS_VIDEO_DVI:
 450                 versions->pcb_video_type = PCB_DVI_SL;
 451                 break;
 452
 453         case VERSIONS_VIDEO_DP_165:
 454                 versions->pcb_video_type = PCB_DP_165MPIX;
 455                 break;
 456
 457         case VERSIONS_VIDEO_DP_300:
 458                 versions->pcb_video_type = PCB_DP_300MPIX;
 459                 break;
 460
 461         case VERSIONS_VIDEO_HDMI:
 462                 versions->pcb_video_type = PCB_HDMI;
 463                 break;
 464         }
 465
 466         versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
 467
 468         if (raw_versions & VERSIONS_SFP)
 469                 versions->pcb_transmission_type = PCB_FIBER_3G;
 470         else
 471                 versions->pcb_transmission_type = PCB_CAT_1G;
 472
 473         return 0;
 474 }
 475
 476 /**
 477  * get_features() - Fill structure with info from features register.
 478  * @fpga:     Identifier of the FPGA device to be queried for information
 479  * @features: Pointer to the structure to fill with information from the
 480  *            features register
 481  *
 482  * This is the legacy version and should be considered deprecated for new
 483  * devices.
 484  *
 485  * Return: 0
 486  */
 487 static int get_features(unsigned int fpga, struct fpga_features *features)
 488 {
 489         enum {
 490                 FEATURE_CARRIER_SPEED_2_5 = BIT(4),
 491                 FEATURE_RAM_MASK = 0x7 << 5,
 492                 FEATURE_RAM_DDR2_32BIT = 0x0 << 5,
 493                 FEATURE_RAM_DDR3_32BIT = 0x1 << 5,
 494                 FEATURE_RAM_DDR3_48BIT = 0x2 << 5,
 495                 FEATURE_PCM_AUDIO_TX = BIT(9),
 496                 FEATURE_PCM_AUDIO_RX = BIT(10),
 497                 FEATURE_OSD = BIT(11),
 498                 FEATURE_USB20 = BIT(12),
 499                 FEATURE_COMPRESSION_MASK = 7 << 13,
 500                 FEATURE_COMPRESSION_TYPE1 = 0x1 << 13,
 501                 FEATURE_COMPRESSION_TYPE1_TYPE2 = 0x3 << 13,
 502                 FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3 = 0x7 << 13,
 503         };
 504
 505         enum {
 506                 EXTENDED_FEATURE_SPDIF_AUDIO_TX = BIT(0),
 507                 EXTENDED_FEATURE_SPDIF_AUDIO_RX = BIT(1),
 508                 EXTENDED_FEATURE_RS232 = BIT(2),
 509                 EXTENDED_FEATURE_COMPRESSION_PIPES = BIT(3),
 510                 EXTENDED_FEATURE_INTERLACE = BIT(4),
 511         };
 512
 513         u16 raw_features;
 514         u16 raw_extended_features;
 515
 516         memset(features, 0, sizeof(struct fpga_features));
 517
 518         FPGA_GET_REG(fpga, fpga_features, &raw_features);
 519         FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features);
 520
 521         features->video_channels = raw_features & 0x3;
 522         features->carriers = (raw_features >> 2) & 0x3;
 523
 524         features->carrier_speed = (raw_features & FEATURE_CARRIER_SPEED_2_5)
 525                 ? CARRIER_SPEED_2_5G : CARRIER_SPEED_1G;
 526
 527         switch (raw_features & FEATURE_RAM_MASK) {
 528         case FEATURE_RAM_DDR2_32BIT:
 529                 features->ram_config = RAM_DDR2_32BIT_295MBPS;
 530                 break;
 531
 532         case FEATURE_RAM_DDR3_32BIT:
 533                 features->ram_config = RAM_DDR3_32BIT_590MBPS;
 534                 break;
 535
 536         case FEATURE_RAM_DDR3_48BIT:
 537                 features->ram_config = RAM_DDR3_48BIT_590MBPS;
 538                 break;
 539         }
 540
 541         features->pcm_tx = raw_features & FEATURE_PCM_AUDIO_TX;
 542         features->pcm_rx = raw_features & FEATURE_PCM_AUDIO_RX;
 543         features->spdif_tx = raw_extended_features &
 544                                 EXTENDED_FEATURE_SPDIF_AUDIO_TX;
 545         features->spdif_rx = raw_extended_features &
 546                                 EXTENDED_FEATURE_SPDIF_AUDIO_RX;
 547
 548         features->usb2 = raw_features & FEATURE_USB20;
 549         features->rs232 = raw_extended_features & EXTENDED_FEATURE_RS232;
 550
 551         features->compression_type1 = false;
 552         features->compression_type2 = false;
 553         features->compression_type3 = false;
 554         switch (raw_features & FEATURE_COMPRESSION_MASK) {
 555         case FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3:
 556                 features->compression_type3 = true;
 557                 /* fall-through */
 558         case FEATURE_COMPRESSION_TYPE1_TYPE2:
 559                 features->compression_type2 = true;
 560                 /* fall-through */
 561         case FEATURE_COMPRESSION_TYPE1:
 562                 features->compression_type1 = true;
 563                 break;
 564         }
 565
 566         features->interlace = raw_extended_features &
 567                                 EXTENDED_FEATURE_INTERLACE;
 568         features->osd = raw_features & FEATURE_OSD;
 569         features->compression_pipes = raw_extended_features &
 570                                         EXTENDED_FEATURE_COMPRESSION_PIPES;
 571
 572         return 0;
 573 }
 574
 575 #endif
 576
 577 /**
 578  * fpga_print_info() - Print information about FPGA device
 579  * @dev: FPGA device to print information about
 580  */
 581 static void fpga_print_info(struct udevice *dev)
 582 {
 583         struct ihs_fpga_priv *priv = dev_get_priv(dev);
 584         u16 fpga_version;
 585         struct fpga_versions versions;
 586         struct fpga_features features;
 587
 588         ihs_fpga_get(priv->map, fpga_version, &fpga_version);
 589         get_versions(dev, &versions);
 590         get_features(dev, &features);
 591
 592         if (versions.video_channel)
 593                 printf("Videochannel");
 594         else
 595                 printf("Mainchannel");
 596
 597         if (versions.con_side)
 598                 printf(" User");
 599         else
 600                 printf(" Server");
 601
 602         switch (versions.pcb_transmission_type) {
 603         case PCB_CAT_1G:
 604         case PCB_CAT_10G:
 605                 printf(" CAT");
 606                 break;
 607         case PCB_FIBER_3G:
 608         case PCB_FIBER_10G:
 609                 printf(" Fiber");
 610                 break;
 611         };
 612
 613         switch (versions.pcb_video_type) {
 614         case PCB_DVI_SL:
 615                 printf(" DVI,");
 616                 break;
 617         case PCB_DP_165MPIX:
 618                 printf(" DP 165MPix/s,");
 619                 break;
 620         case PCB_DP_300MPIX:
 621                 printf(" DP 300MPix/s,");
 622                 break;
 623         case PCB_HDMI:
 624                 printf(" HDMI,");
 625                 break;
 626         case PCB_DP_1_2:
 627                 printf(" DP 1.2,");
 628                 break;
 629         case PCB_HDMI_2_0:
 630                 printf(" HDMI 2.0,");
 631                 break;
 632         }
 633
 634         printf(" FPGA V %d.%02d\n       features: ",
 635                fpga_version / 100, fpga_version % 100);
 636
 637         if (!features.compression_type1 &&
 638             !features.compression_type2 &&
 639             !features.compression_type3)
 640                 printf("no compression, ");
 641
 642         if (features.compression_type1)
 643                 printf("type1, ");
 644
 645         if (features.compression_type2)
 646                 printf("type2, ");
 647
 648         if (features.compression_type3)
 649                 printf("type3, ");
 650
 651         printf("%sosd", features.osd ? "" : "no ");
 652
 653         if (features.pcm_rx && features.pcm_tx)
 654                 printf(", pcm rx+tx");
 655         else if (features.pcm_rx)
 656                 printf(", pcm rx");
 657         else if (features.pcm_tx)
 658                 printf(", pcm tx");
 659
 660         if (features.spdif_rx && features.spdif_tx)
 661                 printf(", spdif rx+tx");
 662         else if (features.spdif_rx)
 663                 printf(", spdif rx");
 664         else if (features.spdif_tx)
 665                 printf(", spdif tx");
 666
 667         puts(",\n       ");
 668
 669         switch (features.sysclock) {
 670         case SYSCLK_147456:
 671                 printf("clock 147.456 MHz");
 672                 break;
 673         }
 674
 675         switch (features.ram_config) {
 676         case RAM_DDR2_32BIT_295MBPS:
 677                 printf(", RAM 32 bit DDR2");
 678                 break;
 679         case RAM_DDR3_32BIT_590MBPS:
 680                 printf(", RAM 32 bit DDR3");
 681                 break;
 682         case RAM_DDR3_48BIT_590MBPS:
 683         case RAM_DDR3_48BIT_1800MBPS:
 684                 printf(", RAM 48 bit DDR3");
 685                 break;
 686         case RAM_DDR3_64BIT_1800MBPS:
 687                 printf(", RAM 64 bit DDR3");
 688                 break;
 689         }
 690
 691         printf(", %d carrier(s)", features.carriers);
 692
 693         switch (features.carrier_speed) {
 694         case CARRIER_SPEED_1G:
 695                 printf(", 1Gbit/s");
 696                 break;
 697         case CARRIER_SPEED_3G:
 698                 printf(", 3Gbit/s");
 699                 break;
 700         case CARRIER_SPEED_10G:
 701                 printf(", 10Gbit/s");
 702                 break;
 703         }
 704
 705         printf(", %d video channel(s)\n", features.video_channels);
 706 }
 707
 708 /**
 709  * do_reflection_test() - Run reflection test on a FPGA device
 710  * @dev: FPGA device to run reflection test on
 711  *
 712  * Return: 0 if reflection test succeeded, -ve on error
 713  */
 714 static int do_reflection_test(struct udevice *dev)
 715 {
 716         struct ihs_fpga_priv *priv = dev_get_priv(dev);
 717         int ctr = 0;
 718
 719         while (1) {
 720                 u16 val;
 721
 722                 ihs_fpga_set(priv->map, reflection_low, REFLECTION_TESTPATTERN);
 723
 724                 ihs_fpga_get(priv->map, reflection_low, &val);
 725                 if (val == (~REFLECTION_TESTPATTERN & 0xffff))
 726                         return -EIO;
 727
 728                 mdelay(REFLECTION_TEST_DELAY);
 729                 if (ctr++ > REFLECTION_TEST_ROUNDS)
 730                         return 0;
 731         }
 732 }
 733
 734 /**
 735  * wait_for_fpga_done() - Wait until 'done'-flag is set for FPGA device
 736  * @dev: FPGA device whose done flag to wait for
 737  *
 738  * This function waits until it detects that the done-GPIO's value was changed
 739  * to 1 by the FPGA, which indicates that the device is configured and ready to
 740  * use.
 741  *
 742  * Return: 0 if done flag was detected, -ve on error
 743  */
 744 static int wait_for_fpga_done(struct udevice *dev)
 745 {
 746         struct ihs_fpga_priv *priv = dev_get_priv(dev);
 747         int ctr = 0;
 748         int done_val;
 749
 750         while (1) {
 751                 done_val = dm_gpio_get_value(&priv->done_gpio);
 752                 if (done_val < 0) {
 753                         debug("%s: Error while reading done-GPIO (err = %d)\n",
 754                               dev->name, done_val);
 755                         return done_val;
 756                 }
 757
 758                 if (done_val)
 759                         return 0;
 760
 761                 mdelay(FPGA_DONE_WAIT_DELAY);
 762                 if (ctr++ > FPGA_DONE_WAIT_ROUND) {
 763                         debug("%s: FPGA init failed (done not detected)\n",
 764                               dev->name);
 765                         return -EIO;
 766                 }
 767         }
 768 }
 769
 770 static int ihs_fpga_probe(struct udevice *dev)
 771 {
 772         struct ihs_fpga_priv *priv = dev_get_priv(dev);
 773         int ret;
 774
 775         /* TODO(mario.six@gdsys.cc): Case of FPGA attached to MCLink bus */
 776
 777         ret = regmap_init_mem(dev_ofnode(dev), &priv->map);
 778         if (ret) {
 779                 debug("%s: Could not initialize regmap (err = %d)",
 780                       dev->name, ret);
 781                 return ret;
 782         }
 783
 784         ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio,
 785                                    GPIOD_IS_OUT);
 786         if (ret) {
 787                 debug("%s: Could not get reset-GPIO (err = %d)\n",
 788                       dev->name, ret);
 789                 return ret;
 790         }
 791
 792         if (!priv->reset_gpio.dev) {
 793                 debug("%s: Could not get reset-GPIO\n", dev->name);
 794                 return -ENOENT;
 795         }
 796
 797         ret = gpio_request_by_name(dev, "done-gpios", 0, &priv->done_gpio,
 798                                    GPIOD_IS_IN);
 799         if (ret) {
 800                 debug("%s: Could not get done-GPIO (err = %d)\n",
 801                       dev->name, ret);
 802                 return ret;
 803         }
 804
 805         if (!priv->done_gpio.dev) {
 806                 debug("%s: Could not get done-GPIO\n", dev->name);
 807                 return -ENOENT;
 808         }
 809
 810         ret = dm_gpio_set_value(&priv->reset_gpio, 1);
 811         if (ret) {
 812                 debug("%s: Error while setting reset-GPIO (err = %d)\n",
 813                       dev->name, ret);
 814                 return ret;
 815         }
 816
 817         /* If FPGA already runs, don't initialize again */
 818         if (do_reflection_test(dev))
 819                 goto reflection_ok;
 820
 821         ret = dm_gpio_set_value(&priv->reset_gpio, 0);
 822         if (ret) {
 823                 debug("%s: Error while setting reset-GPIO (err = %d)\n",
 824                       dev->name, ret);
 825                 return ret;
 826         }
 827
 828         ret = wait_for_fpga_done(dev);
 829         if (ret) {
 830                 debug("%s: Error while waiting for FPGA done (err = %d)\n",
 831                       dev->name, ret);
 832                 return ret;
 833         }
 834
 835         udelay(10);
 836
 837         ret = dm_gpio_set_value(&priv->reset_gpio, 1);
 838         if (ret) {
 839                 debug("%s: Error while setting reset-GPIO (err = %d)\n",
 840                       dev->name, ret);
 841                 return ret;
 842         }
 843
 844         if (!do_reflection_test(dev)) {
 845                 debug("%s: Reflection test FAILED\n", dev->name);
 846                 return -EIO;
 847         }
 848
 849 reflection_ok:
 850         printf("%s: Reflection test passed.\n", dev->name);
 851
 852         fpga_print_info(dev);
 853
 854         return 0;
 855 }
 856
 857 static const struct udevice_id ihs_fpga_ids[] = {
 858         { .compatible = "gdsys,iocon_fpga" },
 859         { .compatible = "gdsys,iocpu_fpga" },
 860         { }
 861 };
 862
 863 U_BOOT_DRIVER(ihs_fpga_bus) = {
 864         .name           = "ihs_fpga_bus",
 865         .id             = UCLASS_MISC,
 866         .of_match       = ihs_fpga_ids,
 867         .probe          = ihs_fpga_probe,
 868         .priv_auto      = sizeof(struct ihs_fpga_priv),
 869 };