drivers/misc/hi6421v600-irq.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device driver for irqs in HISI PMIC IC
   4  *
   5  * Copyright (c) 2013 Linaro Ltd.
   6  * Copyright (c) 2011 Hisilicon.
   7  * Copyright (c) 2020-2021 Huawei Technologies Co., Ltd.
   8  */
   9
  10 #include <linux/bitops.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/irq.h>
  13 #include <linux/mfd/hi6421-spmi-pmic.h>
  14 #include <linux/module.h>
  15 #include <linux/of_gpio.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/slab.h>
  18 #include <linux/irqdomain.h>
  19 #include <linux/regmap.h>
  20
  21 struct hi6421v600_irq {
  22         struct device           *dev;
  23         struct irq_domain       *domain;
  24         int                     irq;
  25         unsigned int            *irqs;
  26         struct regmap           *regmap;
  27
  28         /* Protect IRQ mask changes */
  29         spinlock_t              lock;
  30 };
  31
  32 enum hi6421v600_irq_list {
  33         OTMP = 0,
  34         VBUS_CONNECT,
  35         VBUS_DISCONNECT,
  36         ALARMON_R,
  37         HOLD_6S,
  38         HOLD_1S,
  39         POWERKEY_UP,
  40         POWERKEY_DOWN,
  41         OCP_SCP_R,
  42         COUL_R,
  43         SIM0_HPD_R,
  44         SIM0_HPD_F,
  45         SIM1_HPD_R,
  46         SIM1_HPD_F,
  47
  48         PMIC_IRQ_LIST_MAX
  49 };
  50
  51 #define HISI_IRQ_BANK_SIZE              2
  52
  53 /*
  54  * IRQ number for the power key button and mask for both UP and DOWN IRQs
  55  */
  56 #define HISI_POWERKEY_IRQ_NUM           0
  57 #define HISI_IRQ_POWERKEY_UP_DOWN       (BIT(POWERKEY_DOWN) | BIT(POWERKEY_UP))
  58
  59 /*
  60  * Registers for IRQ address and IRQ mask bits
  61  *
  62  * Please notice that we need to regmap a larger region, as other
  63  * registers are used by the irqs.
  64  * See drivers/irq/hi6421-irq.c.
  65  */
  66 #define SOC_PMIC_IRQ_MASK_0_ADDR        0x0202
  67 #define SOC_PMIC_IRQ0_ADDR              0x0212
  68
  69 /*
  70  * The IRQs are mapped as:
  71  *
  72  *      ======================  =============   ============    =====
  73  *      IRQ                     MASK REGISTER   IRQ REGISTER    BIT
  74  *      ======================  =============   ============    =====
  75  *      OTMP                    0x0202          0x212           bit 0
  76  *      VBUS_CONNECT            0x0202          0x212           bit 1
  77  *      VBUS_DISCONNECT         0x0202          0x212           bit 2
  78  *      ALARMON_R               0x0202          0x212           bit 3
  79  *      HOLD_6S                 0x0202          0x212           bit 4
  80  *      HOLD_1S                 0x0202          0x212           bit 5
  81  *      POWERKEY_UP             0x0202          0x212           bit 6
  82  *      POWERKEY_DOWN           0x0202          0x212           bit 7
  83  *
  84  *      OCP_SCP_R               0x0203          0x213           bit 0
  85  *      COUL_R                  0x0203          0x213           bit 1
  86  *      SIM0_HPD_R              0x0203          0x213           bit 2
  87  *      SIM0_HPD_F              0x0203          0x213           bit 3
  88  *      SIM1_HPD_R              0x0203          0x213           bit 4
  89  *      SIM1_HPD_F              0x0203          0x213           bit 5
  90  *      ======================  =============   ============    =====
  91  *
  92  * Each mask register contains 8 bits. The ancillary macros below
  93  * convert a number from 0 to 14 into a register address and a bit mask
  94  */
  95 #define HISI_IRQ_MASK_REG(irq_data)     (SOC_PMIC_IRQ_MASK_0_ADDR + \
  96                                          (irqd_to_hwirq(irq_data) / BITS_PER_BYTE))
  97 #define HISI_IRQ_MASK_BIT(irq_data)     BIT(irqd_to_hwirq(irq_data) & (BITS_PER_BYTE - 1))
  98 #define HISI_8BITS_MASK                 0xff
  99
 100 static irqreturn_t hi6421v600_irq_handler(int irq, void *__priv)
 101 {
 102         struct hi6421v600_irq *priv = __priv;
 103         unsigned long pending;
 104         unsigned int in;
 105         int i, offset;
 106
 107         for (i = 0; i < HISI_IRQ_BANK_SIZE; i++) {
 108                 regmap_read(priv->regmap, SOC_PMIC_IRQ0_ADDR + i, &in);
 109
 110                 /* Mark pending IRQs as handled */
 111                 regmap_write(priv->regmap, SOC_PMIC_IRQ0_ADDR + i, in);
 112
 113                 pending = in & HISI_8BITS_MASK;
 114
 115                 if (i == HISI_POWERKEY_IRQ_NUM &&
 116                     (pending & HISI_IRQ_POWERKEY_UP_DOWN) == HISI_IRQ_POWERKEY_UP_DOWN) {
 117                         /*
 118                          * If both powerkey down and up IRQs are received,
 119                          * handle them at the right order
 120                          */
 121                         generic_handle_irq(priv->irqs[POWERKEY_DOWN]);
 122                         generic_handle_irq(priv->irqs[POWERKEY_UP]);
 123                         pending &= ~HISI_IRQ_POWERKEY_UP_DOWN;
 124                 }
 125
 126                 if (!pending)
 127                         continue;
 128
 129                 for_each_set_bit(offset, &pending, BITS_PER_BYTE) {
 130                         generic_handle_irq(priv->irqs[offset + i * BITS_PER_BYTE]);
 131                 }
 132         }
 133
 134         return IRQ_HANDLED;
 135 }
 136
 137 static void hi6421v600_irq_mask(struct irq_data *d)
 138 {
 139         struct hi6421v600_irq *priv = irq_data_get_irq_chip_data(d);
 140         unsigned long flags;
 141         unsigned int data;
 142         u32 offset;
 143
 144         offset = HISI_IRQ_MASK_REG(d);
 145
 146         spin_lock_irqsave(&priv->lock, flags);
 147
 148         regmap_read(priv->regmap, offset, &data);
 149         data |= HISI_IRQ_MASK_BIT(d);
 150         regmap_write(priv->regmap, offset, data);
 151
 152         spin_unlock_irqrestore(&priv->lock, flags);
 153 }
 154
 155 static void hi6421v600_irq_unmask(struct irq_data *d)
 156 {
 157         struct hi6421v600_irq *priv = irq_data_get_irq_chip_data(d);
 158         u32 data, offset;
 159         unsigned long flags;
 160
 161         offset = HISI_IRQ_MASK_REG(d);
 162
 163         spin_lock_irqsave(&priv->lock, flags);
 164
 165         regmap_read(priv->regmap, offset, &data);
 166         data &= ~HISI_IRQ_MASK_BIT(d);
 167         regmap_write(priv->regmap, offset, data);
 168
 169         spin_unlock_irqrestore(&priv->lock, flags);
 170 }
 171
 172 static struct irq_chip hi6421v600_pmu_irqchip = {
 173         .name           = "hi6421v600-irq",
 174         .irq_mask       = hi6421v600_irq_mask,
 175         .irq_unmask     = hi6421v600_irq_unmask,
 176         .irq_disable    = hi6421v600_irq_mask,
 177         .irq_enable     = hi6421v600_irq_unmask,
 178 };
 179
 180 static int hi6421v600_irq_map(struct irq_domain *d, unsigned int virq,
 181                               irq_hw_number_t hw)
 182 {
 183         struct hi6421v600_irq *priv = d->host_data;
 184
 185         irq_set_chip_and_handler_name(virq, &hi6421v600_pmu_irqchip,
 186                                       handle_simple_irq, "hi6421v600");
 187         irq_set_chip_data(virq, priv);
 188         irq_set_irq_type(virq, IRQ_TYPE_NONE);
 189
 190         return 0;
 191 }
 192
 193 static const struct irq_domain_ops hi6421v600_domain_ops = {
 194         .map    = hi6421v600_irq_map,
 195         .xlate  = irq_domain_xlate_twocell,
 196 };
 197
 198 static void hi6421v600_irq_init(struct hi6421v600_irq *priv)
 199 {
 200         int i;
 201         unsigned int pending;
 202
 203         /* Mask all IRQs */
 204         for (i = 0; i < HISI_IRQ_BANK_SIZE; i++)
 205                 regmap_write(priv->regmap, SOC_PMIC_IRQ_MASK_0_ADDR + i,
 206                              HISI_8BITS_MASK);
 207
 208         /* Mark all IRQs as handled */
 209         for (i = 0; i < HISI_IRQ_BANK_SIZE; i++) {
 210                 regmap_read(priv->regmap, SOC_PMIC_IRQ0_ADDR + i, &pending);
 211                 regmap_write(priv->regmap, SOC_PMIC_IRQ0_ADDR + i,
 212                              HISI_8BITS_MASK);
 213         }
 214 }
 215
 216 static int hi6421v600_irq_probe(struct platform_device *pdev)
 217 {
 218         struct device *pmic_dev = pdev->dev.parent;
 219         struct device_node *np = pmic_dev->of_node;
 220         struct platform_device *pmic_pdev;
 221         struct device *dev = &pdev->dev;
 222         struct hi6421v600_irq *priv;
 223         struct hi6421_spmi_pmic *pmic;
 224         unsigned int virq;
 225         int i, ret;
 226
 227         /*
 228          * This driver is meant to be called by hi6421-spmi-core,
 229          * which should first set drvdata. If this doesn't happen, hit
 230          * a warn on and return.
 231          */
 232         pmic = dev_get_drvdata(pmic_dev);
 233         if (WARN_ON(!pmic))
 234                 return -ENODEV;
 235
 236         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 237         if (!priv)
 238                 return -ENOMEM;
 239
 240         priv->dev = dev;
 241         priv->regmap = pmic->regmap;
 242
 243         spin_lock_init(&priv->lock);
 244
 245         pmic_pdev = container_of(pmic_dev, struct platform_device, dev);
 246
 247         priv->irq = platform_get_irq(pmic_pdev, 0);
 248         if (priv->irq < 0) {
 249                 dev_err(dev, "Error %d when getting IRQs\n", priv->irq);
 250                 return priv->irq;
 251         }
 252
 253         platform_set_drvdata(pdev, priv);
 254
 255         hi6421v600_irq_init(priv);
 256
 257         priv->irqs = devm_kzalloc(dev, PMIC_IRQ_LIST_MAX * sizeof(int), GFP_KERNEL);
 258         if (!priv->irqs)
 259                 return -ENOMEM;
 260
 261         priv->domain = irq_domain_add_simple(np, PMIC_IRQ_LIST_MAX, 0,
 262                                              &hi6421v600_domain_ops, priv);
 263         if (!priv->domain) {
 264                 dev_err(dev, "Failed to create IRQ domain\n");
 265                 return -ENODEV;
 266         }
 267
 268         for (i = 0; i < PMIC_IRQ_LIST_MAX; i++) {
 269                 virq = irq_create_mapping(priv->domain, i);
 270                 if (!virq) {
 271                         dev_err(dev, "Failed to map H/W IRQ\n");
 272                         return -ENODEV;
 273                 }
 274                 priv->irqs[i] = virq;
 275         }
 276
 277         ret = devm_request_threaded_irq(dev,
 278                                         priv->irq, hi6421v600_irq_handler,
 279                                         NULL,
 280                                         IRQF_TRIGGER_LOW | IRQF_SHARED | IRQF_NO_SUSPEND,
 281                                         "pmic", priv);
 282         if (ret < 0) {
 283                 dev_err(dev, "Failed to start IRQ handling thread: error %d\n",
 284                         ret);
 285                 return ret;
 286         }
 287
 288         return 0;
 289 }
 290
 291 static const struct platform_device_id hi6421v600_irq_table[] = {
 292         { .name = "hi6421v600-irq" },
 293         {},
 294 };
 295 MODULE_DEVICE_TABLE(platform, hi6421v600_irq_table);
 296
 297 static struct platform_driver hi6421v600_irq_driver = {
 298         .id_table = hi6421v600_irq_table,
 299         .driver = {
 300                 .name = "hi6421v600-irq",
 301         },
 302         .probe  = hi6421v600_irq_probe,
 303 };
 304 module_platform_driver(hi6421v600_irq_driver);
 305
 306 MODULE_DESCRIPTION("HiSilicon Hi6421v600 IRQ driver");
 307 MODULE_LICENSE("GPL v2");