drivers/misc/habanalabs/include/gaudi/asic_reg/gaudi_regs.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright 2016-2020 HabanaLabs, Ltd.
   4  * All Rights Reserved.
   5  *
   6  */
   7
   8 #ifndef ASIC_REG_GAUDI_REGS_H_
   9 #define ASIC_REG_GAUDI_REGS_H_
  10
  11 #include "gaudi_blocks.h"
  12 #include "psoc_global_conf_regs.h"
  13 #include "psoc_timestamp_regs.h"
  14 #include "cpu_if_regs.h"
  15 #include "mmu_up_regs.h"
  16 #include "stlb_regs.h"
  17 #include "dma0_qm_regs.h"
  18 #include "dma1_qm_regs.h"
  19 #include "dma2_qm_regs.h"
  20 #include "dma3_qm_regs.h"
  21 #include "dma4_qm_regs.h"
  22 #include "dma5_qm_regs.h"
  23 #include "dma6_qm_regs.h"
  24 #include "dma7_qm_regs.h"
  25 #include "dma0_core_regs.h"
  26 #include "dma1_core_regs.h"
  27 #include "dma2_core_regs.h"
  28 #include "dma3_core_regs.h"
  29 #include "dma4_core_regs.h"
  30 #include "dma5_core_regs.h"
  31 #include "dma6_core_regs.h"
  32 #include "dma7_core_regs.h"
  33 #include "mme0_ctrl_regs.h"
  34 #include "mme1_ctrl_regs.h"
  35 #include "mme2_ctrl_regs.h"
  36 #include "mme3_ctrl_regs.h"
  37 #include "mme0_qm_regs.h"
  38 #include "mme2_qm_regs.h"
  39 #include "tpc0_cfg_regs.h"
  40 #include "tpc1_cfg_regs.h"
  41 #include "tpc2_cfg_regs.h"
  42 #include "tpc3_cfg_regs.h"
  43 #include "tpc4_cfg_regs.h"
  44 #include "tpc5_cfg_regs.h"
  45 #include "tpc6_cfg_regs.h"
  46 #include "tpc7_cfg_regs.h"
  47 #include "tpc0_qm_regs.h"
  48 #include "tpc1_qm_regs.h"
  49 #include "tpc2_qm_regs.h"
  50 #include "tpc3_qm_regs.h"
  51 #include "tpc4_qm_regs.h"
  52 #include "tpc5_qm_regs.h"
  53 #include "tpc6_qm_regs.h"
  54 #include "tpc7_qm_regs.h"
  55 #include "dma_if_e_n_down_ch0_regs.h"
  56 #include "dma_if_e_n_down_ch1_regs.h"
  57 #include "dma_if_e_s_down_ch0_regs.h"
  58 #include "dma_if_e_s_down_ch1_regs.h"
  59 #include "dma_if_w_n_down_ch0_regs.h"
  60 #include "dma_if_w_n_down_ch1_regs.h"
  61 #include "dma_if_w_s_down_ch0_regs.h"
  62 #include "dma_if_w_s_down_ch1_regs.h"
  63 #include "dma_if_e_n_regs.h"
  64 #include "dma_if_e_s_regs.h"
  65 #include "dma_if_w_n_regs.h"
  66 #include "dma_if_w_s_regs.h"
  67 #include "nif_rtr_ctrl_0_regs.h"
  68 #include "nif_rtr_ctrl_1_regs.h"
  69 #include "nif_rtr_ctrl_2_regs.h"
  70 #include "nif_rtr_ctrl_3_regs.h"
  71 #include "nif_rtr_ctrl_4_regs.h"
  72 #include "nif_rtr_ctrl_5_regs.h"
  73 #include "nif_rtr_ctrl_6_regs.h"
  74 #include "nif_rtr_ctrl_7_regs.h"
  75 #include "sif_rtr_ctrl_0_regs.h"
  76 #include "sif_rtr_ctrl_1_regs.h"
  77 #include "sif_rtr_ctrl_2_regs.h"
  78 #include "sif_rtr_ctrl_3_regs.h"
  79 #include "sif_rtr_ctrl_4_regs.h"
  80 #include "sif_rtr_ctrl_5_regs.h"
  81 #include "sif_rtr_ctrl_6_regs.h"
  82 #include "sif_rtr_ctrl_7_regs.h"
  83 #include "psoc_etr_regs.h"
  84 #include "psoc_cpu_pll_regs.h"
  85
  86 #include "dma0_qm_masks.h"
  87 #include "mme0_qm_masks.h"
  88 #include "tpc0_qm_masks.h"
  89 #include "dma0_core_masks.h"
  90 #include "tpc0_cfg_masks.h"
  91 #include "psoc_global_conf_masks.h"
  92
  93 #include "nic0_qm0_regs.h"
  94 #include "nic1_qm0_regs.h"
  95 #include "nic2_qm0_regs.h"
  96 #include "nic3_qm0_regs.h"
  97 #include "nic4_qm0_regs.h"
  98 #include "nic0_qm1_regs.h"
  99 #include "nic1_qm1_regs.h"
 100 #include "nic2_qm1_regs.h"
 101 #include "nic3_qm1_regs.h"
 102 #include "nic4_qm1_regs.h"
 103
 104 #include "nic0_qm0_masks.h"
 105
 106 #define GAUDI_ECC_MEM_SEL_OFFSET                0xF18
 107 #define GAUDI_ECC_ADDRESS_OFFSET                0xF1C
 108 #define GAUDI_ECC_SYNDROME_OFFSET               0xF20
 109 #define GAUDI_ECC_MEM_INFO_CLR_OFFSET           0xF28
 110 #define GAUDI_ECC_MEM_INFO_CLR_SERR_MASK        BIT(8)
 111 #define GAUDI_ECC_MEM_INFO_CLR_DERR_MASK        BIT(9)
 112 #define GAUDI_ECC_SERR0_OFFSET                  0xF30
 113 #define GAUDI_ECC_DERR0_OFFSET                  0xF40
 114
 115 #define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0                     0x492000
 116 #define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0               0x494000
 117 #define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0               0x494800
 118 #define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_DATA_0                0x495000
 119 #define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0                     0x495800
 120 #define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0                  0x496000
 121 #define mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_SOB_OBJ_0                     0x4B2000
 122 #define mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_MON_STATUS_0                  0x4B6000
 123 #define mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_SOB_OBJ_0                     0x4D2000
 124 #define mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_MON_STATUS_0                  0x4D6000
 125 #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0                     0x4F2000
 126 #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_1                     0x4F2004
 127 #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047                  0x4F3FFC
 128 #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0               0x4F4000
 129 #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0               0x4F4800
 130 #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_DATA_0                0x4F5000
 131 #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_ARM_0                     0x4F5800
 132 #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0                  0x4F6000
 133 #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_511                0x4F67FC
 134
 135 #define mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AW                            0x300400
 136 #define mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AW                            0x310400
 137 #define mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AW                            0x320400
 138 #define mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AW                            0x330400
 139 #define mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AW                            0x340400
 140 #define mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AW                            0x350400
 141 #define mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AW                            0x360400
 142 #define mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AW                            0x370400
 143
 144 #define mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AR                            0x300490
 145 #define mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AR                            0x310490
 146 #define mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AR                            0x320490
 147 #define mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AR                            0x330490
 148 #define mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AR                            0x340490
 149 #define mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AR                            0x350490
 150 #define mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AR                            0x360490
 151 #define mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AR                            0x370490
 152
 153 #define mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0                          0x300410
 154 #define mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0                          0x310410
 155 #define mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0                          0x320410
 156 #define mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0                          0x330410
 157 #define mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0                          0x340410
 158 #define mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0                          0x350410
 159 #define mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0                          0x360410
 160 #define mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0                          0x370410
 161
 162 #define mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0                          0x300450
 163 #define mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0                          0x310450
 164 #define mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0                          0x320450
 165 #define mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0                          0x330450
 166 #define mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0                          0x340450
 167 #define mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0                          0x350450
 168 #define mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0                          0x360450
 169 #define mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0                          0x370450
 170
 171 #define mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0                          0x3004A0
 172 #define mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0                          0x3104A0
 173 #define mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0                          0x3204A0
 174 #define mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0                          0x3304A0
 175 #define mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0                          0x3404A0
 176 #define mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0                          0x3504A0
 177 #define mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0                          0x3604A0
 178 #define mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0                          0x3704A0
 179
 180 #define mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0                          0x3004E0
 181 #define mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0                          0x3104E0
 182 #define mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0                          0x3204E0
 183 #define mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0                          0x3304E0
 184 #define mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0                          0x3404E0
 185 #define mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0                          0x3504E0
 186 #define mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0                          0x3604E0
 187 #define mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0                          0x3704E0
 188
 189 #define mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AW                            0x380400
 190 #define mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AW                            0x390400
 191 #define mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AW                            0x3A0400
 192 #define mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AW                            0x3B0400
 193 #define mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AW                            0x3C0400
 194 #define mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AW                            0x3D0400
 195 #define mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AW                            0x3E0400
 196 #define mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AW                            0x3F0400
 197
 198 #define mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AR                            0x380490
 199 #define mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AR                            0x390490
 200 #define mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AR                            0x3A0490
 201 #define mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AR                            0x3B0490
 202 #define mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AR                            0x3C0490
 203 #define mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AR                            0x3D0490
 204 #define mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AR                            0x3E0490
 205 #define mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AR                            0x3F0490
 206
 207 #define mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0                          0x380410
 208 #define mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0                          0x390410
 209 #define mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0                          0x3A0410
 210 #define mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0                          0x3B0410
 211 #define mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0                          0x3C0410
 212 #define mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0                          0x3D0410
 213 #define mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0                          0x3E0410
 214 #define mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0                          0x3F0410
 215
 216 #define mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0                          0x380450
 217 #define mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0                          0x390450
 218 #define mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0                          0x3A0450
 219 #define mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0                          0x3B0450
 220 #define mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0                          0x3C0450
 221 #define mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0                          0x3D0450
 222 #define mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0                          0x3E0450
 223 #define mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0                          0x3F0450
 224
 225 #define mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0                          0x3804A0
 226 #define mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0                          0x3904A0
 227 #define mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0                          0x3A04A0
 228 #define mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0                          0x3B04A0
 229 #define mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0                          0x3C04A0
 230 #define mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0                          0x3D04A0
 231 #define mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0                          0x3E04A0
 232 #define mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0                          0x3F04A0
 233
 234 #define mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0                          0x3804E0
 235 #define mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0                          0x3904E0
 236 #define mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0                          0x3A04E0
 237 #define mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0                          0x3B04E0
 238 #define mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0                          0x3C04E0
 239 #define mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0                          0x3D04E0
 240 #define mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0                          0x3E04E0
 241 #define mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0                          0x3F04E0
 242
 243 #define mmDMA_IF_W_S_DOWN_RSP_MID_WGHT_0                             0x489030
 244 #define mmDMA_IF_W_S_DOWN_RSP_MID_WGHT_1                             0x489034
 245
 246 #define mmDMA_IF_E_S_DOWN_RSP_MID_WGHT_0                             0x4A9030
 247 #define mmDMA_IF_E_S_DOWN_RSP_MID_WGHT_1                             0x4A9034
 248
 249 #define mmDMA_IF_W_N_DOWN_RSP_MID_WGHT_0                             0x4C9030
 250 #define mmDMA_IF_W_N_DOWN_RSP_MID_WGHT_1                             0x4C9034
 251
 252 #define mmDMA_IF_E_N_DOWN_RSP_MID_WGHT_0                             0x4E9030
 253 #define mmDMA_IF_E_N_DOWN_RSP_MID_WGHT_1                             0x4E9034
 254
 255 #define mmMME1_QM_GLBL_CFG0                                          0xE8000
 256 #define mmMME1_QM_GLBL_STS0                                          0xE8038
 257
 258 #define mmMME0_SBAB_SB_STALL                                         0x4002C
 259 #define mmMME0_SBAB_ARUSER0                                          0x40034
 260 #define mmMME0_SBAB_ARUSER1                                          0x40038
 261 #define mmMME0_SBAB_PROT                                             0x40050
 262
 263 #define mmMME1_SBAB_SB_STALL                                         0xC002C
 264 #define mmMME1_SBAB_ARUSER0                                          0xC0034
 265 #define mmMME1_SBAB_ARUSER1                                          0xC0038
 266 #define mmMME1_SBAB_PROT                                             0xC0050
 267
 268 #define mmMME2_SBAB_SB_STALL                                         0x14002C
 269 #define mmMME2_SBAB_ARUSER0                                          0x140034
 270 #define mmMME2_SBAB_ARUSER1                                          0x140038
 271 #define mmMME2_SBAB_PROT                                             0x140050
 272
 273 #define mmMME3_SBAB_SB_STALL                                         0x1C002C
 274 #define mmMME3_SBAB_ARUSER0                                          0x1C0034
 275 #define mmMME3_SBAB_ARUSER1                                          0x1C0038
 276 #define mmMME3_SBAB_PROT                                             0x1C0050
 277
 278 #define mmMME0_ACC_ACC_STALL                                         0x20028
 279 #define mmMME0_ACC_WBC                                               0x20038
 280 #define mmMME0_ACC_PROT                                              0x20050
 281
 282 #define mmMME1_ACC_ACC_STALL                                         0xA0028
 283 #define mmMME1_ACC_WBC                                               0xA0038
 284 #define mmMME1_ACC_PROT                                              0xA0050
 285
 286 #define mmMME2_ACC_ACC_STALL                                         0x120028
 287 #define mmMME2_ACC_WBC                                               0x120038
 288 #define mmMME2_ACC_PROT                                              0x120050
 289
 290 #define mmMME3_ACC_ACC_STALL                                         0x1A0028
 291 #define mmMME3_ACC_WBC                                               0x1A0038
 292 #define mmMME3_ACC_PROT                                              0x1A0050
 293
 294 #define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR                         0x800040
 295
 296 #define mmPSOC_EFUSE_READ                                            0xC4A000
 297 #define mmPSOC_EFUSE_DATA_0                                          0xC4A080
 298
 299 #define mmPCIE_WRAP_MAX_OUTSTAND                                     0xC01B20
 300 #define mmPCIE_WRAP_LBW_PROT_OVR                                     0xC01B48
 301 #define mmPCIE_WRAP_HBW_DRAIN_CFG                                    0xC01D54
 302 #define mmPCIE_WRAP_LBW_DRAIN_CFG                                    0xC01D5C
 303
 304 #define mmPCIE_MSI_INTR_0                                            0xC13000
 305
 306 #define mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG                           0xC02000
 307
 308 #define mmPCIE_AUX_FLR_CTRL                                          0xC07394
 309 #define mmPCIE_AUX_DBI                                               0xC07490
 310
 311 #define mmPSOC_PCI_PLL_NR                                            0xC72100
 312 #define mmSRAM_W_PLL_NR                                              0x4C8100
 313 #define mmPSOC_HBM_PLL_NR                                            0xC74100
 314 #define mmNIC0_PLL_NR                                                0xCF9100
 315 #define mmDMA_W_PLL_NR                                               0x487100
 316 #define mmMESH_W_PLL_NR                                              0x4C7100
 317 #define mmPSOC_MME_PLL_NR                                            0xC71100
 318 #define mmPSOC_TPC_PLL_NR                                            0xC73100
 319 #define mmIF_W_PLL_NR                                                0x488100
 320
 321 #endif /* ASIC_REG_GAUDI_REGS_H_ */