11 #define MAX_DMA_CHUNK_SIZE (0x80000)
13 #define MAX_DMA_TRANSFER_TASKS (64)
15 #define DMAC_STATUS_SUCCESS (0)
16 #define DMAC_STATUS_ERROR (-1)
18 #define SPRD_GPS_DMA_IRQ (44)
20 #define DMAC_BLOCK_SIZE (0xffff)
22 #define CH_STAT_MASK (0x0000000f)
24 #define CHANNEL_ENABLE (1)
25 #define CHANNEL_DISABLE (0)
27 #define DMAC_REMAP_NOACP 1
29 #define REG_PERI_CTRL0 (IO_ADDRESS(0xFCA09000))
31 #define RCHAIN_EN (0x02)
32 #define RCHAIN_EN_MASK (0xfffffffc)
34 //#define NUMBER_1K (1024)
36 #define NUMBER_16K (16*1024)
38 #define NUMBER_64K (64*1024)
40 #define REG_DMAC_BASE CG_DRIVER_DMA_BASE_PA
43 #define REG_DMAC_CX_CURR_CNT0 (IO_ADDRESS(REG_DMAC_BASE) + 0x0704)
45 typedef struct DMA_CFG_S
47 unsigned int src_addr;
48 unsigned int dma_phys;
49 unsigned int dma_size;
50 void __iomem *dma_virt;
52 unsigned int lli_count;
53 unsigned int lli_size;
54 unsigned int lli_addr_pa;
60 unsigned int cx_config_arg;
63 unsigned int ch_en : 1;
64 unsigned int itc_en : 1;
65 unsigned int flow_ctrl : 2;
66 unsigned int peri : 6;
67 unsigned int reserve1 : 2;
69 unsigned int reserve2 : 1;
71 unsigned int reserve3 : 1;
74 unsigned int dmode : 1;
75 unsigned int smode : 1;
81 int CgCpuDmaLLIDataCopyFromGps(TCgCpuDmaTask *apDmaTask, U32 aDmaTaskCount, U32 aDeviceAddress, U32 aDestAddress);
83 int CgCpuDmaDataCopyFromGps(TCgCpuDmaTask *apDmaTask, U32 aDmaTaskCount, U32 aDeviceAddress, U32 aDestAddress);