2 * (C) Copyright 2009-2013 ADVANSEE
3 * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
5 * Based on the mpc512x iim code:
6 * Copyright 2008 Silicon Turnkey Express, Inc.
7 * Martha Marx <mmarx@silicontkx.com>
9 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/errno.h>
16 #ifndef CONFIG_MPC512X
17 #include <asm/arch/imx-regs.h>
20 /* FSL IIM-specific constants */
21 #define STAT_BUSY 0x80
22 #define STAT_PRGD 0x02
23 #define STAT_SNSD 0x01
25 #define STATM_PRGD_M 0x02
26 #define STATM_SNSD_M 0x01
34 #define ERR_PARITYE 0x02
36 #define EMASK_PRGE_M 0x80
37 #define EMASK_WPE_M 0x40
38 #define EMASK_OPE_M 0x20
39 #define EMASK_RPE_M 0x10
40 #define EMASK_WLRE_M 0x08
41 #define EMASK_SNSE_M 0x04
42 #define EMASK_PARITYE_M 0x02
45 #define FCTL_PRG_LENGTH_MASK 0x70
46 #define FCTL_ESNS_N 0x08
47 #define FCTL_ESNS_0 0x04
48 #define FCTL_ESNS_1 0x02
51 #define UA_A_BANK_MASK 0x38
52 #define UA_A_ROWH_MASK 0x07
54 #define LA_A_ROWL_MASK 0xf8
55 #define LA_A_BIT_MASK 0x07
57 #define PREV_PROD_REV_MASK 0xf8
58 #define PREV_PROD_VT_MASK 0x07
60 /* Select the correct accessors depending on endianness */
61 #if __BYTE_ORDER == __LITTLE_ENDIAN
62 #define iim_read32 in_le32
63 #define iim_write32 out_le32
64 #define iim_clrsetbits32 clrsetbits_le32
65 #define iim_clrbits32 clrbits_le32
66 #define iim_setbits32 setbits_le32
67 #elif __BYTE_ORDER == __BIG_ENDIAN
68 #define iim_read32 in_be32
69 #define iim_write32 out_be32
70 #define iim_clrsetbits32 clrsetbits_be32
71 #define iim_clrbits32 clrbits_be32
72 #define iim_setbits32 setbits_be32
74 #error Endianess is not defined: please fix to continue
77 /* IIM control registers */
96 static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int assert,
99 *regs = (struct fsl_iim *)IIM_BASE_ADDR;
101 if (bank >= ARRAY_SIZE((*regs)->bank) ||
102 word >= ARRAY_SIZE((*regs)->bank[0].word) ||
104 printf("fsl_iim %s(): Invalid argument\n", caller);
111 static void clear_status(struct fsl_iim *regs)
113 iim_setbits32(®s->stat, 0);
114 iim_setbits32(®s->err, 0);
117 static void finish_access(struct fsl_iim *regs, u32 *stat, u32 *err)
119 *stat = iim_read32(®s->stat);
120 *err = iim_read32(®s->err);
124 static int prepare_read(struct fsl_iim **regs, u32 bank, u32 word, u32 *val,
129 ret = prepare_access(regs, bank, word, val != NULL, caller);
138 int fuse_read(u32 bank, u32 word, u32 *val)
140 struct fsl_iim *regs;
144 ret = prepare_read(®s, bank, word, val, __func__);
148 *val = iim_read32(®s->bank[bank].word[word]);
149 finish_access(regs, &stat, &err);
152 puts("fsl_iim fuse_read(): Read protect error\n");
159 static void direct_access(struct fsl_iim *regs, u32 bank, u32 word, u32 bit,
160 u32 fctl, u32 *stat, u32 *err)
162 iim_write32(®s->ua, bank << 3 | word >> 5);
163 iim_write32(®s->la, (word << 3 | bit) & 0xff);
164 if (fctl == FCTL_PRG)
165 iim_write32(®s->prg_p, 0xaa);
166 iim_setbits32(®s->fctl, fctl);
167 while (iim_read32(®s->stat) & STAT_BUSY)
169 finish_access(regs, stat, err);
172 int fuse_sense(u32 bank, u32 word, u32 *val)
174 struct fsl_iim *regs;
178 ret = prepare_read(®s, bank, word, val, __func__);
182 direct_access(regs, bank, word, 0, FCTL_ESNS_N, &stat, &err);
184 if (err & ERR_SNSE) {
185 puts("fsl_iim fuse_sense(): Explicit sense cycle error\n");
189 if (!(stat & STAT_SNSD)) {
190 puts("fsl_iim fuse_sense(): Explicit sense cycle did not complete\n");
194 *val = iim_read32(®s->sdat);
198 static int prog_bit(struct fsl_iim *regs, u32 bank, u32 word, u32 bit)
203 direct_access(regs, bank, word, bit, FCTL_PRG, &stat, &err);
204 iim_write32(®s->prg_p, 0x00);
206 if (err & ERR_PRGE) {
207 puts("fsl_iim fuse_prog(): Program error\n");
212 puts("fsl_iim fuse_prog(): Write protect error\n");
216 if (!(stat & STAT_PRGD)) {
217 puts("fsl_iim fuse_prog(): Program did not complete\n");
224 static int prepare_write(struct fsl_iim **regs, u32 bank, u32 word, u32 val,
227 return prepare_access(regs, bank, word, !(val & ~0xff), caller);
230 int fuse_prog(u32 bank, u32 word, u32 val)
232 struct fsl_iim *regs;
236 ret = prepare_write(®s, bank, word, val, __func__);
240 for (bit = 0; val; bit++, val >>= 1)
242 ret = prog_bit(regs, bank, word, bit);
250 int fuse_override(u32 bank, u32 word, u32 val)
252 struct fsl_iim *regs;
256 ret = prepare_write(®s, bank, word, val, __func__);
261 iim_write32(®s->bank[bank].word[word], val);
262 finish_access(regs, &stat, &err);
265 puts("fsl_iim fuse_override(): Override protect error\n");