1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at25.c -- support most SPI EEPROMs, such as Atmel AT25 models
4 * and Cypress FRAMs FM25 models
6 * Copyright (C) 2006 David Brownell
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/slab.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/sched.h>
16 #include <linux/nvmem-provider.h>
17 #include <linux/spi/spi.h>
18 #include <linux/spi/eeprom.h>
19 #include <linux/property.h>
20 #include <linux/math.h>
23 * NOTE: this is an *EEPROM* driver. The vagaries of product naming
24 * mean that some AT25 products are EEPROMs, and others are FLASH.
25 * Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver,
28 * EEPROMs that can be used with this driver include, for example:
32 #define FM25_SN_LEN 8 /* serial number length */
33 #define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */
36 struct spi_device *spi;
38 struct spi_eeprom chip;
40 struct nvmem_config nvmem_config;
41 struct nvmem_device *nvmem;
42 u8 sernum[FM25_SN_LEN];
43 u8 command[EE_MAXADDRLEN + 1];
46 #define AT25_WREN 0x06 /* latch the write enable */
47 #define AT25_WRDI 0x04 /* reset the write enable */
48 #define AT25_RDSR 0x05 /* read status register */
49 #define AT25_WRSR 0x01 /* write status register */
50 #define AT25_READ 0x03 /* read byte(s) */
51 #define AT25_WRITE 0x02 /* write byte(s)/sector */
52 #define FM25_SLEEP 0xb9 /* enter sleep mode */
53 #define FM25_RDID 0x9f /* read device ID */
54 #define FM25_RDSN 0xc3 /* read S/N */
56 #define AT25_SR_nRDY 0x01 /* nRDY = write-in-progress */
57 #define AT25_SR_WEN 0x02 /* write enable (latched) */
58 #define AT25_SR_BP0 0x04 /* BP for software writeprotect */
59 #define AT25_SR_BP1 0x08
60 #define AT25_SR_WPEN 0x80 /* writeprotect enable */
62 #define AT25_INSTR_BIT3 0x08 /* Additional address bit in instr */
64 #define FM25_ID_LEN 9 /* ID length */
66 /* Specs often allow 5 msec for a page write, sometimes 20 msec;
67 * it's important to recover from write timeouts.
71 /*-------------------------------------------------------------------------*/
73 #define io_limit PAGE_SIZE /* bytes */
75 static int at25_ee_read(void *priv, unsigned int offset,
76 void *val, size_t count)
78 struct at25_data *at25 = priv;
82 struct spi_transfer t[2];
86 if (unlikely(offset >= at25->chip.byte_len))
88 if ((offset + count) > at25->chip.byte_len)
89 count = at25->chip.byte_len - offset;
96 if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
97 if (offset >= (1U << (at25->addrlen * 8)))
98 instr |= AT25_INSTR_BIT3;
100 mutex_lock(&at25->lock);
104 /* 8/16/24-bit address is written MSB first */
105 switch (at25->addrlen) {
106 default: /* case 3 */
107 *cp++ = offset >> 16;
113 case 0: /* can't happen: for better codegen */
117 spi_message_init(&m);
118 memset(t, 0, sizeof(t));
120 t[0].tx_buf = at25->command;
121 t[0].len = at25->addrlen + 1;
122 spi_message_add_tail(&t[0], &m);
126 spi_message_add_tail(&t[1], &m);
128 /* Read it all at once.
130 * REVISIT that's potentially a problem with large chips, if
131 * other devices on the bus need to be accessed regularly or
132 * this chip is clocked very slowly
134 status = spi_sync(at25->spi, &m);
135 dev_dbg(&at25->spi->dev, "read %zu bytes at %d --> %zd\n",
136 count, offset, status);
138 mutex_unlock(&at25->lock);
143 * read extra registers as ID or serial number
145 static int fm25_aux_read(struct at25_data *at25, u8 *buf, uint8_t command,
149 struct spi_transfer t[2];
150 struct spi_message m;
152 spi_message_init(&m);
153 memset(t, 0, sizeof(t));
155 t[0].tx_buf = at25->command;
157 spi_message_add_tail(&t[0], &m);
161 spi_message_add_tail(&t[1], &m);
163 mutex_lock(&at25->lock);
165 at25->command[0] = command;
167 status = spi_sync(at25->spi, &m);
168 dev_dbg(&at25->spi->dev, "read %d aux bytes --> %d\n", len, status);
170 mutex_unlock(&at25->lock);
174 static ssize_t sernum_show(struct device *dev, struct device_attribute *attr, char *buf)
176 struct at25_data *at25;
178 at25 = dev_get_drvdata(dev);
179 return sysfs_emit(buf, "%*ph\n", (int)sizeof(at25->sernum), at25->sernum);
181 static DEVICE_ATTR_RO(sernum);
183 static struct attribute *sernum_attrs[] = {
184 &dev_attr_sernum.attr,
187 ATTRIBUTE_GROUPS(sernum);
189 static int at25_ee_write(void *priv, unsigned int off, void *val, size_t count)
191 struct at25_data *at25 = priv;
192 const char *buf = val;
197 if (unlikely(off >= at25->chip.byte_len))
199 if ((off + count) > at25->chip.byte_len)
200 count = at25->chip.byte_len - off;
201 if (unlikely(!count))
204 /* Temp buffer starts with command and address */
205 buf_size = at25->chip.page_size;
206 if (buf_size > io_limit)
208 bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL);
212 /* For write, rollover is within the page ... so we write at
213 * most one page, then manually roll over to the next page.
215 mutex_lock(&at25->lock);
217 unsigned long timeout, retries;
219 unsigned offset = (unsigned) off;
225 status = spi_write(at25->spi, cp, 1);
227 dev_dbg(&at25->spi->dev, "WREN --> %d\n", status);
232 if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
233 if (offset >= (1U << (at25->addrlen * 8)))
234 instr |= AT25_INSTR_BIT3;
237 /* 8/16/24-bit address is written MSB first */
238 switch (at25->addrlen) {
239 default: /* case 3 */
240 *cp++ = offset >> 16;
246 case 0: /* can't happen: for better codegen */
250 /* Write as much of a page as we can */
251 segment = buf_size - (offset % buf_size);
254 memcpy(cp, buf, segment);
255 status = spi_write(at25->spi, bounce,
256 segment + at25->addrlen + 1);
257 dev_dbg(&at25->spi->dev, "write %u bytes at %u --> %d\n",
258 segment, offset, status);
262 /* REVISIT this should detect (or prevent) failed writes
263 * to readonly sections of the EEPROM...
266 /* Wait for non-busy status */
267 timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT);
271 sr = spi_w8r8(at25->spi, AT25_RDSR);
272 if (sr < 0 || (sr & AT25_SR_nRDY)) {
273 dev_dbg(&at25->spi->dev,
274 "rdsr --> %d (%02x)\n", sr, sr);
275 /* at HZ=100, this is sloooow */
279 if (!(sr & AT25_SR_nRDY))
281 } while (retries++ < 3 || time_before_eq(jiffies, timeout));
283 if ((sr < 0) || (sr & AT25_SR_nRDY)) {
284 dev_err(&at25->spi->dev,
285 "write %u bytes offset %u, timeout after %u msecs\n",
287 jiffies_to_msecs(jiffies -
288 (timeout - EE_TIMEOUT)));
299 mutex_unlock(&at25->lock);
305 /*-------------------------------------------------------------------------*/
307 static int at25_fw_to_chip(struct device *dev, struct spi_eeprom *chip)
311 memset(chip, 0, sizeof(*chip));
312 strncpy(chip->name, "at25", sizeof(chip->name));
314 if (device_property_read_u32(dev, "size", &val) == 0 ||
315 device_property_read_u32(dev, "at25,byte-len", &val) == 0) {
316 chip->byte_len = val;
318 dev_err(dev, "Error: missing \"size\" property\n");
322 if (device_property_read_u32(dev, "pagesize", &val) == 0 ||
323 device_property_read_u32(dev, "at25,page-size", &val) == 0) {
324 chip->page_size = val;
326 dev_err(dev, "Error: missing \"pagesize\" property\n");
330 if (device_property_read_u32(dev, "at25,addr-mode", &val) == 0) {
331 chip->flags = (u16)val;
333 if (device_property_read_u32(dev, "address-width", &val)) {
335 "Error: missing \"address-width\" property\n");
340 chip->flags |= EE_INSTR_BIT3_IS_ADDR;
343 chip->flags |= EE_ADDR1;
346 chip->flags |= EE_ADDR2;
349 chip->flags |= EE_ADDR3;
353 "Error: bad \"address-width\" property: %u\n",
357 if (device_property_present(dev, "read-only"))
358 chip->flags |= EE_READONLY;
363 static const struct of_device_id at25_of_match[] = {
364 { .compatible = "atmel,at25",},
365 { .compatible = "cypress,fm25",},
368 MODULE_DEVICE_TABLE(of, at25_of_match);
370 static const struct spi_device_id at25_spi_ids[] = {
375 MODULE_DEVICE_TABLE(spi, at25_spi_ids);
377 static int at25_probe(struct spi_device *spi)
379 struct at25_data *at25 = NULL;
383 u8 sernum[FM25_SN_LEN];
387 err = device_property_match_string(&spi->dev, "compatible", "cypress,fm25");
393 at25 = devm_kzalloc(&spi->dev, sizeof(struct at25_data), GFP_KERNEL);
397 /* Chip description */
398 if (spi->dev.platform_data) {
399 memcpy(&at25->chip, spi->dev.platform_data, sizeof(at25->chip));
400 } else if (!is_fram) {
401 err = at25_fw_to_chip(&spi->dev, &at25->chip);
406 /* Ping the chip ... the status register is pretty portable,
407 * unlike probing manufacturer IDs. We do expect that system
408 * firmware didn't write it in the past few milliseconds!
410 sr = spi_w8r8(spi, AT25_RDSR);
411 if (sr < 0 || sr & AT25_SR_nRDY) {
412 dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr);
416 mutex_init(&at25->lock);
418 spi_set_drvdata(spi, at25);
422 fm25_aux_read(at25, id, FM25_RDID, FM25_ID_LEN);
425 "Error: no Cypress FRAM (id %02x)\n", id[6]);
428 /* set size found in ID */
429 if (id[7] < 0x21 || id[7] > 0x26) {
430 dev_err(&spi->dev, "Error: unsupported size (id %02x)\n", id[7]);
433 at25->chip.byte_len = int_pow(2, id[7] - 0x21 + 4) * 1024;
435 if (at25->chip.byte_len > 64 * 1024)
436 at25->chip.flags |= EE_ADDR3;
438 at25->chip.flags |= EE_ADDR2;
441 fm25_aux_read(at25, sernum, FM25_RDSN, FM25_SN_LEN);
442 /* swap byte order */
443 for (i = 0; i < FM25_SN_LEN; i++)
444 at25->sernum[i] = sernum[FM25_SN_LEN - 1 - i];
447 at25->chip.page_size = PAGE_SIZE;
448 strncpy(at25->chip.name, "fm25", sizeof(at25->chip.name));
451 /* For now we only support 8/16/24 bit addressing */
452 if (at25->chip.flags & EE_ADDR1)
454 else if (at25->chip.flags & EE_ADDR2)
456 else if (at25->chip.flags & EE_ADDR3)
459 dev_dbg(&spi->dev, "unsupported address type\n");
463 at25->nvmem_config.type = is_fram ? NVMEM_TYPE_FRAM : NVMEM_TYPE_EEPROM;
464 at25->nvmem_config.name = dev_name(&spi->dev);
465 at25->nvmem_config.dev = &spi->dev;
466 at25->nvmem_config.read_only = at25->chip.flags & EE_READONLY;
467 at25->nvmem_config.root_only = true;
468 at25->nvmem_config.owner = THIS_MODULE;
469 at25->nvmem_config.compat = true;
470 at25->nvmem_config.base_dev = &spi->dev;
471 at25->nvmem_config.reg_read = at25_ee_read;
472 at25->nvmem_config.reg_write = at25_ee_write;
473 at25->nvmem_config.priv = at25;
474 at25->nvmem_config.stride = 1;
475 at25->nvmem_config.word_size = 1;
476 at25->nvmem_config.size = at25->chip.byte_len;
478 at25->nvmem = devm_nvmem_register(&spi->dev, &at25->nvmem_config);
479 if (IS_ERR(at25->nvmem))
480 return PTR_ERR(at25->nvmem);
482 dev_info(&spi->dev, "%d %s %s %s%s, pagesize %u\n",
483 (at25->chip.byte_len < 1024) ?
484 at25->chip.byte_len : (at25->chip.byte_len / 1024),
485 (at25->chip.byte_len < 1024) ? "Byte" : "KByte",
486 at25->chip.name, is_fram ? "fram" : "eeprom",
487 (at25->chip.flags & EE_READONLY) ? " (readonly)" : "",
488 at25->chip.page_size);
492 /*-------------------------------------------------------------------------*/
494 static struct spi_driver at25_driver = {
497 .of_match_table = at25_of_match,
498 .dev_groups = sernum_groups,
501 .id_table = at25_spi_ids,
504 module_spi_driver(at25_driver);
506 MODULE_DESCRIPTION("Driver for most SPI EEPROMs");
507 MODULE_AUTHOR("David Brownell");
508 MODULE_LICENSE("GPL");
509 MODULE_ALIAS("spi:at25");