drivers/misc/cxl/native.c

   1 /*
   2  * Copyright 2014 IBM Corp.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9
  10 #include <linux/spinlock.h>
  11 #include <linux/sched.h>
  12 #include <linux/slab.h>
  13 #include <linux/sched.h>
  14 #include <linux/mutex.h>
  15 #include <linux/mm.h>
  16 #include <linux/uaccess.h>
  17 #include <linux/delay.h>
  18 #include <asm/synch.h>
  19 #include <misc/cxl-base.h>
  20
  21 #include "cxl.h"
  22 #include "trace.h"
  23
  24 static int afu_control(struct cxl_afu *afu, u64 command, u64 clear,
  25                        u64 result, u64 mask, bool enabled)
  26 {
  27         u64 AFU_Cntl;
  28         unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
  29         int rc = 0;
  30
  31         spin_lock(&afu->afu_cntl_lock);
  32         pr_devel("AFU command starting: %llx\n", command);
  33
  34         trace_cxl_afu_ctrl(afu, command);
  35
  36         AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
  37         cxl_p2n_write(afu, CXL_AFU_Cntl_An, (AFU_Cntl & ~clear) | command);
  38
  39         AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
  40         while ((AFU_Cntl & mask) != result) {
  41                 if (time_after_eq(jiffies, timeout)) {
  42                         dev_warn(&afu->dev, "WARNING: AFU control timed out!\n");
  43                         rc = -EBUSY;
  44                         goto out;
  45                 }
  46
  47                 if (!cxl_ops->link_ok(afu->adapter, afu)) {
  48                         afu->enabled = enabled;
  49                         rc = -EIO;
  50                         goto out;
  51                 }
  52
  53                 pr_devel_ratelimited("AFU control... (0x%016llx)\n",
  54                                      AFU_Cntl | command);
  55                 cpu_relax();
  56                 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
  57         };
  58
  59         if (AFU_Cntl & CXL_AFU_Cntl_An_RA) {
  60                 /*
  61                  * Workaround for a bug in the XSL used in the Mellanox CX4
  62                  * that fails to clear the RA bit after an AFU reset,
  63                  * preventing subsequent AFU resets from working.
  64                  */
  65                 cxl_p2n_write(afu, CXL_AFU_Cntl_An, AFU_Cntl & ~CXL_AFU_Cntl_An_RA);
  66         }
  67
  68         pr_devel("AFU command complete: %llx\n", command);
  69         afu->enabled = enabled;
  70 out:
  71         trace_cxl_afu_ctrl_done(afu, command, rc);
  72         spin_unlock(&afu->afu_cntl_lock);
  73
  74         return rc;
  75 }
  76
  77 static int afu_enable(struct cxl_afu *afu)
  78 {
  79         pr_devel("AFU enable request\n");
  80
  81         return afu_control(afu, CXL_AFU_Cntl_An_E, 0,
  82                            CXL_AFU_Cntl_An_ES_Enabled,
  83                            CXL_AFU_Cntl_An_ES_MASK, true);
  84 }
  85
  86 int cxl_afu_disable(struct cxl_afu *afu)
  87 {
  88         pr_devel("AFU disable request\n");
  89
  90         return afu_control(afu, 0, CXL_AFU_Cntl_An_E,
  91                            CXL_AFU_Cntl_An_ES_Disabled,
  92                            CXL_AFU_Cntl_An_ES_MASK, false);
  93 }
  94
  95 /* This will disable as well as reset */
  96 static int native_afu_reset(struct cxl_afu *afu)
  97 {
  98         pr_devel("AFU reset request\n");
  99
 100         return afu_control(afu, CXL_AFU_Cntl_An_RA, 0,
 101                            CXL_AFU_Cntl_An_RS_Complete | CXL_AFU_Cntl_An_ES_Disabled,
 102                            CXL_AFU_Cntl_An_RS_MASK | CXL_AFU_Cntl_An_ES_MASK,
 103                            false);
 104 }
 105
 106 static int native_afu_check_and_enable(struct cxl_afu *afu)
 107 {
 108         if (!cxl_ops->link_ok(afu->adapter, afu)) {
 109                 WARN(1, "Refusing to enable afu while link down!\n");
 110                 return -EIO;
 111         }
 112         if (afu->enabled)
 113                 return 0;
 114         return afu_enable(afu);
 115 }
 116
 117 int cxl_psl_purge(struct cxl_afu *afu)
 118 {
 119         u64 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
 120         u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
 121         u64 dsisr, dar;
 122         u64 start, end;
 123         unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
 124         int rc = 0;
 125
 126         trace_cxl_psl_ctrl(afu, CXL_PSL_SCNTL_An_Pc);
 127
 128         pr_devel("PSL purge request\n");
 129
 130         if (!cxl_ops->link_ok(afu->adapter, afu)) {
 131                 dev_warn(&afu->dev, "PSL Purge called with link down, ignoring\n");
 132                 rc = -EIO;
 133                 goto out;
 134         }
 135
 136         if ((AFU_Cntl & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
 137                 WARN(1, "psl_purge request while AFU not disabled!\n");
 138                 cxl_afu_disable(afu);
 139         }
 140
 141         cxl_p1n_write(afu, CXL_PSL_SCNTL_An,
 142                        PSL_CNTL | CXL_PSL_SCNTL_An_Pc);
 143         start = local_clock();
 144         PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
 145         while ((PSL_CNTL &  CXL_PSL_SCNTL_An_Ps_MASK)
 146                         == CXL_PSL_SCNTL_An_Ps_Pending) {
 147                 if (time_after_eq(jiffies, timeout)) {
 148                         dev_warn(&afu->dev, "WARNING: PSL Purge timed out!\n");
 149                         rc = -EBUSY;
 150                         goto out;
 151                 }
 152                 if (!cxl_ops->link_ok(afu->adapter, afu)) {
 153                         rc = -EIO;
 154                         goto out;
 155                 }
 156
 157                 dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
 158                 pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%016llx  PSL_DSISR: 0x%016llx\n", PSL_CNTL, dsisr);
 159                 if (dsisr & CXL_PSL_DSISR_TRANS) {
 160                         dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
 161                         dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%016llx, DAR: 0x%016llx\n", dsisr, dar);
 162                         cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
 163                 } else if (dsisr) {
 164                         dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%016llx\n", dsisr);
 165                         cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
 166                 } else {
 167                         cpu_relax();
 168                 }
 169                 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
 170         };
 171         end = local_clock();
 172         pr_devel("PSL purged in %lld ns\n", end - start);
 173
 174         cxl_p1n_write(afu, CXL_PSL_SCNTL_An,
 175                        PSL_CNTL & ~CXL_PSL_SCNTL_An_Pc);
 176 out:
 177         trace_cxl_psl_ctrl_done(afu, CXL_PSL_SCNTL_An_Pc, rc);
 178         return rc;
 179 }
 180
 181 static int spa_max_procs(int spa_size)
 182 {
 183         /*
 184          * From the CAIA:
 185          *    end_of_SPA_area = SPA_Base + ((n+4) * 128) + (( ((n*8) + 127) >> 7) * 128) + 255
 186          * Most of that junk is really just an overly-complicated way of saying
 187          * the last 256 bytes are __aligned(128), so it's really:
 188          *    end_of_SPA_area = end_of_PSL_queue_area + __aligned(128) 255
 189          * and
 190          *    end_of_PSL_queue_area = SPA_Base + ((n+4) * 128) + (n*8) - 1
 191          * so
 192          *    sizeof(SPA) = ((n+4) * 128) + (n*8) + __aligned(128) 256
 193          * Ignore the alignment (which is safe in this case as long as we are
 194          * careful with our rounding) and solve for n:
 195          */
 196         return ((spa_size / 8) - 96) / 17;
 197 }
 198
 199 int cxl_alloc_spa(struct cxl_afu *afu)
 200 {
 201         unsigned spa_size;
 202
 203         /* Work out how many pages to allocate */
 204         afu->native->spa_order = -1;
 205         do {
 206                 afu->native->spa_order++;
 207                 spa_size = (1 << afu->native->spa_order) * PAGE_SIZE;
 208
 209                 if (spa_size > 0x100000) {
 210                         dev_warn(&afu->dev, "num_of_processes too large for the SPA, limiting to %i (0x%x)\n",
 211                                         afu->native->spa_max_procs, afu->native->spa_size);
 212                         afu->num_procs = afu->native->spa_max_procs;
 213                         break;
 214                 }
 215
 216                 afu->native->spa_size = spa_size;
 217                 afu->native->spa_max_procs = spa_max_procs(afu->native->spa_size);
 218         } while (afu->native->spa_max_procs < afu->num_procs);
 219
 220         if (!(afu->native->spa = (struct cxl_process_element *)
 221               __get_free_pages(GFP_KERNEL | __GFP_ZERO, afu->native->spa_order))) {
 222                 pr_err("cxl_alloc_spa: Unable to allocate scheduled process area\n");
 223                 return -ENOMEM;
 224         }
 225         pr_devel("spa pages: %i afu->spa_max_procs: %i   afu->num_procs: %i\n",
 226                  1<<afu->native->spa_order, afu->native->spa_max_procs, afu->num_procs);
 227
 228         return 0;
 229 }
 230
 231 static void attach_spa(struct cxl_afu *afu)
 232 {
 233         u64 spap;
 234
 235         afu->native->sw_command_status = (__be64 *)((char *)afu->native->spa +
 236                                             ((afu->native->spa_max_procs + 3) * 128));
 237
 238         spap = virt_to_phys(afu->native->spa) & CXL_PSL_SPAP_Addr;
 239         spap |= ((afu->native->spa_size >> (12 - CXL_PSL_SPAP_Size_Shift)) - 1) & CXL_PSL_SPAP_Size;
 240         spap |= CXL_PSL_SPAP_V;
 241         pr_devel("cxl: SPA allocated at 0x%p. Max processes: %i, sw_command_status: 0x%p CXL_PSL_SPAP_An=0x%016llx\n",
 242                 afu->native->spa, afu->native->spa_max_procs,
 243                 afu->native->sw_command_status, spap);
 244         cxl_p1n_write(afu, CXL_PSL_SPAP_An, spap);
 245 }
 246
 247 static inline void detach_spa(struct cxl_afu *afu)
 248 {
 249         cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0);
 250 }
 251
 252 void cxl_release_spa(struct cxl_afu *afu)
 253 {
 254         if (afu->native->spa) {
 255                 free_pages((unsigned long) afu->native->spa,
 256                         afu->native->spa_order);
 257                 afu->native->spa = NULL;
 258         }
 259 }
 260
 261 int cxl_tlb_slb_invalidate(struct cxl *adapter)
 262 {
 263         unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
 264
 265         pr_devel("CXL adapter wide TLBIA & SLBIA\n");
 266
 267         cxl_p1_write(adapter, CXL_PSL_AFUSEL, CXL_PSL_AFUSEL_A);
 268
 269         cxl_p1_write(adapter, CXL_PSL_TLBIA, CXL_TLB_SLB_IQ_ALL);
 270         while (cxl_p1_read(adapter, CXL_PSL_TLBIA) & CXL_TLB_SLB_P) {
 271                 if (time_after_eq(jiffies, timeout)) {
 272                         dev_warn(&adapter->dev, "WARNING: CXL adapter wide TLBIA timed out!\n");
 273                         return -EBUSY;
 274                 }
 275                 if (!cxl_ops->link_ok(adapter, NULL))
 276                         return -EIO;
 277                 cpu_relax();
 278         }
 279
 280         cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_ALL);
 281         while (cxl_p1_read(adapter, CXL_PSL_SLBIA) & CXL_TLB_SLB_P) {
 282                 if (time_after_eq(jiffies, timeout)) {
 283                         dev_warn(&adapter->dev, "WARNING: CXL adapter wide SLBIA timed out!\n");
 284                         return -EBUSY;
 285                 }
 286                 if (!cxl_ops->link_ok(adapter, NULL))
 287                         return -EIO;
 288                 cpu_relax();
 289         }
 290         return 0;
 291 }
 292
 293 static int cxl_write_sstp(struct cxl_afu *afu, u64 sstp0, u64 sstp1)
 294 {
 295         int rc;
 296
 297         /* 1. Disable SSTP by writing 0 to SSTP1[V] */
 298         cxl_p2n_write(afu, CXL_SSTP1_An, 0);
 299
 300         /* 2. Invalidate all SLB entries */
 301         if ((rc = cxl_afu_slbia(afu)))
 302                 return rc;
 303
 304         /* 3. Set SSTP0_An */
 305         cxl_p2n_write(afu, CXL_SSTP0_An, sstp0);
 306
 307         /* 4. Set SSTP1_An */
 308         cxl_p2n_write(afu, CXL_SSTP1_An, sstp1);
 309
 310         return 0;
 311 }
 312
 313 /* Using per slice version may improve performance here. (ie. SLBIA_An) */
 314 static void slb_invalid(struct cxl_context *ctx)
 315 {
 316         struct cxl *adapter = ctx->afu->adapter;
 317         u64 slbia;
 318
 319         WARN_ON(!mutex_is_locked(&ctx->afu->native->spa_mutex));
 320
 321         cxl_p1_write(adapter, CXL_PSL_LBISEL,
 322                         ((u64)be32_to_cpu(ctx->elem->common.pid) << 32) |
 323                         be32_to_cpu(ctx->elem->lpid));
 324         cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_LPIDPID);
 325
 326         while (1) {
 327                 if (!cxl_ops->link_ok(adapter, NULL))
 328                         break;
 329                 slbia = cxl_p1_read(adapter, CXL_PSL_SLBIA);
 330                 if (!(slbia & CXL_TLB_SLB_P))
 331                         break;
 332                 cpu_relax();
 333         }
 334 }
 335
 336 static int do_process_element_cmd(struct cxl_context *ctx,
 337                                   u64 cmd, u64 pe_state)
 338 {
 339         u64 state;
 340         unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
 341         int rc = 0;
 342
 343         trace_cxl_llcmd(ctx, cmd);
 344
 345         WARN_ON(!ctx->afu->enabled);
 346
 347         ctx->elem->software_state = cpu_to_be32(pe_state);
 348         smp_wmb();
 349         *(ctx->afu->native->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe);
 350         smp_mb();
 351         cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe);
 352         while (1) {
 353                 if (time_after_eq(jiffies, timeout)) {
 354                         dev_warn(&ctx->afu->dev, "WARNING: Process Element Command timed out!\n");
 355                         rc = -EBUSY;
 356                         goto out;
 357                 }
 358                 if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) {
 359                         dev_warn(&ctx->afu->dev, "WARNING: Device link down, aborting Process Element Command!\n");
 360                         rc = -EIO;
 361                         goto out;
 362                 }
 363                 state = be64_to_cpup(ctx->afu->native->sw_command_status);
 364                 if (state == ~0ULL) {
 365                         pr_err("cxl: Error adding process element to AFU\n");
 366                         rc = -1;
 367                         goto out;
 368                 }
 369                 if ((state & (CXL_SPA_SW_CMD_MASK | CXL_SPA_SW_STATE_MASK  | CXL_SPA_SW_LINK_MASK)) ==
 370                     (cmd | (cmd >> 16) | ctx->pe))
 371                         break;
 372                 /*
 373                  * The command won't finish in the PSL if there are
 374                  * outstanding DSIs.  Hence we need to yield here in
 375                  * case there are outstanding DSIs that we need to
 376                  * service.  Tuning possiblity: we could wait for a
 377                  * while before sched
 378                  */
 379                 schedule();
 380
 381         }
 382 out:
 383         trace_cxl_llcmd_done(ctx, cmd, rc);
 384         return rc;
 385 }
 386
 387 static int add_process_element(struct cxl_context *ctx)
 388 {
 389         int rc = 0;
 390
 391         mutex_lock(&ctx->afu->native->spa_mutex);
 392         pr_devel("%s Adding pe: %i started\n", __func__, ctx->pe);
 393         if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_ADD, CXL_PE_SOFTWARE_STATE_V)))
 394                 ctx->pe_inserted = true;
 395         pr_devel("%s Adding pe: %i finished\n", __func__, ctx->pe);
 396         mutex_unlock(&ctx->afu->native->spa_mutex);
 397         return rc;
 398 }
 399
 400 static int terminate_process_element(struct cxl_context *ctx)
 401 {
 402         int rc = 0;
 403
 404         /* fast path terminate if it's already invalid */
 405         if (!(ctx->elem->software_state & cpu_to_be32(CXL_PE_SOFTWARE_STATE_V)))
 406                 return rc;
 407
 408         mutex_lock(&ctx->afu->native->spa_mutex);
 409         pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe);
 410         /* We could be asked to terminate when the hw is down. That
 411          * should always succeed: it's not running if the hw has gone
 412          * away and is being reset.
 413          */
 414         if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu))
 415                 rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_TERMINATE,
 416                                             CXL_PE_SOFTWARE_STATE_V | CXL_PE_SOFTWARE_STATE_T);
 417         ctx->elem->software_state = 0;  /* Remove Valid bit */
 418         pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe);
 419         mutex_unlock(&ctx->afu->native->spa_mutex);
 420         return rc;
 421 }
 422
 423 static int remove_process_element(struct cxl_context *ctx)
 424 {
 425         int rc = 0;
 426
 427         mutex_lock(&ctx->afu->native->spa_mutex);
 428         pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe);
 429
 430         /* We could be asked to remove when the hw is down. Again, if
 431          * the hw is down, the PE is gone, so we succeed.
 432          */
 433         if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu))
 434                 rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_REMOVE, 0);
 435
 436         if (!rc)
 437                 ctx->pe_inserted = false;
 438         slb_invalid(ctx);
 439         pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe);
 440         mutex_unlock(&ctx->afu->native->spa_mutex);
 441
 442         return rc;
 443 }
 444
 445 void cxl_assign_psn_space(struct cxl_context *ctx)
 446 {
 447         if (!ctx->afu->pp_size || ctx->master) {
 448                 ctx->psn_phys = ctx->afu->psn_phys;
 449                 ctx->psn_size = ctx->afu->adapter->ps_size;
 450         } else {
 451                 ctx->psn_phys = ctx->afu->psn_phys +
 452                         (ctx->afu->native->pp_offset + ctx->afu->pp_size * ctx->pe);
 453                 ctx->psn_size = ctx->afu->pp_size;
 454         }
 455 }
 456
 457 static int activate_afu_directed(struct cxl_afu *afu)
 458 {
 459         int rc;
 460
 461         dev_info(&afu->dev, "Activating AFU directed mode\n");
 462
 463         afu->num_procs = afu->max_procs_virtualised;
 464         if (afu->native->spa == NULL) {
 465                 if (cxl_alloc_spa(afu))
 466                         return -ENOMEM;
 467         }
 468         attach_spa(afu);
 469
 470         cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_AFU);
 471         cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL);
 472         cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L);
 473
 474         afu->current_mode = CXL_MODE_DIRECTED;
 475
 476         if ((rc = cxl_chardev_m_afu_add(afu)))
 477                 return rc;
 478
 479         if ((rc = cxl_sysfs_afu_m_add(afu)))
 480                 goto err;
 481
 482         if ((rc = cxl_chardev_s_afu_add(afu)))
 483                 goto err1;
 484
 485         return 0;
 486 err1:
 487         cxl_sysfs_afu_m_remove(afu);
 488 err:
 489         cxl_chardev_afu_remove(afu);
 490         return rc;
 491 }
 492
 493 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 494 #define set_endian(sr) ((sr) |= CXL_PSL_SR_An_LE)
 495 #else
 496 #define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE))
 497 #endif
 498
 499 static u64 calculate_sr(struct cxl_context *ctx)
 500 {
 501         u64 sr = 0;
 502
 503         set_endian(sr);
 504         if (ctx->master)
 505                 sr |= CXL_PSL_SR_An_MP;
 506         if (mfspr(SPRN_LPCR) & LPCR_TC)
 507                 sr |= CXL_PSL_SR_An_TC;
 508         if (ctx->kernel) {
 509                 if (!ctx->real_mode)
 510                         sr |= CXL_PSL_SR_An_R;
 511                 sr |= (mfmsr() & MSR_SF) | CXL_PSL_SR_An_HV;
 512         } else {
 513                 sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R;
 514                 sr &= ~(CXL_PSL_SR_An_HV);
 515                 if (!test_tsk_thread_flag(current, TIF_32BIT))
 516                         sr |= CXL_PSL_SR_An_SF;
 517         }
 518         return sr;
 519 }
 520
 521 static void update_ivtes_directed(struct cxl_context *ctx)
 522 {
 523         bool need_update = (ctx->status == STARTED);
 524         int r;
 525
 526         if (need_update) {
 527                 WARN_ON(terminate_process_element(ctx));
 528                 WARN_ON(remove_process_element(ctx));
 529         }
 530
 531         for (r = 0; r < CXL_IRQ_RANGES; r++) {
 532                 ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]);
 533                 ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]);
 534         }
 535
 536         /*
 537          * Theoretically we could use the update llcmd, instead of a
 538          * terminate/remove/add (or if an atomic update was required we could
 539          * do a suspend/update/resume), however it seems there might be issues
 540          * with the update llcmd on some cards (including those using an XSL on
 541          * an ASIC) so for now it's safest to go with the commands that are
 542          * known to work. In the future if we come across a situation where the
 543          * card may be performing transactions using the same PE while we are
 544          * doing this update we might need to revisit this.
 545          */
 546         if (need_update)
 547                 WARN_ON(add_process_element(ctx));
 548 }
 549
 550 static int attach_afu_directed(struct cxl_context *ctx, u64 wed, u64 amr)
 551 {
 552         u32 pid;
 553         int result;
 554
 555         cxl_assign_psn_space(ctx);
 556
 557         ctx->elem->ctxtime = 0; /* disable */
 558         ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID));
 559         ctx->elem->haurp = 0; /* disable */
 560         ctx->elem->sdr = cpu_to_be64(mfspr(SPRN_SDR1));
 561
 562         pid = current->pid;
 563         if (ctx->kernel)
 564                 pid = 0;
 565         ctx->elem->common.tid = 0;
 566         ctx->elem->common.pid = cpu_to_be32(pid);
 567
 568         ctx->elem->sr = cpu_to_be64(calculate_sr(ctx));
 569
 570         ctx->elem->common.csrp = 0; /* disable */
 571         ctx->elem->common.aurp0 = 0; /* disable */
 572         ctx->elem->common.aurp1 = 0; /* disable */
 573
 574         cxl_prefault(ctx, wed);
 575
 576         ctx->elem->common.sstp0 = cpu_to_be64(ctx->sstp0);
 577         ctx->elem->common.sstp1 = cpu_to_be64(ctx->sstp1);
 578
 579         /*
 580          * Ensure we have the multiplexed PSL interrupt set up to take faults
 581          * for kernel contexts that may not have allocated any AFU IRQs at all:
 582          */
 583         if (ctx->irqs.range[0] == 0) {
 584                 ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq;
 585                 ctx->irqs.range[0] = 1;
 586         }
 587
 588         update_ivtes_directed(ctx);
 589
 590         ctx->elem->common.amr = cpu_to_be64(amr);
 591         ctx->elem->common.wed = cpu_to_be64(wed);
 592
 593         /* first guy needs to enable */
 594         if ((result = cxl_ops->afu_check_and_enable(ctx->afu)))
 595                 return result;
 596
 597         return add_process_element(ctx);
 598 }
 599
 600 static int deactivate_afu_directed(struct cxl_afu *afu)
 601 {
 602         dev_info(&afu->dev, "Deactivating AFU directed mode\n");
 603
 604         afu->current_mode = 0;
 605         afu->num_procs = 0;
 606
 607         cxl_sysfs_afu_m_remove(afu);
 608         cxl_chardev_afu_remove(afu);
 609
 610         /*
 611          * The CAIA section 2.2.1 indicates that the procedure for starting and
 612          * stopping an AFU in AFU directed mode is AFU specific, which is not
 613          * ideal since this code is generic and with one exception has no
 614          * knowledge of the AFU. This is in contrast to the procedure for
 615          * disabling a dedicated process AFU, which is documented to just
 616          * require a reset. The architecture does indicate that both an AFU
 617          * reset and an AFU disable should result in the AFU being disabled and
 618          * we do both followed by a PSL purge for safety.
 619          *
 620          * Notably we used to have some issues with the disable sequence on PSL
 621          * cards, which is why we ended up using this heavy weight procedure in
 622          * the first place, however a bug was discovered that had rendered the
 623          * disable operation ineffective, so it is conceivable that was the
 624          * sole explanation for those difficulties. Careful regression testing
 625          * is recommended if anyone attempts to remove or reorder these
 626          * operations.
 627          *
 628          * The XSL on the Mellanox CX4 behaves a little differently from the
 629          * PSL based cards and will time out an AFU reset if the AFU is still
 630          * enabled. That card is special in that we do have a means to identify
 631          * it from this code, so in that case we skip the reset and just use a
 632          * disable/purge to avoid the timeout and corresponding noise in the
 633          * kernel log.
 634          */
 635         if (afu->adapter->native->sl_ops->needs_reset_before_disable)
 636                 cxl_ops->afu_reset(afu);
 637         cxl_afu_disable(afu);
 638         cxl_psl_purge(afu);
 639
 640         return 0;
 641 }
 642
 643 static int activate_dedicated_process(struct cxl_afu *afu)
 644 {
 645         dev_info(&afu->dev, "Activating dedicated process mode\n");
 646
 647         cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process);
 648
 649         cxl_p1n_write(afu, CXL_PSL_CtxTime_An, 0); /* disable */
 650         cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0);    /* disable */
 651         cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL);
 652         cxl_p1n_write(afu, CXL_PSL_LPID_An, mfspr(SPRN_LPID));
 653         cxl_p1n_write(afu, CXL_HAURP_An, 0);       /* disable */
 654         cxl_p1n_write(afu, CXL_PSL_SDR_An, mfspr(SPRN_SDR1));
 655
 656         cxl_p2n_write(afu, CXL_CSRP_An, 0);        /* disable */
 657         cxl_p2n_write(afu, CXL_AURP0_An, 0);       /* disable */
 658         cxl_p2n_write(afu, CXL_AURP1_An, 0);       /* disable */
 659
 660         afu->current_mode = CXL_MODE_DEDICATED;
 661         afu->num_procs = 1;
 662
 663         return cxl_chardev_d_afu_add(afu);
 664 }
 665
 666 static void update_ivtes_dedicated(struct cxl_context *ctx)
 667 {
 668         struct cxl_afu *afu = ctx->afu;
 669
 670         cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An,
 671                        (((u64)ctx->irqs.offset[0] & 0xffff) << 48) |
 672                        (((u64)ctx->irqs.offset[1] & 0xffff) << 32) |
 673                        (((u64)ctx->irqs.offset[2] & 0xffff) << 16) |
 674                         ((u64)ctx->irqs.offset[3] & 0xffff));
 675         cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, (u64)
 676                        (((u64)ctx->irqs.range[0] & 0xffff) << 48) |
 677                        (((u64)ctx->irqs.range[1] & 0xffff) << 32) |
 678                        (((u64)ctx->irqs.range[2] & 0xffff) << 16) |
 679                         ((u64)ctx->irqs.range[3] & 0xffff));
 680 }
 681
 682 static int attach_dedicated(struct cxl_context *ctx, u64 wed, u64 amr)
 683 {
 684         struct cxl_afu *afu = ctx->afu;
 685         u64 pid;
 686         int rc;
 687
 688         pid = (u64)current->pid << 32;
 689         if (ctx->kernel)
 690                 pid = 0;
 691         cxl_p2n_write(afu, CXL_PSL_PID_TID_An, pid);
 692
 693         cxl_p1n_write(afu, CXL_PSL_SR_An, calculate_sr(ctx));
 694
 695         if ((rc = cxl_write_sstp(afu, ctx->sstp0, ctx->sstp1)))
 696                 return rc;
 697
 698         cxl_prefault(ctx, wed);
 699
 700         update_ivtes_dedicated(ctx);
 701
 702         cxl_p2n_write(afu, CXL_PSL_AMR_An, amr);
 703
 704         /* master only context for dedicated */
 705         cxl_assign_psn_space(ctx);
 706
 707         if ((rc = cxl_ops->afu_reset(afu)))
 708                 return rc;
 709
 710         cxl_p2n_write(afu, CXL_PSL_WED_An, wed);
 711
 712         return afu_enable(afu);
 713 }
 714
 715 static int deactivate_dedicated_process(struct cxl_afu *afu)
 716 {
 717         dev_info(&afu->dev, "Deactivating dedicated process mode\n");
 718
 719         afu->current_mode = 0;
 720         afu->num_procs = 0;
 721
 722         cxl_chardev_afu_remove(afu);
 723
 724         return 0;
 725 }
 726
 727 static int native_afu_deactivate_mode(struct cxl_afu *afu, int mode)
 728 {
 729         if (mode == CXL_MODE_DIRECTED)
 730                 return deactivate_afu_directed(afu);
 731         if (mode == CXL_MODE_DEDICATED)
 732                 return deactivate_dedicated_process(afu);
 733         return 0;
 734 }
 735
 736 static int native_afu_activate_mode(struct cxl_afu *afu, int mode)
 737 {
 738         if (!mode)
 739                 return 0;
 740         if (!(mode & afu->modes_supported))
 741                 return -EINVAL;
 742
 743         if (!cxl_ops->link_ok(afu->adapter, afu)) {
 744                 WARN(1, "Device link is down, refusing to activate!\n");
 745                 return -EIO;
 746         }
 747
 748         if (mode == CXL_MODE_DIRECTED)
 749                 return activate_afu_directed(afu);
 750         if (mode == CXL_MODE_DEDICATED)
 751                 return activate_dedicated_process(afu);
 752
 753         return -EINVAL;
 754 }
 755
 756 static int native_attach_process(struct cxl_context *ctx, bool kernel,
 757                                 u64 wed, u64 amr)
 758 {
 759         if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) {
 760                 WARN(1, "Device link is down, refusing to attach process!\n");
 761                 return -EIO;
 762         }
 763
 764         ctx->kernel = kernel;
 765         if (ctx->afu->current_mode == CXL_MODE_DIRECTED)
 766                 return attach_afu_directed(ctx, wed, amr);
 767
 768         if (ctx->afu->current_mode == CXL_MODE_DEDICATED)
 769                 return attach_dedicated(ctx, wed, amr);
 770
 771         return -EINVAL;
 772 }
 773
 774 static inline int detach_process_native_dedicated(struct cxl_context *ctx)
 775 {
 776         /*
 777          * The CAIA section 2.1.1 indicates that we need to do an AFU reset to
 778          * stop the AFU in dedicated mode (we therefore do not make that
 779          * optional like we do in the afu directed path). It does not indicate
 780          * that we need to do an explicit disable (which should occur
 781          * implicitly as part of the reset) or purge, but we do these as well
 782          * to be on the safe side.
 783          *
 784          * Notably we used to have some issues with the disable sequence
 785          * (before the sequence was spelled out in the architecture) which is
 786          * why we were so heavy weight in the first place, however a bug was
 787          * discovered that had rendered the disable operation ineffective, so
 788          * it is conceivable that was the sole explanation for those
 789          * difficulties. Point is, we should be careful and do some regression
 790          * testing if we ever attempt to remove any part of this procedure.
 791          */
 792         cxl_ops->afu_reset(ctx->afu);
 793         cxl_afu_disable(ctx->afu);
 794         cxl_psl_purge(ctx->afu);
 795         return 0;
 796 }
 797
 798 static void native_update_ivtes(struct cxl_context *ctx)
 799 {
 800         if (ctx->afu->current_mode == CXL_MODE_DIRECTED)
 801                 return update_ivtes_directed(ctx);
 802         if (ctx->afu->current_mode == CXL_MODE_DEDICATED)
 803                 return update_ivtes_dedicated(ctx);
 804         WARN(1, "native_update_ivtes: Bad mode\n");
 805 }
 806
 807 static inline int detach_process_native_afu_directed(struct cxl_context *ctx)
 808 {
 809         if (!ctx->pe_inserted)
 810                 return 0;
 811         if (terminate_process_element(ctx))
 812                 return -1;
 813         if (remove_process_element(ctx))
 814                 return -1;
 815
 816         return 0;
 817 }
 818
 819 static int native_detach_process(struct cxl_context *ctx)
 820 {
 821         trace_cxl_detach(ctx);
 822
 823         if (ctx->afu->current_mode == CXL_MODE_DEDICATED)
 824                 return detach_process_native_dedicated(ctx);
 825
 826         return detach_process_native_afu_directed(ctx);
 827 }
 828
 829 static int native_get_irq_info(struct cxl_afu *afu, struct cxl_irq_info *info)
 830 {
 831         u64 pidtid;
 832
 833         /* If the adapter has gone away, we can't get any meaningful
 834          * information.
 835          */
 836         if (!cxl_ops->link_ok(afu->adapter, afu))
 837                 return -EIO;
 838
 839         info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
 840         info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
 841         info->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An);
 842         pidtid = cxl_p2n_read(afu, CXL_PSL_PID_TID_An);
 843         info->pid = pidtid >> 32;
 844         info->tid = pidtid & 0xffffffff;
 845         info->afu_err = cxl_p2n_read(afu, CXL_AFU_ERR_An);
 846         info->errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
 847         info->proc_handle = 0;
 848
 849         return 0;
 850 }
 851
 852 void cxl_native_psl_irq_dump_regs(struct cxl_context *ctx)
 853 {
 854         u64 fir1, fir2, fir_slice, serr, afu_debug;
 855
 856         fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR1);
 857         fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR2);
 858         fir_slice = cxl_p1n_read(ctx->afu, CXL_PSL_FIR_SLICE_An);
 859         afu_debug = cxl_p1n_read(ctx->afu, CXL_AFU_DEBUG_An);
 860
 861         dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1);
 862         dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2);
 863         if (ctx->afu->adapter->native->sl_ops->register_serr_irq) {
 864                 serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An);
 865                 cxl_afu_decode_psl_serr(ctx->afu, serr);
 866         }
 867         dev_crit(&ctx->afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice);
 868         dev_crit(&ctx->afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug);
 869 }
 870
 871 static irqreturn_t native_handle_psl_slice_error(struct cxl_context *ctx,
 872                                                 u64 dsisr, u64 errstat)
 873 {
 874
 875         dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%016llx\n", errstat);
 876
 877         if (ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers)
 878                 ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers(ctx);
 879
 880         if (ctx->afu->adapter->native->sl_ops->debugfs_stop_trace) {
 881                 dev_crit(&ctx->afu->dev, "STOPPING CXL TRACE\n");
 882                 ctx->afu->adapter->native->sl_ops->debugfs_stop_trace(ctx->afu->adapter);
 883         }
 884
 885         return cxl_ops->ack_irq(ctx, 0, errstat);
 886 }
 887
 888 static irqreturn_t fail_psl_irq(struct cxl_afu *afu, struct cxl_irq_info *irq_info)
 889 {
 890         if (irq_info->dsisr & CXL_PSL_DSISR_TRANS)
 891                 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
 892         else
 893                 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
 894
 895         return IRQ_HANDLED;
 896 }
 897
 898 static irqreturn_t native_irq_multiplexed(int irq, void *data)
 899 {
 900         struct cxl_afu *afu = data;
 901         struct cxl_context *ctx;
 902         struct cxl_irq_info irq_info;
 903         int ph = cxl_p2n_read(afu, CXL_PSL_PEHandle_An) & 0xffff;
 904         int ret;
 905
 906         if ((ret = native_get_irq_info(afu, &irq_info))) {
 907                 WARN(1, "Unable to get CXL IRQ Info: %i\n", ret);
 908                 return fail_psl_irq(afu, &irq_info);
 909         }
 910
 911         rcu_read_lock();
 912         ctx = idr_find(&afu->contexts_idr, ph);
 913         if (ctx) {
 914                 ret = cxl_irq(irq, ctx, &irq_info);
 915                 rcu_read_unlock();
 916                 return ret;
 917         }
 918         rcu_read_unlock();
 919
 920         WARN(1, "Unable to demultiplex CXL PSL IRQ for PE %i DSISR %016llx DAR"
 921                 " %016llx\n(Possible AFU HW issue - was a term/remove acked"
 922                 " with outstanding transactions?)\n", ph, irq_info.dsisr,
 923                 irq_info.dar);
 924         return fail_psl_irq(afu, &irq_info);
 925 }
 926
 927 static void native_irq_wait(struct cxl_context *ctx)
 928 {
 929         u64 dsisr;
 930         int timeout = 1000;
 931         int ph;
 932
 933         /*
 934          * Wait until no further interrupts are presented by the PSL
 935          * for this context.
 936          */
 937         while (timeout--) {
 938                 ph = cxl_p2n_read(ctx->afu, CXL_PSL_PEHandle_An) & 0xffff;
 939                 if (ph != ctx->pe)
 940                         return;
 941                 dsisr = cxl_p2n_read(ctx->afu, CXL_PSL_DSISR_An);
 942                 if ((dsisr & CXL_PSL_DSISR_PENDING) == 0)
 943                         return;
 944                 /*
 945                  * We are waiting for the workqueue to process our
 946                  * irq, so need to let that run here.
 947                  */
 948                 msleep(1);
 949         }
 950
 951         dev_warn(&ctx->afu->dev, "WARNING: waiting on DSI for PE %i"
 952                  " DSISR %016llx!\n", ph, dsisr);
 953         return;
 954 }
 955
 956 static irqreturn_t native_slice_irq_err(int irq, void *data)
 957 {
 958         struct cxl_afu *afu = data;
 959         u64 fir_slice, errstat, serr, afu_debug, afu_error, dsisr;
 960
 961         /*
 962          * slice err interrupt is only used with full PSL (no XSL)
 963          */
 964         serr = cxl_p1n_read(afu, CXL_PSL_SERR_An);
 965         fir_slice = cxl_p1n_read(afu, CXL_PSL_FIR_SLICE_An);
 966         errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
 967         afu_debug = cxl_p1n_read(afu, CXL_AFU_DEBUG_An);
 968         afu_error = cxl_p2n_read(afu, CXL_AFU_ERR_An);
 969         dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
 970         cxl_afu_decode_psl_serr(afu, serr);
 971         dev_crit(&afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice);
 972         dev_crit(&afu->dev, "CXL_PSL_ErrStat_An: 0x%016llx\n", errstat);
 973         dev_crit(&afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug);
 974         dev_crit(&afu->dev, "AFU_ERR_An: 0x%.16llx\n", afu_error);
 975         dev_crit(&afu->dev, "PSL_DSISR_An: 0x%.16llx\n", dsisr);
 976
 977         cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
 978
 979         return IRQ_HANDLED;
 980 }
 981
 982 void cxl_native_err_irq_dump_regs(struct cxl *adapter)
 983 {
 984         u64 fir1, fir2;
 985
 986         fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1);
 987         fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2);
 988
 989         dev_crit(&adapter->dev, "PSL_FIR1: 0x%016llx\nPSL_FIR2: 0x%016llx\n", fir1, fir2);
 990 }
 991
 992 static irqreturn_t native_irq_err(int irq, void *data)
 993 {
 994         struct cxl *adapter = data;
 995         u64 err_ivte;
 996
 997         WARN(1, "CXL ERROR interrupt %i\n", irq);
 998
 999         err_ivte = cxl_p1_read(adapter, CXL_PSL_ErrIVTE);
1000         dev_crit(&adapter->dev, "PSL_ErrIVTE: 0x%016llx\n", err_ivte);
1001
1002         if (adapter->native->sl_ops->debugfs_stop_trace) {
1003                 dev_crit(&adapter->dev, "STOPPING CXL TRACE\n");
1004                 adapter->native->sl_ops->debugfs_stop_trace(adapter);
1005         }
1006
1007         if (adapter->native->sl_ops->err_irq_dump_registers)
1008                 adapter->native->sl_ops->err_irq_dump_registers(adapter);
1009
1010         return IRQ_HANDLED;
1011 }
1012
1013 int cxl_native_register_psl_err_irq(struct cxl *adapter)
1014 {
1015         int rc;
1016
1017         adapter->irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err",
1018                                       dev_name(&adapter->dev));
1019         if (!adapter->irq_name)
1020                 return -ENOMEM;
1021
1022         if ((rc = cxl_register_one_irq(adapter, native_irq_err, adapter,
1023                                        &adapter->native->err_hwirq,
1024                                        &adapter->native->err_virq,
1025                                        adapter->irq_name))) {
1026                 kfree(adapter->irq_name);
1027                 adapter->irq_name = NULL;
1028                 return rc;
1029         }
1030
1031         cxl_p1_write(adapter, CXL_PSL_ErrIVTE, adapter->native->err_hwirq & 0xffff);
1032
1033         return 0;
1034 }
1035
1036 void cxl_native_release_psl_err_irq(struct cxl *adapter)
1037 {
1038         if (adapter->native->err_virq != irq_find_mapping(NULL, adapter->native->err_hwirq))
1039                 return;
1040
1041         cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000);
1042         cxl_unmap_irq(adapter->native->err_virq, adapter);
1043         cxl_ops->release_one_irq(adapter, adapter->native->err_hwirq);
1044         kfree(adapter->irq_name);
1045 }
1046
1047 int cxl_native_register_serr_irq(struct cxl_afu *afu)
1048 {
1049         u64 serr;
1050         int rc;
1051
1052         afu->err_irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err",
1053                                       dev_name(&afu->dev));
1054         if (!afu->err_irq_name)
1055                 return -ENOMEM;
1056
1057         if ((rc = cxl_register_one_irq(afu->adapter, native_slice_irq_err, afu,
1058                                        &afu->serr_hwirq,
1059                                        &afu->serr_virq, afu->err_irq_name))) {
1060                 kfree(afu->err_irq_name);
1061                 afu->err_irq_name = NULL;
1062                 return rc;
1063         }
1064
1065         serr = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1066         serr = (serr & 0x00ffffffffff0000ULL) | (afu->serr_hwirq & 0xffff);
1067         cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
1068
1069         return 0;
1070 }
1071
1072 void cxl_native_release_serr_irq(struct cxl_afu *afu)
1073 {
1074         if (afu->serr_virq != irq_find_mapping(NULL, afu->serr_hwirq))
1075                 return;
1076
1077         cxl_p1n_write(afu, CXL_PSL_SERR_An, 0x0000000000000000);
1078         cxl_unmap_irq(afu->serr_virq, afu);
1079         cxl_ops->release_one_irq(afu->adapter, afu->serr_hwirq);
1080         kfree(afu->err_irq_name);
1081 }
1082
1083 int cxl_native_register_psl_irq(struct cxl_afu *afu)
1084 {
1085         int rc;
1086
1087         afu->psl_irq_name = kasprintf(GFP_KERNEL, "cxl-%s",
1088                                       dev_name(&afu->dev));
1089         if (!afu->psl_irq_name)
1090                 return -ENOMEM;
1091
1092         if ((rc = cxl_register_one_irq(afu->adapter, native_irq_multiplexed,
1093                                     afu, &afu->native->psl_hwirq, &afu->native->psl_virq,
1094                                     afu->psl_irq_name))) {
1095                 kfree(afu->psl_irq_name);
1096                 afu->psl_irq_name = NULL;
1097         }
1098         return rc;
1099 }
1100
1101 void cxl_native_release_psl_irq(struct cxl_afu *afu)
1102 {
1103         if (afu->native->psl_virq != irq_find_mapping(NULL, afu->native->psl_hwirq))
1104                 return;
1105
1106         cxl_unmap_irq(afu->native->psl_virq, afu);
1107         cxl_ops->release_one_irq(afu->adapter, afu->native->psl_hwirq);
1108         kfree(afu->psl_irq_name);
1109 }
1110
1111 static void recover_psl_err(struct cxl_afu *afu, u64 errstat)
1112 {
1113         u64 dsisr;
1114
1115         pr_devel("RECOVERING FROM PSL ERROR... (0x%016llx)\n", errstat);
1116
1117         /* Clear PSL_DSISR[PE] */
1118         dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1119         cxl_p2n_write(afu, CXL_PSL_DSISR_An, dsisr & ~CXL_PSL_DSISR_An_PE);
1120
1121         /* Write 1s to clear error status bits */
1122         cxl_p2n_write(afu, CXL_PSL_ErrStat_An, errstat);
1123 }
1124
1125 static int native_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask)
1126 {
1127         trace_cxl_psl_irq_ack(ctx, tfc);
1128         if (tfc)
1129                 cxl_p2n_write(ctx->afu, CXL_PSL_TFC_An, tfc);
1130         if (psl_reset_mask)
1131                 recover_psl_err(ctx->afu, psl_reset_mask);
1132
1133         return 0;
1134 }
1135
1136 int cxl_check_error(struct cxl_afu *afu)
1137 {
1138         return (cxl_p1n_read(afu, CXL_PSL_SCNTL_An) == ~0ULL);
1139 }
1140
1141 static bool native_support_attributes(const char *attr_name,
1142                                       enum cxl_attrs type)
1143 {
1144         return true;
1145 }
1146
1147 static int native_afu_cr_read64(struct cxl_afu *afu, int cr, u64 off, u64 *out)
1148 {
1149         if (unlikely(!cxl_ops->link_ok(afu->adapter, afu)))
1150                 return -EIO;
1151         if (unlikely(off >= afu->crs_len))
1152                 return -ERANGE;
1153         *out = in_le64(afu->native->afu_desc_mmio + afu->crs_offset +
1154                 (cr * afu->crs_len) + off);
1155         return 0;
1156 }
1157
1158 static int native_afu_cr_read32(struct cxl_afu *afu, int cr, u64 off, u32 *out)
1159 {
1160         if (unlikely(!cxl_ops->link_ok(afu->adapter, afu)))
1161                 return -EIO;
1162         if (unlikely(off >= afu->crs_len))
1163                 return -ERANGE;
1164         *out = in_le32(afu->native->afu_desc_mmio + afu->crs_offset +
1165                 (cr * afu->crs_len) + off);
1166         return 0;
1167 }
1168
1169 static int native_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off, u16 *out)
1170 {
1171         u64 aligned_off = off & ~0x3L;
1172         u32 val;
1173         int rc;
1174
1175         rc = native_afu_cr_read32(afu, cr, aligned_off, &val);
1176         if (!rc)
1177                 *out = (val >> ((off & 0x3) * 8)) & 0xffff;
1178         return rc;
1179 }
1180
1181 static int native_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off, u8 *out)
1182 {
1183         u64 aligned_off = off & ~0x3L;
1184         u32 val;
1185         int rc;
1186
1187         rc = native_afu_cr_read32(afu, cr, aligned_off, &val);
1188         if (!rc)
1189                 *out = (val >> ((off & 0x3) * 8)) & 0xff;
1190         return rc;
1191 }
1192
1193 static int native_afu_cr_write32(struct cxl_afu *afu, int cr, u64 off, u32 in)
1194 {
1195         if (unlikely(!cxl_ops->link_ok(afu->adapter, afu)))
1196                 return -EIO;
1197         if (unlikely(off >= afu->crs_len))
1198                 return -ERANGE;
1199         out_le32(afu->native->afu_desc_mmio + afu->crs_offset +
1200                 (cr * afu->crs_len) + off, in);
1201         return 0;
1202 }
1203
1204 static int native_afu_cr_write16(struct cxl_afu *afu, int cr, u64 off, u16 in)
1205 {
1206         u64 aligned_off = off & ~0x3L;
1207         u32 val32, mask, shift;
1208         int rc;
1209
1210         rc = native_afu_cr_read32(afu, cr, aligned_off, &val32);
1211         if (rc)
1212                 return rc;
1213         shift = (off & 0x3) * 8;
1214         WARN_ON(shift == 24);
1215         mask = 0xffff << shift;
1216         val32 = (val32 & ~mask) | (in << shift);
1217
1218         rc = native_afu_cr_write32(afu, cr, aligned_off, val32);
1219         return rc;
1220 }
1221
1222 static int native_afu_cr_write8(struct cxl_afu *afu, int cr, u64 off, u8 in)
1223 {
1224         u64 aligned_off = off & ~0x3L;
1225         u32 val32, mask, shift;
1226         int rc;
1227
1228         rc = native_afu_cr_read32(afu, cr, aligned_off, &val32);
1229         if (rc)
1230                 return rc;
1231         shift = (off & 0x3) * 8;
1232         mask = 0xff << shift;
1233         val32 = (val32 & ~mask) | (in << shift);
1234
1235         rc = native_afu_cr_write32(afu, cr, aligned_off, val32);
1236         return rc;
1237 }
1238
1239 const struct cxl_backend_ops cxl_native_ops = {
1240         .module = THIS_MODULE,
1241         .adapter_reset = cxl_pci_reset,
1242         .alloc_one_irq = cxl_pci_alloc_one_irq,
1243         .release_one_irq = cxl_pci_release_one_irq,
1244         .alloc_irq_ranges = cxl_pci_alloc_irq_ranges,
1245         .release_irq_ranges = cxl_pci_release_irq_ranges,
1246         .setup_irq = cxl_pci_setup_irq,
1247         .handle_psl_slice_error = native_handle_psl_slice_error,
1248         .psl_interrupt = NULL,
1249         .ack_irq = native_ack_irq,
1250         .irq_wait = native_irq_wait,
1251         .attach_process = native_attach_process,
1252         .detach_process = native_detach_process,
1253         .update_ivtes = native_update_ivtes,
1254         .support_attributes = native_support_attributes,
1255         .link_ok = cxl_adapter_link_ok,
1256         .release_afu = cxl_pci_release_afu,
1257         .afu_read_err_buffer = cxl_pci_afu_read_err_buffer,
1258         .afu_check_and_enable = native_afu_check_and_enable,
1259         .afu_activate_mode = native_afu_activate_mode,
1260         .afu_deactivate_mode = native_afu_deactivate_mode,
1261         .afu_reset = native_afu_reset,
1262         .afu_cr_read8 = native_afu_cr_read8,
1263         .afu_cr_read16 = native_afu_cr_read16,
1264         .afu_cr_read32 = native_afu_cr_read32,
1265         .afu_cr_read64 = native_afu_cr_read64,
1266         .afu_cr_write8 = native_afu_cr_write8,
1267         .afu_cr_write16 = native_afu_cr_write16,
1268         .afu_cr_write32 = native_afu_cr_write32,
1269         .read_adapter_vpd = cxl_pci_read_adapter_vpd,
1270 };