drivers/misc/cardreader/rts5249.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /* Driver for Realtek PCI-Express card reader
   3  *
   4  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   5  *
   6  * Author:
   7  *   Wei WANG <wei_wang@realsil.com.cn>
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/delay.h>
  12 #include <linux/rtsx_pci.h>
  13
  14 #include "rtsx_pcr.h"
  15
  16 static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
  17 {
  18         u8 val;
  19
  20         rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  21         return val & 0x0F;
  22 }
  23
  24 static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  25 {
  26         u8 driving_3v3[4][3] = {
  27                 {0x11, 0x11, 0x18},
  28                 {0x55, 0x55, 0x5C},
  29                 {0xFF, 0xFF, 0xFF},
  30                 {0x96, 0x96, 0x96},
  31         };
  32         u8 driving_1v8[4][3] = {
  33                 {0xC4, 0xC4, 0xC4},
  34                 {0x3C, 0x3C, 0x3C},
  35                 {0xFE, 0xFE, 0xFE},
  36                 {0xB3, 0xB3, 0xB3},
  37         };
  38         u8 (*driving)[3], drive_sel;
  39
  40         if (voltage == OUTPUT_3V3) {
  41                 driving = driving_3v3;
  42                 drive_sel = pcr->sd30_drive_sel_3v3;
  43         } else {
  44                 driving = driving_1v8;
  45                 drive_sel = pcr->sd30_drive_sel_1v8;
  46         }
  47
  48         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
  49                         0xFF, driving[drive_sel][0]);
  50         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
  51                         0xFF, driving[drive_sel][1]);
  52         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
  53                         0xFF, driving[drive_sel][2]);
  54 }
  55
  56 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
  57 {
  58         struct pci_dev *pdev = pcr->pci;
  59         u32 reg;
  60
  61         pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
  62         pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  63
  64         if (!rtsx_vendor_setting_valid(reg)) {
  65                 pcr_dbg(pcr, "skip fetch vendor setting\n");
  66                 return;
  67         }
  68
  69         pcr->aspm_en = rtsx_reg_to_aspm(reg);
  70         pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  71         pcr->card_drive_sel &= 0x3F;
  72         pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
  73
  74         pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
  75         pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  76
  77         if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A))
  78                 pcr->rtd3_en = rtsx_reg_to_rtd3_uhsii(reg);
  79
  80         if (rtsx_check_mmc_support(reg))
  81                 pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
  82         pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  83         if (rtsx_reg_check_reverse_socket(reg))
  84                 pcr->flags |= PCR_REVERSE_SOCKET;
  85 }
  86
  87 static void rts5249_init_from_cfg(struct rtsx_pcr *pcr)
  88 {
  89         struct pci_dev *pdev = pcr->pci;
  90         int l1ss;
  91         struct rtsx_cr_option *option = &(pcr->option);
  92         u32 lval;
  93
  94         l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
  95         if (!l1ss)
  96                 return;
  97
  98         pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
  99
 100         if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
 101                 if (0 == (lval & 0x0F))
 102                         rtsx_pci_enable_oobs_polling(pcr);
 103                 else
 104                         rtsx_pci_disable_oobs_polling(pcr);
 105         }
 106
 107
 108         if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
 109                 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
 110
 111         if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
 112                 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
 113
 114         if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
 115                 rtsx_set_dev_flag(pcr, PM_L1_1_EN);
 116
 117         if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
 118                 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
 119
 120         if (option->ltr_en) {
 121                 u16 val;
 122
 123                 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
 124                 if (val & PCI_EXP_DEVCTL2_LTR_EN) {
 125                         option->ltr_enabled = true;
 126                         option->ltr_active = true;
 127                         rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
 128                 } else {
 129                         option->ltr_enabled = false;
 130                 }
 131         }
 132 }
 133
 134 static int rts5249_init_from_hw(struct rtsx_pcr *pcr)
 135 {
 136         struct rtsx_cr_option *option = &(pcr->option);
 137
 138         if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
 139                                 | PM_L1_1_EN | PM_L1_2_EN))
 140                 option->force_clkreq_0 = false;
 141         else
 142                 option->force_clkreq_0 = true;
 143
 144         return 0;
 145 }
 146
 147 static void rts52xa_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
 148 {
 149         /* Set relink_time to 0 */
 150         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
 151         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
 152         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
 153                                 RELINK_TIME_MASK, 0);
 154
 155         rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
 156                         D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
 157
 158         if (!runtime) {
 159                 rtsx_pci_write_register(pcr, RTS524A_AUTOLOAD_CFG1,
 160                                 CD_RESUME_EN_MASK, 0);
 161                 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00);
 162                 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20);
 163         }
 164
 165         rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN);
 166 }
 167
 168 static void rts52xa_save_content_from_efuse(struct rtsx_pcr *pcr)
 169 {
 170         u8 cnt, sv;
 171         u16 j = 0;
 172         u8 tmp;
 173         u8 val;
 174         int i;
 175
 176         rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
 177                                 REG_EFUSE_BYPASS | REG_EFUSE_POR, REG_EFUSE_POR);
 178         udelay(1);
 179
 180         pcr_dbg(pcr, "Enable efuse por!");
 181         pcr_dbg(pcr, "save efuse to autoload");
 182
 183         rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, REG_EFUSE_ADD_MASK, 0x00);
 184         rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
 185                                 REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
 186         /* Wait transfer end */
 187         for (j = 0; j < 1024; j++) {
 188                 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
 189                 if ((tmp & 0x80) == 0)
 190                         break;
 191         }
 192         rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
 193         cnt = val & 0x0F;
 194         sv = val & 0x10;
 195
 196         if (sv) {
 197                 for (i = 0; i < 4; i++) {
 198                         rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
 199                                 REG_EFUSE_ADD_MASK, 0x04 + i);
 200                         rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
 201                                 REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
 202                         /* Wait transfer end */
 203                         for (j = 0; j < 1024; j++) {
 204                                 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
 205                                 if ((tmp & 0x80) == 0)
 206                                         break;
 207                         }
 208                         rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
 209                         rtsx_pci_write_register(pcr, 0xFF04 + i, 0xFF, val);
 210                 }
 211         } else {
 212                 rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr));
 213                 rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8));
 214                 rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr));
 215                 rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8));
 216         }
 217
 218         for (i = 0; i < cnt * 4; i++) {
 219                 if (sv)
 220                         rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
 221                                 REG_EFUSE_ADD_MASK, 0x08 + i);
 222                 else
 223                         rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
 224                                 REG_EFUSE_ADD_MASK, 0x04 + i);
 225                 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
 226                                 REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
 227                 /* Wait transfer end */
 228                 for (j = 0; j < 1024; j++) {
 229                         rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
 230                         if ((tmp & 0x80) == 0)
 231                                 break;
 232                 }
 233                 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
 234                 rtsx_pci_write_register(pcr, 0xFF08 + i, 0xFF, val);
 235         }
 236         rtsx_pci_write_register(pcr, 0xFF00, 0xFF, (cnt & 0x7F) | 0x80);
 237         rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
 238                 REG_EFUSE_BYPASS | REG_EFUSE_POR, REG_EFUSE_BYPASS);
 239         pcr_dbg(pcr, "Disable efuse por!");
 240 }
 241
 242 static void rts52xa_save_content_to_autoload_space(struct rtsx_pcr *pcr)
 243 {
 244         u8 val;
 245
 246         rtsx_pci_read_register(pcr, RESET_LOAD_REG, &val);
 247         if (val & 0x02) {
 248                 rtsx_pci_read_register(pcr, RTS525A_BIOS_CFG, &val);
 249                 if (val & RTS525A_LOAD_BIOS_FLAG) {
 250                         rtsx_pci_write_register(pcr, RTS525A_BIOS_CFG,
 251                                 RTS525A_LOAD_BIOS_FLAG, RTS525A_CLEAR_BIOS_FLAG);
 252
 253                         rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
 254                                 REG_EFUSE_POWER_MASK, REG_EFUSE_POWERON);
 255
 256                         pcr_dbg(pcr, "Power ON efuse!");
 257                         mdelay(1);
 258                         rts52xa_save_content_from_efuse(pcr);
 259                 } else {
 260                         rtsx_pci_read_register(pcr, RTS524A_PME_FORCE_CTL, &val);
 261                         if (!(val & 0x08))
 262                                 rts52xa_save_content_from_efuse(pcr);
 263                 }
 264         } else {
 265                 pcr_dbg(pcr, "Load from autoload");
 266                 rtsx_pci_write_register(pcr, 0xFF00, 0xFF, 0x80);
 267                 rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr));
 268                 rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8));
 269                 rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr));
 270                 rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8));
 271         }
 272 }
 273
 274 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
 275 {
 276         struct rtsx_cr_option *option = &(pcr->option);
 277
 278         rts5249_init_from_cfg(pcr);
 279         rts5249_init_from_hw(pcr);
 280
 281         rtsx_pci_init_cmd(pcr);
 282
 283         if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A))
 284                 rts52xa_save_content_to_autoload_space(pcr);
 285
 286         /* Rest L1SUB Config */
 287         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
 288         /* Configure GPIO as output */
 289         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
 290         /* Reset ASPM state to default value */
 291         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
 292         /* Switch LDO3318 source from DV33 to card_3v3 */
 293         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
 294         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
 295         /* LED shine disabled, set initial shine cycle period */
 296         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
 297         /* Configure driving */
 298         rts5249_fill_driving(pcr, OUTPUT_3V3);
 299         if (pcr->flags & PCR_REVERSE_SOCKET)
 300                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
 301         else
 302                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
 303
 304         rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
 305
 306         if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
 307                 rtsx_pci_write_register(pcr, REG_VREF, PWD_SUSPND_EN, PWD_SUSPND_EN);
 308                 rtsx_pci_write_register(pcr, RTS524A_AUTOLOAD_CFG1,
 309                         CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
 310         }
 311
 312         if (pcr->rtd3_en) {
 313                 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
 314                         rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x01);
 315                         rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x30);
 316                 } else {
 317                         rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x01);
 318                         rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x33);
 319                 }
 320         } else {
 321                 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
 322                         rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00);
 323                         rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20);
 324                 } else {
 325                         rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x30);
 326                         rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x00);
 327                 }
 328         }
 329
 330         /*
 331          * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
 332          * to drive low, and we forcibly request clock.
 333          */
 334         if (option->force_clkreq_0 && pcr->aspm_mode == ASPM_MODE_CFG)
 335                 rtsx_pci_write_register(pcr, PETXCFG,
 336                         FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
 337         else
 338                 rtsx_pci_write_register(pcr, PETXCFG,
 339                         FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
 340
 341         rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
 342         if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
 343                 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
 344                                 REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF);
 345                 pcr_dbg(pcr, "Power OFF efuse!");
 346         }
 347
 348         return 0;
 349 }
 350
 351 static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
 352 {
 353         int err;
 354
 355         err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
 356         if (err < 0)
 357                 return err;
 358
 359         err = rtsx_pci_write_phy_register(pcr, PHY_REV,
 360                         PHY_REV_RESV | PHY_REV_RXIDLE_LATCHED |
 361                         PHY_REV_P1_EN | PHY_REV_RXIDLE_EN |
 362                         PHY_REV_CLKREQ_TX_EN | PHY_REV_RX_PWST |
 363                         PHY_REV_CLKREQ_DT_1_0 | PHY_REV_STOP_CLKRD |
 364                         PHY_REV_STOP_CLKWR);
 365         if (err < 0)
 366                 return err;
 367
 368         msleep(1);
 369
 370         err = rtsx_pci_write_phy_register(pcr, PHY_BPCR,
 371                         PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL |
 372                         PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN);
 373         if (err < 0)
 374                 return err;
 375
 376         err = rtsx_pci_write_phy_register(pcr, PHY_PCR,
 377                         PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
 378                         PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 |
 379                         PHY_PCR_RSSI_EN | PHY_PCR_RX10K);
 380         if (err < 0)
 381                 return err;
 382
 383         err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
 384                         PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR |
 385                         PHY_RCR2_CDR_SR_2 | PHY_RCR2_FREQSEL_12 |
 386                         PHY_RCR2_CDR_SC_12P | PHY_RCR2_CALIB_LATE);
 387         if (err < 0)
 388                 return err;
 389
 390         err = rtsx_pci_write_phy_register(pcr, PHY_FLD4,
 391                         PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF |
 392                         PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA |
 393                         PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER |
 394                         PHY_FLD4_BER_CHK_EN);
 395         if (err < 0)
 396                 return err;
 397         err = rtsx_pci_write_phy_register(pcr, PHY_RDR,
 398                         PHY_RDR_RXDSEL_1_9 | PHY_SSC_AUTO_PWD);
 399         if (err < 0)
 400                 return err;
 401         err = rtsx_pci_write_phy_register(pcr, PHY_RCR1,
 402                         PHY_RCR1_ADP_TIME_4 | PHY_RCR1_VCO_COARSE);
 403         if (err < 0)
 404                 return err;
 405         err = rtsx_pci_write_phy_register(pcr, PHY_FLD3,
 406                         PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 |
 407                         PHY_FLD3_RXDELINK);
 408         if (err < 0)
 409                 return err;
 410
 411         return rtsx_pci_write_phy_register(pcr, PHY_TUNE,
 412                         PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 |
 413                         PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 |
 414                         PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12);
 415 }
 416
 417 static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr)
 418 {
 419         return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
 420 }
 421
 422 static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr)
 423 {
 424         return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
 425 }
 426
 427 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
 428 {
 429         return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
 430 }
 431
 432 static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
 433 {
 434         return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
 435 }
 436
 437 static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card)
 438 {
 439         int err;
 440         struct rtsx_cr_option *option = &pcr->option;
 441
 442         if (option->ocp_en)
 443                 rtsx_pci_enable_ocp(pcr);
 444
 445         rtsx_pci_init_cmd(pcr);
 446         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
 447                         SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
 448         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
 449                         LDO3318_PWR_MASK, 0x02);
 450         err = rtsx_pci_send_cmd(pcr, 100);
 451         if (err < 0)
 452                 return err;
 453
 454         msleep(5);
 455
 456         rtsx_pci_init_cmd(pcr);
 457         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
 458                         SD_POWER_MASK, SD_VCC_POWER_ON);
 459         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
 460                         LDO3318_PWR_MASK, 0x06);
 461         return rtsx_pci_send_cmd(pcr, 100);
 462 }
 463
 464 static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card)
 465 {
 466         struct rtsx_cr_option *option = &pcr->option;
 467
 468         if (option->ocp_en)
 469                 rtsx_pci_disable_ocp(pcr);
 470
 471         rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK, SD_POWER_OFF);
 472
 473         rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0x00);
 474         return 0;
 475 }
 476
 477 static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 478 {
 479         int err;
 480         u16 append;
 481
 482         switch (voltage) {
 483         case OUTPUT_3V3:
 484                 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
 485                         PHY_TUNE_VOLTAGE_3V3);
 486                 if (err < 0)
 487                         return err;
 488                 break;
 489         case OUTPUT_1V8:
 490                 append = PHY_TUNE_D18_1V8;
 491                 if (CHK_PCI_PID(pcr, 0x5249)) {
 492                         err = rtsx_pci_update_phy(pcr, PHY_BACR,
 493                                 PHY_BACR_BASIC_MASK, 0);
 494                         if (err < 0)
 495                                 return err;
 496                         append = PHY_TUNE_D18_1V7;
 497                 }
 498
 499                 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
 500                         append);
 501                 if (err < 0)
 502                         return err;
 503                 break;
 504         default:
 505                 pcr_dbg(pcr, "unknown output voltage %d\n", voltage);
 506                 return -EINVAL;
 507         }
 508
 509         /* set pad drive */
 510         rtsx_pci_init_cmd(pcr);
 511         rts5249_fill_driving(pcr, voltage);
 512         return rtsx_pci_send_cmd(pcr, 100);
 513 }
 514
 515 static const struct pcr_ops rts5249_pcr_ops = {
 516         .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
 517         .extra_init_hw = rts5249_extra_init_hw,
 518         .optimize_phy = rts5249_optimize_phy,
 519         .turn_on_led = rtsx_base_turn_on_led,
 520         .turn_off_led = rtsx_base_turn_off_led,
 521         .enable_auto_blink = rtsx_base_enable_auto_blink,
 522         .disable_auto_blink = rtsx_base_disable_auto_blink,
 523         .card_power_on = rtsx_base_card_power_on,
 524         .card_power_off = rtsx_base_card_power_off,
 525         .switch_output_voltage = rtsx_base_switch_output_voltage,
 526 };
 527
 528 /* SD Pull Control Enable:
 529  *     SD_DAT[3:0] ==> pull up
 530  *     SD_CD       ==> pull up
 531  *     SD_WP       ==> pull up
 532  *     SD_CMD      ==> pull up
 533  *     SD_CLK      ==> pull down
 534  */
 535 static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
 536         RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
 537         RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
 538         RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
 539         RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
 540         0,
 541 };
 542
 543 /* SD Pull Control Disable:
 544  *     SD_DAT[3:0] ==> pull down
 545  *     SD_CD       ==> pull up
 546  *     SD_WP       ==> pull down
 547  *     SD_CMD      ==> pull down
 548  *     SD_CLK      ==> pull down
 549  */
 550 static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
 551         RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
 552         RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
 553         RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
 554         RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
 555         0,
 556 };
 557
 558 /* MS Pull Control Enable:
 559  *     MS CD       ==> pull up
 560  *     others      ==> pull down
 561  */
 562 static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
 563         RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
 564         RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
 565         RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
 566         0,
 567 };
 568
 569 /* MS Pull Control Disable:
 570  *     MS CD       ==> pull up
 571  *     others      ==> pull down
 572  */
 573 static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
 574         RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
 575         RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
 576         RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
 577         0,
 578 };
 579
 580 void rts5249_init_params(struct rtsx_pcr *pcr)
 581 {
 582         struct rtsx_cr_option *option = &(pcr->option);
 583
 584         pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
 585         pcr->num_slots = 2;
 586         pcr->ops = &rts5249_pcr_ops;
 587
 588         pcr->flags = 0;
 589         pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
 590         pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
 591         pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
 592         pcr->aspm_en = ASPM_L1_EN;
 593         pcr->aspm_mode = ASPM_MODE_CFG;
 594         pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
 595         pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
 596
 597         pcr->ic_version = rts5249_get_ic_version(pcr);
 598         pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
 599         pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
 600         pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
 601         pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
 602
 603         pcr->reg_pm_ctrl3 = PM_CTRL3;
 604
 605         option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
 606                                 | LTR_L1SS_PWR_GATE_EN);
 607         option->ltr_en = true;
 608
 609         /* Init latency of active, idle, L1OFF to 60us, 300us, 3ms */
 610         option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
 611         option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
 612         option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
 613         option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
 614         option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5249_DEF;
 615         option->ltr_l1off_snooze_sspwrgate =
 616                 LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF;
 617 }
 618
 619 static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val)
 620 {
 621         addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
 622
 623         return __rtsx_pci_write_phy_register(pcr, addr, val);
 624 }
 625
 626 static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val)
 627 {
 628         addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
 629
 630         return __rtsx_pci_read_phy_register(pcr, addr, val);
 631 }
 632
 633 static int rts524a_optimize_phy(struct rtsx_pcr *pcr)
 634 {
 635         int err;
 636
 637         err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
 638                 D3_DELINK_MODE_EN, 0x00);
 639         if (err < 0)
 640                 return err;
 641
 642         rtsx_pci_write_phy_register(pcr, PHY_PCR,
 643                 PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
 644                 PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN);
 645         rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
 646                 PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
 647
 648         if (is_version(pcr, 0x524A, IC_VER_A)) {
 649                 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
 650                         PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
 651                 rtsx_pci_write_phy_register(pcr, PHY_SSCCR2,
 652                         PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 |
 653                         PHY_SSCCR2_TIME2_WIDTH);
 654                 rtsx_pci_write_phy_register(pcr, PHY_ANA1A,
 655                         PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST |
 656                         PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV);
 657                 rtsx_pci_write_phy_register(pcr, PHY_ANA1D,
 658                         PHY_ANA1D_DEBUG_ADDR);
 659                 rtsx_pci_write_phy_register(pcr, PHY_DIG1E,
 660                         PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 |
 661                         PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST |
 662                         PHY_DIG1E_RCLK_TX_EN_KEEP |
 663                         PHY_DIG1E_RCLK_TX_TERM_KEEP |
 664                         PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP |
 665                         PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP |
 666                         PHY_DIG1E_RX_EN_KEEP);
 667         }
 668
 669         rtsx_pci_write_phy_register(pcr, PHY_ANA08,
 670                 PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN |
 671                 PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI);
 672
 673         return 0;
 674 }
 675
 676 static int rts524a_extra_init_hw(struct rtsx_pcr *pcr)
 677 {
 678         rts5249_extra_init_hw(pcr);
 679
 680         rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
 681                 FORCE_ASPM_L1_EN, FORCE_ASPM_L1_EN);
 682         rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
 683         rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN,
 684                 LDO_VCC_LMT_EN);
 685         rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
 686         if (is_version(pcr, 0x524A, IC_VER_A)) {
 687                 rtsx_pci_write_register(pcr, LDO_DV18_CFG,
 688                         LDO_DV18_SR_MASK, LDO_DV18_SR_DF);
 689                 rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
 690                         LDO_VCC_REF_TUNE_MASK, LDO_VCC_REF_1V2);
 691                 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
 692                         LDO_VIO_REF_TUNE_MASK, LDO_VIO_REF_1V2);
 693                 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
 694                         LDO_VIO_SR_MASK, LDO_VIO_SR_DF);
 695                 rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
 696                         LDO_REF12_TUNE_MASK, LDO_REF12_TUNE_DF);
 697                 rtsx_pci_write_register(pcr, SD40_LDO_CTL1,
 698                         SD40_VIO_TUNE_MASK, SD40_VIO_TUNE_1V7);
 699         }
 700
 701         return 0;
 702 }
 703
 704 static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
 705 {
 706         struct rtsx_cr_option *option = &(pcr->option);
 707
 708         u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
 709         int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST);
 710         int aspm_L1_1, aspm_L1_2;
 711         u8 val = 0;
 712
 713         aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
 714         aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
 715
 716         if (active) {
 717                 /* Run, latency: 60us */
 718                 if (aspm_L1_1)
 719                         val = option->ltr_l1off_snooze_sspwrgate;
 720         } else {
 721                 /* L1off, latency: 300us */
 722                 if (aspm_L1_2)
 723                         val = option->ltr_l1off_sspwrgate;
 724         }
 725
 726         if (aspm_L1_1 || aspm_L1_2) {
 727                 if (rtsx_check_dev_flag(pcr,
 728                                         LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) {
 729                         if (card_exist)
 730                                 val &= ~L1OFF_MBIAS2_EN_5250;
 731                         else
 732                                 val |= L1OFF_MBIAS2_EN_5250;
 733                 }
 734         }
 735         rtsx_set_l1off_sub(pcr, val);
 736 }
 737
 738 static const struct pcr_ops rts524a_pcr_ops = {
 739         .write_phy = rts524a_write_phy,
 740         .read_phy = rts524a_read_phy,
 741         .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
 742         .extra_init_hw = rts524a_extra_init_hw,
 743         .optimize_phy = rts524a_optimize_phy,
 744         .turn_on_led = rtsx_base_turn_on_led,
 745         .turn_off_led = rtsx_base_turn_off_led,
 746         .enable_auto_blink = rtsx_base_enable_auto_blink,
 747         .disable_auto_blink = rtsx_base_disable_auto_blink,
 748         .card_power_on = rtsx_base_card_power_on,
 749         .card_power_off = rtsx_base_card_power_off,
 750         .switch_output_voltage = rtsx_base_switch_output_voltage,
 751         .force_power_down = rts52xa_force_power_down,
 752         .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
 753 };
 754
 755 void rts524a_init_params(struct rtsx_pcr *pcr)
 756 {
 757         rts5249_init_params(pcr);
 758         pcr->aspm_mode = ASPM_MODE_REG;
 759         pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
 760         pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
 761         pcr->option.ltr_l1off_snooze_sspwrgate =
 762                 LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
 763
 764         pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
 765         pcr->ops = &rts524a_pcr_ops;
 766
 767         pcr->option.ocp_en = 1;
 768         if (pcr->option.ocp_en)
 769                 pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
 770         pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
 771         pcr->option.sd_800mA_ocp_thd = RTS524A_OCP_THD_800;
 772
 773 }
 774
 775 static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card)
 776 {
 777         rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
 778                 LDO_VCC_TUNE_MASK, LDO_VCC_3V3);
 779         return rtsx_base_card_power_on(pcr, card);
 780 }
 781
 782 static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 783 {
 784         switch (voltage) {
 785         case OUTPUT_3V3:
 786                 rtsx_pci_write_register(pcr, LDO_CONFIG2,
 787                         LDO_D3318_MASK, LDO_D3318_33V);
 788                 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);
 789                 break;
 790         case OUTPUT_1V8:
 791                 rtsx_pci_write_register(pcr, LDO_CONFIG2,
 792                         LDO_D3318_MASK, LDO_D3318_18V);
 793                 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,
 794                         SD_IO_USING_1V8);
 795                 break;
 796         default:
 797                 return -EINVAL;
 798         }
 799
 800         rtsx_pci_init_cmd(pcr);
 801         rts5249_fill_driving(pcr, voltage);
 802         return rtsx_pci_send_cmd(pcr, 100);
 803 }
 804
 805 static int rts525a_optimize_phy(struct rtsx_pcr *pcr)
 806 {
 807         int err;
 808
 809         err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
 810                 D3_DELINK_MODE_EN, 0x00);
 811         if (err < 0)
 812                 return err;
 813
 814         rtsx_pci_write_phy_register(pcr, _PHY_FLD0,
 815                 _PHY_FLD0_CLK_REQ_20C | _PHY_FLD0_RX_IDLE_EN |
 816                 _PHY_FLD0_BIT_ERR_RSTN | _PHY_FLD0_BER_COUNT |
 817                 _PHY_FLD0_BER_TIMER | _PHY_FLD0_CHECK_EN);
 818
 819         rtsx_pci_write_phy_register(pcr, _PHY_ANA03,
 820                 _PHY_ANA03_TIMER_MAX | _PHY_ANA03_OOBS_DEB_EN |
 821                 _PHY_CMU_DEBUG_EN);
 822
 823         if (is_version(pcr, 0x525A, IC_VER_A))
 824                 rtsx_pci_write_phy_register(pcr, _PHY_REV0,
 825                         _PHY_REV0_FILTER_OUT | _PHY_REV0_CDR_BYPASS_PFD |
 826                         _PHY_REV0_CDR_RX_IDLE_BYPASS);
 827
 828         return 0;
 829 }
 830
 831 static int rts525a_extra_init_hw(struct rtsx_pcr *pcr)
 832 {
 833         rts5249_extra_init_hw(pcr);
 834
 835         rtsx_pci_write_register(pcr, RTS5250_CLK_CFG3, RTS525A_CFG_MEM_PD, RTS525A_CFG_MEM_PD);
 836
 837         rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
 838         if (is_version(pcr, 0x525A, IC_VER_A)) {
 839                 rtsx_pci_write_register(pcr, L1SUB_CONFIG2,
 840                         L1SUB_AUTO_CFG, L1SUB_AUTO_CFG);
 841                 rtsx_pci_write_register(pcr, RREF_CFG,
 842                         RREF_VBGSEL_MASK, RREF_VBGSEL_1V25);
 843                 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
 844                         LDO_VIO_TUNE_MASK, LDO_VIO_1V7);
 845                 rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
 846                         LDO_D12_TUNE_MASK, LDO_D12_TUNE_DF);
 847                 rtsx_pci_write_register(pcr, LDO_AV12S_CFG,
 848                         LDO_AV12S_TUNE_MASK, LDO_AV12S_TUNE_DF);
 849                 rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
 850                         LDO_VCC_LMTVTH_MASK, LDO_VCC_LMTVTH_2A);
 851                 rtsx_pci_write_register(pcr, OOBS_CONFIG,
 852                         OOBS_AUTOK_DIS | OOBS_VAL_MASK, 0x89);
 853         }
 854
 855         return 0;
 856 }
 857
 858 static const struct pcr_ops rts525a_pcr_ops = {
 859         .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
 860         .extra_init_hw = rts525a_extra_init_hw,
 861         .optimize_phy = rts525a_optimize_phy,
 862         .turn_on_led = rtsx_base_turn_on_led,
 863         .turn_off_led = rtsx_base_turn_off_led,
 864         .enable_auto_blink = rtsx_base_enable_auto_blink,
 865         .disable_auto_blink = rtsx_base_disable_auto_blink,
 866         .card_power_on = rts525a_card_power_on,
 867         .card_power_off = rtsx_base_card_power_off,
 868         .switch_output_voltage = rts525a_switch_output_voltage,
 869         .force_power_down = rts52xa_force_power_down,
 870         .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
 871 };
 872
 873 void rts525a_init_params(struct rtsx_pcr *pcr)
 874 {
 875         rts5249_init_params(pcr);
 876         pcr->aspm_mode = ASPM_MODE_REG;
 877         pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11);
 878         pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
 879         pcr->option.ltr_l1off_snooze_sspwrgate =
 880                 LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
 881
 882         pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
 883         pcr->ops = &rts525a_pcr_ops;
 884
 885         pcr->option.ocp_en = 1;
 886         if (pcr->option.ocp_en)
 887                 pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
 888         pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
 889         pcr->option.sd_800mA_ocp_thd = RTS525A_OCP_THD_800;
 890 }