drivers/misc/cardreader/rts5228.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /* Driver for Realtek PCI-Express card reader
   3  *
   4  * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
   5  *
   6  * Author:
   7  *   Ricky WU <ricky_wu@realtek.com>
   8  *   Rui FENG <rui_feng@realsil.com.cn>
   9  *   Wei WANG <wei_wang@realsil.com.cn>
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/delay.h>
  14 #include <linux/rtsx_pci.h>
  15
  16 #include "rts5228.h"
  17 #include "rtsx_pcr.h"
  18
  19 static u8 rts5228_get_ic_version(struct rtsx_pcr *pcr)
  20 {
  21         u8 val;
  22
  23         rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  24         return val & IC_VERSION_MASK;
  25 }
  26
  27 static void rts5228_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  28 {
  29         u8 driving_3v3[4][3] = {
  30                 {0x13, 0x13, 0x13},
  31                 {0x96, 0x96, 0x96},
  32                 {0x7F, 0x7F, 0x7F},
  33                 {0x96, 0x96, 0x96},
  34         };
  35         u8 driving_1v8[4][3] = {
  36                 {0x99, 0x99, 0x99},
  37                 {0xB5, 0xB5, 0xB5},
  38                 {0xE6, 0x7E, 0xFE},
  39                 {0x6B, 0x6B, 0x6B},
  40         };
  41         u8 (*driving)[3], drive_sel;
  42
  43         if (voltage == OUTPUT_3V3) {
  44                 driving = driving_3v3;
  45                 drive_sel = pcr->sd30_drive_sel_3v3;
  46         } else {
  47                 driving = driving_1v8;
  48                 drive_sel = pcr->sd30_drive_sel_1v8;
  49         }
  50
  51         rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
  52                          0xFF, driving[drive_sel][0]);
  53
  54         rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
  55                          0xFF, driving[drive_sel][1]);
  56
  57         rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
  58                          0xFF, driving[drive_sel][2]);
  59 }
  60
  61 static void rtsx5228_fetch_vendor_settings(struct rtsx_pcr *pcr)
  62 {
  63         struct pci_dev *pdev = pcr->pci;
  64         u32 reg;
  65
  66         /* 0x724~0x727 */
  67         pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
  68         pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  69
  70         if (!rtsx_vendor_setting_valid(reg)) {
  71                 pcr_dbg(pcr, "skip fetch vendor setting\n");
  72                 return;
  73         }
  74         pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  75         pcr->aspm_en = rtsx_reg_to_aspm(reg);
  76
  77         /* 0x814~0x817 */
  78         pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
  79         pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  80
  81         pcr->rtd3_en = rtsx_reg_to_rtd3(reg);
  82         if (rtsx_check_mmc_support(reg))
  83                 pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
  84         pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  85         if (rtsx_reg_check_reverse_socket(reg))
  86                 pcr->flags |= PCR_REVERSE_SOCKET;
  87 }
  88
  89 static int rts5228_optimize_phy(struct rtsx_pcr *pcr)
  90 {
  91         return rtsx_pci_write_phy_register(pcr, 0x07, 0x8F40);
  92 }
  93
  94 static void rts5228_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
  95 {
  96         /* Set relink_time to 0 */
  97         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
  98         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
  99         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
 100                                 RELINK_TIME_MASK, 0);
 101
 102         rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
 103                         D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
 104
 105         if (!runtime) {
 106                 rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1,
 107                                 CD_RESUME_EN_MASK, 0);
 108                 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
 109                 rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL,
 110                                 FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
 111         }
 112
 113         rtsx_pci_write_register(pcr, FPDCTL,
 114                 SSC_POWER_DOWN, SSC_POWER_DOWN);
 115 }
 116
 117 static int rts5228_enable_auto_blink(struct rtsx_pcr *pcr)
 118 {
 119         return rtsx_pci_write_register(pcr, OLT_LED_CTL,
 120                 LED_SHINE_MASK, LED_SHINE_EN);
 121 }
 122
 123 static int rts5228_disable_auto_blink(struct rtsx_pcr *pcr)
 124 {
 125         return rtsx_pci_write_register(pcr, OLT_LED_CTL,
 126                 LED_SHINE_MASK, LED_SHINE_DISABLE);
 127 }
 128
 129 static int rts5228_turn_on_led(struct rtsx_pcr *pcr)
 130 {
 131         return rtsx_pci_write_register(pcr, GPIO_CTL,
 132                 0x02, 0x02);
 133 }
 134
 135 static int rts5228_turn_off_led(struct rtsx_pcr *pcr)
 136 {
 137         return rtsx_pci_write_register(pcr, GPIO_CTL,
 138                 0x02, 0x00);
 139 }
 140
 141 /* SD Pull Control Enable:
 142  *     SD_DAT[3:0] ==> pull up
 143  *     SD_CD       ==> pull up
 144  *     SD_WP       ==> pull up
 145  *     SD_CMD      ==> pull up
 146  *     SD_CLK      ==> pull down
 147  */
 148 static const u32 rts5228_sd_pull_ctl_enable_tbl[] = {
 149         RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
 150         RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
 151         0,
 152 };
 153
 154 /* SD Pull Control Disable:
 155  *     SD_DAT[3:0] ==> pull down
 156  *     SD_CD       ==> pull up
 157  *     SD_WP       ==> pull down
 158  *     SD_CMD      ==> pull down
 159  *     SD_CLK      ==> pull down
 160  */
 161 static const u32 rts5228_sd_pull_ctl_disable_tbl[] = {
 162         RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
 163         RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
 164         0,
 165 };
 166
 167 static int rts5228_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
 168 {
 169         rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
 170                 | SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
 171         rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
 172         rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
 173                         CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
 174         rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
 175
 176         return 0;
 177 }
 178
 179 static int rts5228_card_power_on(struct rtsx_pcr *pcr, int card)
 180 {
 181         struct rtsx_cr_option *option = &pcr->option;
 182
 183         if (option->ocp_en)
 184                 rtsx_pci_enable_ocp(pcr);
 185
 186         rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,
 187                         CFG_SD_POW_AUTO_PD, CFG_SD_POW_AUTO_PD);
 188
 189         rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG1,
 190                         RTS5228_LDO1_TUNE_MASK, RTS5228_LDO1_33);
 191
 192         rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
 193                         RTS5228_LDO1_POWERON_MASK, RTS5228_LDO1_SOFTSTART);
 194         mdelay(2);
 195         rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
 196                         RTS5228_LDO1_POWERON_MASK, RTS5228_LDO1_FULLON);
 197
 198
 199         rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
 200                         RTS5228_LDO3318_POWERON, RTS5228_LDO3318_POWERON);
 201
 202         msleep(20);
 203
 204         rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
 205
 206         /* Initialize SD_CFG1 register */
 207         rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
 208                         SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1BIT);
 209
 210         rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
 211                         0xFF, SD20_RX_POS_EDGE);
 212         rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
 213         rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
 214                         SD_STOP | SD_CLR_ERR);
 215
 216         /* Reset SD_CFG3 register */
 217         rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
 218         rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
 219                         SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |
 220                         SD30_CLK_STOP_CFG0, 0);
 221
 222         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
 223             pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
 224                 rts5228_sd_set_sample_push_timing_sd30(pcr);
 225
 226         return 0;
 227 }
 228
 229 static int rts5228_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 230 {
 231         int err;
 232         u16 val = 0;
 233
 234         rtsx_pci_write_register(pcr, RTS5228_CARD_PWR_CTL,
 235                         RTS5228_PUPDC, RTS5228_PUPDC);
 236
 237         switch (voltage) {
 238         case OUTPUT_3V3:
 239                 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
 240                 val |= PHY_TUNE_SDBUS_33;
 241                 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
 242                 if (err < 0)
 243                         return err;
 244
 245                 rtsx_pci_write_register(pcr, RTS5228_DV3318_CFG,
 246                                 RTS5228_DV3318_TUNE_MASK, RTS5228_DV3318_33);
 247                 rtsx_pci_write_register(pcr, SD_PAD_CTL,
 248                                 SD_IO_USING_1V8, 0);
 249                 break;
 250         case OUTPUT_1V8:
 251                 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
 252                 val &= ~PHY_TUNE_SDBUS_33;
 253                 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
 254                 if (err < 0)
 255                         return err;
 256
 257                 rtsx_pci_write_register(pcr, RTS5228_DV3318_CFG,
 258                                 RTS5228_DV3318_TUNE_MASK, RTS5228_DV3318_18);
 259                 rtsx_pci_write_register(pcr, SD_PAD_CTL,
 260                                 SD_IO_USING_1V8, SD_IO_USING_1V8);
 261                 break;
 262         default:
 263                 return -EINVAL;
 264         }
 265
 266         /* set pad drive */
 267         rts5228_fill_driving(pcr, voltage);
 268
 269         return 0;
 270 }
 271
 272 static void rts5228_stop_cmd(struct rtsx_pcr *pcr)
 273 {
 274         rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
 275         rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
 276         rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
 277                                 RTS5260_DMA_RST | RTS5260_ADMA3_RST,
 278                                 RTS5260_DMA_RST | RTS5260_ADMA3_RST);
 279         rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
 280 }
 281
 282 static void rts5228_card_before_power_off(struct rtsx_pcr *pcr)
 283 {
 284         rts5228_stop_cmd(pcr);
 285         rts5228_switch_output_voltage(pcr, OUTPUT_3V3);
 286 }
 287
 288 static void rts5228_enable_ocp(struct rtsx_pcr *pcr)
 289 {
 290         u8 val = 0;
 291
 292         val = SD_OCP_INT_EN | SD_DETECT_EN;
 293         rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
 294         rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
 295                         RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN,
 296                         RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN);
 297 }
 298
 299 static void rts5228_disable_ocp(struct rtsx_pcr *pcr)
 300 {
 301         u8 mask = 0;
 302
 303         mask = SD_OCP_INT_EN | SD_DETECT_EN;
 304         rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
 305         rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
 306                         RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, 0);
 307 }
 308
 309 static int rts5228_card_power_off(struct rtsx_pcr *pcr, int card)
 310 {
 311         int err = 0;
 312
 313         rts5228_card_before_power_off(pcr);
 314         err = rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
 315                                 RTS5228_LDO_POWERON_MASK, 0);
 316         rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0, CFG_SD_POW_AUTO_PD, 0);
 317
 318         if (pcr->option.ocp_en)
 319                 rtsx_pci_disable_ocp(pcr);
 320
 321         return err;
 322 }
 323
 324 static void rts5228_init_ocp(struct rtsx_pcr *pcr)
 325 {
 326         struct rtsx_cr_option *option = &pcr->option;
 327
 328         if (option->ocp_en) {
 329                 u8 mask, val;
 330
 331                 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
 332                         RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN,
 333                         RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN);
 334
 335                 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
 336                         RTS5228_LDO1_OCP_THD_MASK, option->sd_800mA_ocp_thd);
 337
 338                 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
 339                         RTS5228_LDO1_OCP_LMT_THD_MASK,
 340                         RTS5228_LDO1_LMT_THD_1500);
 341
 342                 rtsx_pci_read_register(pcr, RTS5228_LDO1_CFG0, &val);
 343
 344                 mask = SD_OCP_GLITCH_MASK;
 345                 val = pcr->hw_param.ocp_glitch;
 346                 rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
 347
 348                 rts5228_enable_ocp(pcr);
 349
 350         } else {
 351                 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
 352                         RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, 0);
 353         }
 354 }
 355
 356 static void rts5228_clear_ocpstat(struct rtsx_pcr *pcr)
 357 {
 358         u8 mask = 0;
 359         u8 val = 0;
 360
 361         mask = SD_OCP_INT_CLR | SD_OC_CLR;
 362         val = SD_OCP_INT_CLR | SD_OC_CLR;
 363
 364         rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
 365
 366         udelay(1000);
 367         rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
 368
 369 }
 370
 371 static void rts5228_process_ocp(struct rtsx_pcr *pcr)
 372 {
 373         if (!pcr->option.ocp_en)
 374                 return;
 375
 376         rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
 377
 378         if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
 379                 rts5228_clear_ocpstat(pcr);
 380                 rts5228_card_power_off(pcr, RTSX_SD_CARD);
 381                 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
 382                 pcr->ocp_stat = 0;
 383         }
 384
 385 }
 386
 387 static void rts5228_init_from_cfg(struct rtsx_pcr *pcr)
 388 {
 389         struct pci_dev *pdev = pcr->pci;
 390         int l1ss;
 391         u32 lval;
 392         struct rtsx_cr_option *option = &pcr->option;
 393
 394         l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
 395         if (!l1ss)
 396                 return;
 397
 398         pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
 399
 400         if (0 == (lval & 0x0F))
 401                 rtsx_pci_enable_oobs_polling(pcr);
 402         else
 403                 rtsx_pci_disable_oobs_polling(pcr);
 404
 405         if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
 406                 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
 407         else
 408                 rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
 409
 410         if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
 411                 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
 412         else
 413                 rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
 414
 415         if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
 416                 rtsx_set_dev_flag(pcr, PM_L1_1_EN);
 417         else
 418                 rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
 419
 420         if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
 421                 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
 422         else
 423                 rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
 424
 425         rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
 426         if (option->ltr_en) {
 427                 u16 val;
 428
 429                 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
 430                 if (val & PCI_EXP_DEVCTL2_LTR_EN) {
 431                         option->ltr_enabled = true;
 432                         option->ltr_active = true;
 433                         rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
 434                 } else {
 435                         option->ltr_enabled = false;
 436                 }
 437         }
 438 }
 439
 440 static int rts5228_extra_init_hw(struct rtsx_pcr *pcr)
 441 {
 442
 443         rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1,
 444                         CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
 445
 446         rts5228_init_from_cfg(pcr);
 447
 448         rtsx_pci_write_register(pcr, L1SUB_CONFIG1,
 449                         AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE);
 450         rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);
 451
 452         rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
 453                         FUNC_FORCE_UPME_XMT_DBG, FUNC_FORCE_UPME_XMT_DBG);
 454
 455         rtsx_pci_write_register(pcr, PCLK_CTL,
 456                         PCLK_MODE_SEL, PCLK_MODE_SEL);
 457
 458         rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
 459         rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN);
 460
 461         /* LED shine disabled, set initial shine cycle period */
 462         rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);
 463
 464         /* Configure driving */
 465         rts5228_fill_driving(pcr, OUTPUT_3V3);
 466
 467         if (pcr->flags & PCR_REVERSE_SOCKET)
 468                 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30);
 469         else
 470                 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);
 471
 472         rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB);
 473
 474         if (pcr->rtd3_en) {
 475                 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x01);
 476                 rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL,
 477                                 FORCE_PM_CONTROL | FORCE_PM_VALUE,
 478                                 FORCE_PM_CONTROL | FORCE_PM_VALUE);
 479         } else {
 480                 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
 481                 rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL,
 482                                 FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
 483         }
 484         rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, D3_DELINK_MODE_EN, 0x00);
 485
 486         return 0;
 487 }
 488
 489 static void rts5228_enable_aspm(struct rtsx_pcr *pcr, bool enable)
 490 {
 491         u8 mask, val;
 492
 493         if (pcr->aspm_enabled == enable)
 494                 return;
 495
 496         mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
 497         val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
 498         val |= (pcr->aspm_en & 0x02);
 499         rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
 500         pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
 501                                            PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en);
 502         pcr->aspm_enabled = enable;
 503 }
 504
 505 static void rts5228_disable_aspm(struct rtsx_pcr *pcr, bool enable)
 506 {
 507         u8 mask, val;
 508
 509         if (pcr->aspm_enabled == enable)
 510                 return;
 511
 512         pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
 513                                            PCI_EXP_LNKCTL_ASPMC, 0);
 514         mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
 515         val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
 516         rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
 517         rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
 518         mdelay(10);
 519         pcr->aspm_enabled = enable;
 520 }
 521
 522 static void rts5228_set_aspm(struct rtsx_pcr *pcr, bool enable)
 523 {
 524         if (enable)
 525                 rts5228_enable_aspm(pcr, true);
 526         else
 527                 rts5228_disable_aspm(pcr, false);
 528 }
 529
 530 static void rts5228_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
 531 {
 532         struct rtsx_cr_option *option = &pcr->option;
 533         int aspm_L1_1, aspm_L1_2;
 534         u8 val = 0;
 535
 536         aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
 537         aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
 538
 539         if (active) {
 540                 /* run, latency: 60us */
 541                 if (aspm_L1_1)
 542                         val = option->ltr_l1off_snooze_sspwrgate;
 543         } else {
 544                 /* l1off, latency: 300us */
 545                 if (aspm_L1_2)
 546                         val = option->ltr_l1off_sspwrgate;
 547         }
 548
 549         rtsx_set_l1off_sub(pcr, val);
 550 }
 551
 552 static const struct pcr_ops rts5228_pcr_ops = {
 553         .fetch_vendor_settings = rtsx5228_fetch_vendor_settings,
 554         .turn_on_led = rts5228_turn_on_led,
 555         .turn_off_led = rts5228_turn_off_led,
 556         .extra_init_hw = rts5228_extra_init_hw,
 557         .enable_auto_blink = rts5228_enable_auto_blink,
 558         .disable_auto_blink = rts5228_disable_auto_blink,
 559         .card_power_on = rts5228_card_power_on,
 560         .card_power_off = rts5228_card_power_off,
 561         .switch_output_voltage = rts5228_switch_output_voltage,
 562         .force_power_down = rts5228_force_power_down,
 563         .stop_cmd = rts5228_stop_cmd,
 564         .set_aspm = rts5228_set_aspm,
 565         .set_l1off_cfg_sub_d0 = rts5228_set_l1off_cfg_sub_d0,
 566         .enable_ocp = rts5228_enable_ocp,
 567         .disable_ocp = rts5228_disable_ocp,
 568         .init_ocp = rts5228_init_ocp,
 569         .process_ocp = rts5228_process_ocp,
 570         .clear_ocpstat = rts5228_clear_ocpstat,
 571         .optimize_phy = rts5228_optimize_phy,
 572 };
 573
 574
 575 static inline u8 double_ssc_depth(u8 depth)
 576 {
 577         return ((depth > 1) ? (depth - 1) : depth);
 578 }
 579
 580 int rts5228_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
 581                 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
 582 {
 583         int err, clk;
 584         u16 n;
 585         u8 clk_divider, mcu_cnt, div;
 586         static const u8 depth[] = {
 587                 [RTSX_SSC_DEPTH_4M] = RTS5228_SSC_DEPTH_4M,
 588                 [RTSX_SSC_DEPTH_2M] = RTS5228_SSC_DEPTH_2M,
 589                 [RTSX_SSC_DEPTH_1M] = RTS5228_SSC_DEPTH_1M,
 590                 [RTSX_SSC_DEPTH_500K] = RTS5228_SSC_DEPTH_512K,
 591         };
 592
 593         if (initial_mode) {
 594                 /* We use 250k(around) here, in initial stage */
 595                 clk_divider = SD_CLK_DIVIDE_128;
 596                 card_clock = 30000000;
 597         } else {
 598                 clk_divider = SD_CLK_DIVIDE_0;
 599         }
 600         err = rtsx_pci_write_register(pcr, SD_CFG1,
 601                         SD_CLK_DIVIDE_MASK, clk_divider);
 602         if (err < 0)
 603                 return err;
 604
 605         card_clock /= 1000000;
 606         pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
 607
 608         clk = card_clock;
 609         if (!initial_mode && double_clk)
 610                 clk = card_clock * 2;
 611         pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
 612                 clk, pcr->cur_clock);
 613
 614         if (clk == pcr->cur_clock)
 615                 return 0;
 616
 617         if (pcr->ops->conv_clk_and_div_n)
 618                 n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
 619         else
 620                 n = clk - 4;
 621         if ((clk <= 4) || (n > 396))
 622                 return -EINVAL;
 623
 624         mcu_cnt = 125/clk + 3;
 625         if (mcu_cnt > 15)
 626                 mcu_cnt = 15;
 627
 628         div = CLK_DIV_1;
 629         while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) {
 630                 if (pcr->ops->conv_clk_and_div_n) {
 631                         int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
 632                                         DIV_N_TO_CLK) * 2;
 633                         n = pcr->ops->conv_clk_and_div_n(dbl_clk,
 634                                         CLK_TO_DIV_N);
 635                 } else {
 636                         n = (n + 4) * 2 - 4;
 637                 }
 638                 div++;
 639         }
 640
 641         n = (n / 2) - 1;
 642         pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
 643
 644         ssc_depth = depth[ssc_depth];
 645         if (double_clk)
 646                 ssc_depth = double_ssc_depth(ssc_depth);
 647
 648         if (ssc_depth) {
 649                 if (div == CLK_DIV_2) {
 650                         if (ssc_depth > 1)
 651                                 ssc_depth -= 1;
 652                         else
 653                                 ssc_depth = RTS5228_SSC_DEPTH_8M;
 654                 } else if (div == CLK_DIV_4) {
 655                         if (ssc_depth > 2)
 656                                 ssc_depth -= 2;
 657                         else
 658                                 ssc_depth = RTS5228_SSC_DEPTH_8M;
 659                 } else if (div == CLK_DIV_8) {
 660                         if (ssc_depth > 3)
 661                                 ssc_depth -= 3;
 662                         else
 663                                 ssc_depth = RTS5228_SSC_DEPTH_8M;
 664                 }
 665         } else {
 666                 ssc_depth = 0;
 667         }
 668         pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
 669
 670         rtsx_pci_init_cmd(pcr);
 671         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
 672                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
 673         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
 674                         0xFF, (div << 4) | mcu_cnt);
 675         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
 676         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
 677                         SSC_DEPTH_MASK, ssc_depth);
 678         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
 679         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
 680         if (vpclk) {
 681                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
 682                                 PHASE_NOT_RESET, 0);
 683                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
 684                                 PHASE_NOT_RESET, 0);
 685                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
 686                                 PHASE_NOT_RESET, PHASE_NOT_RESET);
 687                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
 688                                 PHASE_NOT_RESET, PHASE_NOT_RESET);
 689         }
 690
 691         err = rtsx_pci_send_cmd(pcr, 2000);
 692         if (err < 0)
 693                 return err;
 694
 695         /* Wait SSC clock stable */
 696         udelay(SSC_CLOCK_STABLE_WAIT);
 697         err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
 698         if (err < 0)
 699                 return err;
 700
 701         pcr->cur_clock = clk;
 702         return 0;
 703
 704 }
 705
 706 void rts5228_init_params(struct rtsx_pcr *pcr)
 707 {
 708         struct rtsx_cr_option *option = &pcr->option;
 709         struct rtsx_hw_param *hw_param = &pcr->hw_param;
 710
 711         pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
 712         pcr->num_slots = 1;
 713         pcr->ops = &rts5228_pcr_ops;
 714
 715         pcr->flags = 0;
 716         pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
 717         pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
 718         pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
 719         pcr->aspm_en = ASPM_L1_EN;
 720         pcr->aspm_mode = ASPM_MODE_REG;
 721         pcr->tx_initial_phase = SET_CLOCK_PHASE(28, 27, 11);
 722         pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
 723
 724         pcr->ic_version = rts5228_get_ic_version(pcr);
 725         pcr->sd_pull_ctl_enable_tbl = rts5228_sd_pull_ctl_enable_tbl;
 726         pcr->sd_pull_ctl_disable_tbl = rts5228_sd_pull_ctl_disable_tbl;
 727
 728         pcr->reg_pm_ctrl3 = RTS5228_AUTOLOAD_CFG3;
 729
 730         option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
 731                                 | LTR_L1SS_PWR_GATE_EN);
 732         option->ltr_en = true;
 733
 734         /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
 735         option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
 736         option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
 737         option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
 738         option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
 739         option->ltr_l1off_sspwrgate = 0x7F;
 740         option->ltr_l1off_snooze_sspwrgate = 0x78;
 741
 742         option->ocp_en = 1;
 743         hw_param->interrupt_en |= SD_OC_INT_EN;
 744         hw_param->ocp_glitch =  SD_OCP_GLITCH_800U;
 745         option->sd_800mA_ocp_thd =  RTS5228_LDO1_OCP_THD_930;
 746 }