1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Driver for Realtek PCI-Express card reader
4 * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
7 * Ricky WU <ricky_wu@realtek.com>
8 * Rui FENG <rui_feng@realsil.com.cn>
9 * Wei WANG <wei_wang@realsil.com.cn>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/rtsx_pci.h>
19 static u8 rts5228_get_ic_version(struct rtsx_pcr *pcr)
23 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
24 return val & IC_VERSION_MASK;
27 static void rts5228_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
29 u8 driving_3v3[4][3] = {
35 u8 driving_1v8[4][3] = {
41 u8 (*driving)[3], drive_sel;
43 if (voltage == OUTPUT_3V3) {
44 driving = driving_3v3;
45 drive_sel = pcr->sd30_drive_sel_3v3;
47 driving = driving_1v8;
48 drive_sel = pcr->sd30_drive_sel_1v8;
51 rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
52 0xFF, driving[drive_sel][0]);
54 rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
55 0xFF, driving[drive_sel][1]);
57 rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
58 0xFF, driving[drive_sel][2]);
61 static void rtsx5228_fetch_vendor_settings(struct rtsx_pcr *pcr)
63 struct pci_dev *pdev = pcr->pci;
67 pci_read_config_dword(pdev, PCR_SETTING_REG1, ®);
68 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
70 if (!rtsx_vendor_setting_valid(reg)) {
71 pcr_dbg(pcr, "skip fetch vendor setting\n");
74 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
75 pcr->aspm_en = rtsx_reg_to_aspm(reg);
78 pci_read_config_dword(pdev, PCR_SETTING_REG2, ®);
79 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
81 pcr->rtd3_en = rtsx_reg_to_rtd3(reg);
82 if (rtsx_check_mmc_support(reg))
83 pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
84 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
85 if (rtsx_reg_check_reverse_socket(reg))
86 pcr->flags |= PCR_REVERSE_SOCKET;
89 static int rts5228_optimize_phy(struct rtsx_pcr *pcr)
91 return rtsx_pci_write_phy_register(pcr, 0x07, 0x8F40);
94 static void rts5228_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
96 /* Set relink_time to 0 */
97 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
98 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
99 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
100 RELINK_TIME_MASK, 0);
102 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
103 D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
106 rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1,
107 CD_RESUME_EN_MASK, 0);
108 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
109 rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL,
110 FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
113 rtsx_pci_write_register(pcr, FPDCTL,
114 SSC_POWER_DOWN, SSC_POWER_DOWN);
117 static int rts5228_enable_auto_blink(struct rtsx_pcr *pcr)
119 return rtsx_pci_write_register(pcr, OLT_LED_CTL,
120 LED_SHINE_MASK, LED_SHINE_EN);
123 static int rts5228_disable_auto_blink(struct rtsx_pcr *pcr)
125 return rtsx_pci_write_register(pcr, OLT_LED_CTL,
126 LED_SHINE_MASK, LED_SHINE_DISABLE);
129 static int rts5228_turn_on_led(struct rtsx_pcr *pcr)
131 return rtsx_pci_write_register(pcr, GPIO_CTL,
135 static int rts5228_turn_off_led(struct rtsx_pcr *pcr)
137 return rtsx_pci_write_register(pcr, GPIO_CTL,
141 /* SD Pull Control Enable:
142 * SD_DAT[3:0] ==> pull up
146 * SD_CLK ==> pull down
148 static const u32 rts5228_sd_pull_ctl_enable_tbl[] = {
149 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
150 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
154 /* SD Pull Control Disable:
155 * SD_DAT[3:0] ==> pull down
157 * SD_WP ==> pull down
158 * SD_CMD ==> pull down
159 * SD_CLK ==> pull down
161 static const u32 rts5228_sd_pull_ctl_disable_tbl[] = {
162 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
163 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
167 static int rts5228_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
169 rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
170 | SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
171 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
172 rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
173 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
174 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
179 static int rts5228_card_power_on(struct rtsx_pcr *pcr, int card)
181 struct rtsx_cr_option *option = &pcr->option;
184 rtsx_pci_enable_ocp(pcr);
186 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,
187 CFG_SD_POW_AUTO_PD, CFG_SD_POW_AUTO_PD);
189 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG1,
190 RTS5228_LDO1_TUNE_MASK, RTS5228_LDO1_33);
192 rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
193 RTS5228_LDO1_POWERON_MASK, RTS5228_LDO1_SOFTSTART);
195 rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
196 RTS5228_LDO1_POWERON_MASK, RTS5228_LDO1_FULLON);
199 rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
200 RTS5228_LDO3318_POWERON, RTS5228_LDO3318_POWERON);
204 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
206 /* Initialize SD_CFG1 register */
207 rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
208 SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1BIT);
210 rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
211 0xFF, SD20_RX_POS_EDGE);
212 rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
213 rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
214 SD_STOP | SD_CLR_ERR);
216 /* Reset SD_CFG3 register */
217 rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
218 rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
219 SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |
220 SD30_CLK_STOP_CFG0, 0);
222 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
223 pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
224 rts5228_sd_set_sample_push_timing_sd30(pcr);
229 static int rts5228_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
234 rtsx_pci_write_register(pcr, RTS5228_CARD_PWR_CTL,
235 RTS5228_PUPDC, RTS5228_PUPDC);
239 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
240 val |= PHY_TUNE_SDBUS_33;
241 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
245 rtsx_pci_write_register(pcr, RTS5228_DV3318_CFG,
246 RTS5228_DV3318_TUNE_MASK, RTS5228_DV3318_33);
247 rtsx_pci_write_register(pcr, SD_PAD_CTL,
251 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
252 val &= ~PHY_TUNE_SDBUS_33;
253 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
257 rtsx_pci_write_register(pcr, RTS5228_DV3318_CFG,
258 RTS5228_DV3318_TUNE_MASK, RTS5228_DV3318_18);
259 rtsx_pci_write_register(pcr, SD_PAD_CTL,
260 SD_IO_USING_1V8, SD_IO_USING_1V8);
267 rts5228_fill_driving(pcr, voltage);
272 static void rts5228_stop_cmd(struct rtsx_pcr *pcr)
274 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
275 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
276 rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
277 RTS5260_DMA_RST | RTS5260_ADMA3_RST,
278 RTS5260_DMA_RST | RTS5260_ADMA3_RST);
279 rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
282 static void rts5228_card_before_power_off(struct rtsx_pcr *pcr)
284 rts5228_stop_cmd(pcr);
285 rts5228_switch_output_voltage(pcr, OUTPUT_3V3);
288 static void rts5228_enable_ocp(struct rtsx_pcr *pcr)
292 val = SD_OCP_INT_EN | SD_DETECT_EN;
293 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
294 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
295 RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN,
296 RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN);
299 static void rts5228_disable_ocp(struct rtsx_pcr *pcr)
303 mask = SD_OCP_INT_EN | SD_DETECT_EN;
304 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
305 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
306 RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, 0);
309 static int rts5228_card_power_off(struct rtsx_pcr *pcr, int card)
313 rts5228_card_before_power_off(pcr);
314 err = rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
315 RTS5228_LDO_POWERON_MASK, 0);
316 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0, CFG_SD_POW_AUTO_PD, 0);
318 if (pcr->option.ocp_en)
319 rtsx_pci_disable_ocp(pcr);
324 static void rts5228_init_ocp(struct rtsx_pcr *pcr)
326 struct rtsx_cr_option *option = &pcr->option;
328 if (option->ocp_en) {
331 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
332 RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN,
333 RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN);
335 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
336 RTS5228_LDO1_OCP_THD_MASK, option->sd_800mA_ocp_thd);
338 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
339 RTS5228_LDO1_OCP_LMT_THD_MASK,
340 RTS5228_LDO1_LMT_THD_1500);
342 rtsx_pci_read_register(pcr, RTS5228_LDO1_CFG0, &val);
344 mask = SD_OCP_GLITCH_MASK;
345 val = pcr->hw_param.ocp_glitch;
346 rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
348 rts5228_enable_ocp(pcr);
351 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
352 RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, 0);
356 static void rts5228_clear_ocpstat(struct rtsx_pcr *pcr)
361 mask = SD_OCP_INT_CLR | SD_OC_CLR;
362 val = SD_OCP_INT_CLR | SD_OC_CLR;
364 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
367 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
371 static void rts5228_process_ocp(struct rtsx_pcr *pcr)
373 if (!pcr->option.ocp_en)
376 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
378 if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
379 rts5228_clear_ocpstat(pcr);
380 rts5228_card_power_off(pcr, RTSX_SD_CARD);
381 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
387 static void rts5228_init_from_cfg(struct rtsx_pcr *pcr)
389 struct pci_dev *pdev = pcr->pci;
392 struct rtsx_cr_option *option = &pcr->option;
394 l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
398 pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
400 if (0 == (lval & 0x0F))
401 rtsx_pci_enable_oobs_polling(pcr);
403 rtsx_pci_disable_oobs_polling(pcr);
405 if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
406 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
408 rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
410 if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
411 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
413 rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
415 if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
416 rtsx_set_dev_flag(pcr, PM_L1_1_EN);
418 rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
420 if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
421 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
423 rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
425 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
426 if (option->ltr_en) {
429 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
430 if (val & PCI_EXP_DEVCTL2_LTR_EN) {
431 option->ltr_enabled = true;
432 option->ltr_active = true;
433 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
435 option->ltr_enabled = false;
439 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
440 | PM_L1_1_EN | PM_L1_2_EN))
441 option->force_clkreq_0 = false;
443 option->force_clkreq_0 = true;
446 static int rts5228_extra_init_hw(struct rtsx_pcr *pcr)
448 struct rtsx_cr_option *option = &pcr->option;
450 rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1,
451 CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
453 rts5228_init_from_cfg(pcr);
455 rtsx_pci_write_register(pcr, L1SUB_CONFIG1,
456 AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE);
457 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);
459 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
460 FUNC_FORCE_UPME_XMT_DBG, FUNC_FORCE_UPME_XMT_DBG);
462 rtsx_pci_write_register(pcr, PCLK_CTL,
463 PCLK_MODE_SEL, PCLK_MODE_SEL);
465 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
466 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN);
468 /* LED shine disabled, set initial shine cycle period */
469 rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);
471 /* Configure driving */
472 rts5228_fill_driving(pcr, OUTPUT_3V3);
474 if (pcr->flags & PCR_REVERSE_SOCKET)
475 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30);
477 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);
480 * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
481 * to drive low, and we forcibly request clock.
483 if (option->force_clkreq_0)
484 rtsx_pci_write_register(pcr, PETXCFG,
485 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
487 rtsx_pci_write_register(pcr, PETXCFG,
488 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
490 rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB);
493 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x01);
494 rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL,
495 FORCE_PM_CONTROL | FORCE_PM_VALUE,
496 FORCE_PM_CONTROL | FORCE_PM_VALUE);
498 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
499 rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL,
500 FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
502 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, D3_DELINK_MODE_EN, 0x00);
507 static void rts5228_enable_aspm(struct rtsx_pcr *pcr, bool enable)
511 if (pcr->aspm_enabled == enable)
514 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
515 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
516 val |= (pcr->aspm_en & 0x02);
517 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
518 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
519 PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en);
520 pcr->aspm_enabled = enable;
523 static void rts5228_disable_aspm(struct rtsx_pcr *pcr, bool enable)
527 if (pcr->aspm_enabled == enable)
530 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
531 PCI_EXP_LNKCTL_ASPMC, 0);
532 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
533 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
534 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
535 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
537 pcr->aspm_enabled = enable;
540 static void rts5228_set_aspm(struct rtsx_pcr *pcr, bool enable)
543 rts5228_enable_aspm(pcr, true);
545 rts5228_disable_aspm(pcr, false);
548 static void rts5228_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
550 struct rtsx_cr_option *option = &pcr->option;
551 int aspm_L1_1, aspm_L1_2;
554 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
555 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
558 /* run, latency: 60us */
560 val = option->ltr_l1off_snooze_sspwrgate;
562 /* l1off, latency: 300us */
564 val = option->ltr_l1off_sspwrgate;
567 rtsx_set_l1off_sub(pcr, val);
570 static const struct pcr_ops rts5228_pcr_ops = {
571 .fetch_vendor_settings = rtsx5228_fetch_vendor_settings,
572 .turn_on_led = rts5228_turn_on_led,
573 .turn_off_led = rts5228_turn_off_led,
574 .extra_init_hw = rts5228_extra_init_hw,
575 .enable_auto_blink = rts5228_enable_auto_blink,
576 .disable_auto_blink = rts5228_disable_auto_blink,
577 .card_power_on = rts5228_card_power_on,
578 .card_power_off = rts5228_card_power_off,
579 .switch_output_voltage = rts5228_switch_output_voltage,
580 .force_power_down = rts5228_force_power_down,
581 .stop_cmd = rts5228_stop_cmd,
582 .set_aspm = rts5228_set_aspm,
583 .set_l1off_cfg_sub_d0 = rts5228_set_l1off_cfg_sub_d0,
584 .enable_ocp = rts5228_enable_ocp,
585 .disable_ocp = rts5228_disable_ocp,
586 .init_ocp = rts5228_init_ocp,
587 .process_ocp = rts5228_process_ocp,
588 .clear_ocpstat = rts5228_clear_ocpstat,
589 .optimize_phy = rts5228_optimize_phy,
593 static inline u8 double_ssc_depth(u8 depth)
595 return ((depth > 1) ? (depth - 1) : depth);
598 int rts5228_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
599 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
603 u8 clk_divider, mcu_cnt, div;
604 static const u8 depth[] = {
605 [RTSX_SSC_DEPTH_4M] = RTS5228_SSC_DEPTH_4M,
606 [RTSX_SSC_DEPTH_2M] = RTS5228_SSC_DEPTH_2M,
607 [RTSX_SSC_DEPTH_1M] = RTS5228_SSC_DEPTH_1M,
608 [RTSX_SSC_DEPTH_500K] = RTS5228_SSC_DEPTH_512K,
612 /* We use 250k(around) here, in initial stage */
613 clk_divider = SD_CLK_DIVIDE_128;
614 card_clock = 30000000;
616 clk_divider = SD_CLK_DIVIDE_0;
618 err = rtsx_pci_write_register(pcr, SD_CFG1,
619 SD_CLK_DIVIDE_MASK, clk_divider);
623 card_clock /= 1000000;
624 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
627 if (!initial_mode && double_clk)
628 clk = card_clock * 2;
629 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
630 clk, pcr->cur_clock);
632 if (clk == pcr->cur_clock)
635 if (pcr->ops->conv_clk_and_div_n)
636 n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
639 if ((clk <= 4) || (n > 396))
642 mcu_cnt = 125/clk + 3;
647 while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) {
648 if (pcr->ops->conv_clk_and_div_n) {
649 int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
651 n = pcr->ops->conv_clk_and_div_n(dbl_clk,
660 pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
662 ssc_depth = depth[ssc_depth];
664 ssc_depth = double_ssc_depth(ssc_depth);
667 if (div == CLK_DIV_2) {
671 ssc_depth = RTS5228_SSC_DEPTH_8M;
672 } else if (div == CLK_DIV_4) {
676 ssc_depth = RTS5228_SSC_DEPTH_8M;
677 } else if (div == CLK_DIV_8) {
681 ssc_depth = RTS5228_SSC_DEPTH_8M;
686 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
688 rtsx_pci_init_cmd(pcr);
689 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
690 CLK_LOW_FREQ, CLK_LOW_FREQ);
691 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
692 0xFF, (div << 4) | mcu_cnt);
693 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
694 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
695 SSC_DEPTH_MASK, ssc_depth);
696 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
697 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
699 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
701 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
703 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
704 PHASE_NOT_RESET, PHASE_NOT_RESET);
705 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
706 PHASE_NOT_RESET, PHASE_NOT_RESET);
709 err = rtsx_pci_send_cmd(pcr, 2000);
713 /* Wait SSC clock stable */
714 udelay(SSC_CLOCK_STABLE_WAIT);
715 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
719 pcr->cur_clock = clk;
724 void rts5228_init_params(struct rtsx_pcr *pcr)
726 struct rtsx_cr_option *option = &pcr->option;
727 struct rtsx_hw_param *hw_param = &pcr->hw_param;
729 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
731 pcr->ops = &rts5228_pcr_ops;
734 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
735 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
736 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
737 pcr->aspm_en = ASPM_L1_EN;
738 pcr->aspm_mode = ASPM_MODE_REG;
739 pcr->tx_initial_phase = SET_CLOCK_PHASE(28, 27, 11);
740 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
742 pcr->ic_version = rts5228_get_ic_version(pcr);
743 pcr->sd_pull_ctl_enable_tbl = rts5228_sd_pull_ctl_enable_tbl;
744 pcr->sd_pull_ctl_disable_tbl = rts5228_sd_pull_ctl_disable_tbl;
746 pcr->reg_pm_ctrl3 = RTS5228_AUTOLOAD_CFG3;
748 option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
749 | LTR_L1SS_PWR_GATE_EN);
750 option->ltr_en = true;
752 /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
753 option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
754 option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
755 option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
756 option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
757 option->ltr_l1off_sspwrgate = 0x7F;
758 option->ltr_l1off_snooze_sspwrgate = 0x78;
761 hw_param->interrupt_en |= SD_OC_INT_EN;
762 hw_param->ocp_glitch = SD_OCP_GLITCH_800U;
763 option->sd_800mA_ocp_thd = RTS5228_LDO1_OCP_THD_930;