2 # Multifunction miscellaneous devices
5 menu "Multifunction device drivers"
8 bool "Enable Driver Model for Misc drivers"
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
17 bool "Enable Driver Model for Misc drivers in SPL"
20 Enable driver model for miscellaneous devices. This class is
21 used only for those do not fit other more general classes. A
22 set of generic read, write and ioctl methods may be used to
26 bool "Enable Driver Model for Misc drivers in TPL"
29 Enable driver model for miscellaneous devices. This class is
30 used only for those do not fit other more general classes. A
31 set of generic read, write and ioctl methods may be used to
35 bool "Altera Sysid support"
38 Select this to enable a sysid for Altera devices. Please find
39 details on the "Embedded Peripherals IP User Guide" of Altera.
42 bool "Support for Atmel ATSHA204A module"
45 Enable support for I2C connected Atmel's ATSHA204A
46 CryptoAuthentication module found for example on the Turris Omnia
50 bool "Gateworks System Controller Support"
53 Enable access for the Gateworks System Controller used on Gateworks
54 boards to provide a boot watchdog, power control, temperature monitor,
55 voltage ADCs, and EEPROM.
58 bool "Rockchip e-fuse support"
61 Enable (read-only) access for the e-fuse block found in Rockchip
62 SoCs: accesses can either be made using byte addressing and a length
63 or through child-nodes that are generated based on the e-fuse map
64 retrieved from the DTS.
66 This driver currently supports the RK3399 only, but can easily be
67 extended (by porting the read function from the Linux kernel sources)
68 to support other recent Rockchip devices.
71 bool "Rockchip OTP Support"
74 Enable (read-only) access for the one-time-programmable memory block
75 found in Rockchip SoCs: accesses can either be made using byte
76 addressing and a length or through child-nodes that are generated
77 based on the e-fuse map retrieved from the DTS.
80 bool "SiFive eMemory OTP driver"
83 Enable support for reading and writing the eMemory OTP on the
86 config VEXPRESS_CONFIG
87 bool "Enable support for Arm Versatile Express config bus"
90 If you say Y here, you will get support for accessing the
91 configuration bus on the Arm Versatile Express boards via
95 bool "Enable crosec command"
98 Enable command-line access to the Chrome OS EC (Embedded
99 Controller). This provides the 'crosec' command which has
100 a number of sub-commands for performing EC tasks such as
101 updating its flash, accessing a small saved context area
102 and talking to the I2C bus behind the EC (if there is one).
105 bool "Enable Chrome OS EC"
107 Enable access to the Chrome OS EC. This is a separate
108 microcontroller typically available on a SPI bus on Chromebooks. It
109 provides access to the keyboard, some internal storage and may
110 control access to the battery and main PMIC depending on the
111 device. You can use the 'crosec' command to access it.
114 bool "Enable Chrome OS EC in SPL"
117 Enable access to the Chrome OS EC in SPL. This is a separate
118 microcontroller typically available on a SPI bus on Chromebooks. It
119 provides access to the keyboard, some internal storage and may
120 control access to the battery and main PMIC depending on the
121 device. You can use the 'crosec' command to access it.
124 bool "Enable Chrome OS EC in TPL"
127 Enable access to the Chrome OS EC in TPL. This is a separate
128 microcontroller typically available on a SPI bus on Chromebooks. It
129 provides access to the keyboard, some internal storage and may
130 control access to the battery and main PMIC depending on the
131 device. You can use the 'crosec' command to access it.
134 bool "Enable Chrome OS EC I2C driver"
137 Enable I2C access to the Chrome OS EC. This is used on older
138 ARM Chromebooks such as snow and spring before the standard bus
139 changed to SPI. The EC will accept commands across the I2C using
140 a special message protocol, and provide responses.
143 bool "Enable Chrome OS EC LPC driver"
146 Enable I2C access to the Chrome OS EC. This is used on x86
147 Chromebooks such as link and falco. The keyboard is provided
148 through a legacy port interface, so on x86 machines the main
149 function of the EC is power and thermal management.
151 config SPL_CROS_EC_LPC
152 bool "Enable Chrome OS EC LPC driver in SPL"
155 Enable I2C access to the Chrome OS EC. This is used on x86
156 Chromebooks such as link and falco. The keyboard is provided
157 through a legacy port interface, so on x86 machines the main
158 function of the EC is power and thermal management.
160 config TPL_CROS_EC_LPC
161 bool "Enable Chrome OS EC LPC driver in TPL"
164 Enable I2C access to the Chrome OS EC. This is used on x86
165 Chromebooks such as link and falco. The keyboard is provided
166 through a legacy port interface, so on x86 machines the main
167 function of the EC is power and thermal management.
169 config CROS_EC_SANDBOX
170 bool "Enable Chrome OS EC sandbox driver"
171 depends on CROS_EC && SANDBOX
173 Enable a sandbox emulation of the Chrome OS EC. This supports
174 keyboard (use the -l flag to enable the LCD), verified boot context,
175 EC flash read/write/erase support and a few other things. It is
176 enough to perform a Chrome OS verified boot on sandbox.
178 config SPL_CROS_EC_SANDBOX
179 bool "Enable Chrome OS EC sandbox driver in SPL"
180 depends on SPL_CROS_EC && SANDBOX
182 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
183 keyboard (use the -l flag to enable the LCD), verified boot context,
184 EC flash read/write/erase support and a few other things. It is
185 enough to perform a Chrome OS verified boot on sandbox.
187 config TPL_CROS_EC_SANDBOX
188 bool "Enable Chrome OS EC sandbox driver in TPL"
189 depends on TPL_CROS_EC && SANDBOX
191 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
192 keyboard (use the -l flag to enable the LCD), verified boot context,
193 EC flash read/write/erase support and a few other things. It is
194 enough to perform a Chrome OS verified boot on sandbox.
197 bool "Enable Chrome OS EC SPI driver"
200 Enable SPI access to the Chrome OS EC. This is used on newer
201 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
202 provides a faster and more robust interface than I2C but the bugs
203 are less interesting.
206 bool "Enable support for DS4510 CPU supervisor"
208 Enable support for the Maxim DS4510 CPU supervisor. It has an
209 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
210 and a configurable timer for the supervisor function. The device is
214 bool "Enable FSL SEC_MON Driver"
216 Freescale Security Monitor block is responsible for monitoring
218 Security Monitor can be transitioned on any security failures,
219 like software violations or hardware security violations.
222 bool "Interrupt controller"
224 This enables support for interrupt controllers, including ITSS.
225 Some devices have extra features, such as Apollo Lake. The
226 device has its own uclass since there are several operations
230 bool "Ingenic JZ4780 eFUSE support"
231 depends on ARCH_JZ47XX
233 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
236 bool "Enable MXC OCOTP Driver"
237 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
240 If you say Y here, you will get support for the One Time
241 Programmable memory pages that are stored on the some
242 Freescale i.MX processors.
245 bool "Enable MXC OCOTP driver in SPL"
246 depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
249 If you say Y here, you will get support for the One Time
250 Programmable memory pages, that are stored on some
251 Freescale i.MX processors, in SPL.
253 config NUVOTON_NCT6102D
254 bool "Enable Nuvoton NCT6102D Super I/O driver"
256 If you say Y here, you will get support for the Nuvoton
257 NCT6102D Super I/O driver. This can be used to enable or
258 disable the legacy UART, the watchdog or other devices
259 in the Nuvoton Super IO chips on X86 platforms.
262 bool "Intel Primary to Sideband Bridge"
263 depends on X86 || SANDBOX
265 This enables support for the Intel Primary to Sideband Bridge,
266 abbreviated to P2SB. The P2SB is used to access various peripherals
267 such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
268 space. The space is segmented into different channels and peripherals
269 are accessed by device-specific means within those channels. Devices
270 should be added in the device tree as subnodes of the P2SB. A
271 Peripheral Channel Register? (PCR) API is provided to access those
272 devices - see pcr_readl(), etc.
275 bool "Intel Primary to Sideband Bridge in SPL"
276 depends on SPL && (X86 || SANDBOX)
278 The Primary to Sideband Bridge is used to access various peripherals
279 through memory-mapped I/O in a large chunk of PCI space. The space is
280 segmented into different channels and peripherals are accessed by
281 device-specific means within those channels. Devices should be added
282 in the device tree as subnodes of the p2sb.
285 bool "Intel Primary to Sideband Bridge in TPL"
286 depends on TPL && (X86 || SANDBOX)
288 The Primary to Sideband Bridge is used to access various peripherals
289 through memory-mapped I/O in a large chunk of PCI space. The space is
290 segmented into different channels and peripherals are accessed by
291 device-specific means within those channels. Devices should be added
292 in the device tree as subnodes of the p2sb.
295 bool "Enable power-sequencing drivers"
298 Power-sequencing drivers provide support for controlling power for
299 devices. They are typically referenced by a phandle from another
300 device. When the device is started up, its power sequence can be
304 bool "Enable power-sequencing drivers for SPL"
307 Power-sequencing drivers provide support for controlling power for
308 devices. They are typically referenced by a phandle from another
309 device. When the device is started up, its power sequence can be
313 bool "Enable PCA9551 LED driver"
315 Enable driver for PCA9551 LED controller. This controller
316 is connected via I2C. So I2C needs to be enabled.
318 config PCA9551_I2C_ADDR
319 hex "I2C address of PCA9551 LED controller"
320 depends on PCA9551_LED
323 The I2C address of the PCA9551 LED controller.
326 bool "Enable STM32MP fuse wrapper providing the fuse API"
327 depends on ARCH_STM32MP && MISC
328 default y if CMD_FUSE
330 If you say Y here, you will get support for the fuse API (OTP)
331 for STM32MP architecture.
332 This API is needed for CMD_FUSE.
335 bool "Enable RCC driver for the STM32 SoC's family"
336 depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
338 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
339 block) is responsible of the management of the clock and reset
341 This driver is similar to an MFD driver in the Linux kernel.
344 bool "Enable support for the Tegra CAR driver"
345 depends on TEGRA_NO_BPMP
347 The Tegra CAR (Clock and Reset Controller) is a HW module that
348 controls almost all clocks and resets in a Tegra SoC.
351 bool "Enable support for the Tegra186 BPMP driver"
354 The Tegra BPMP (Boot and Power Management Processor) is a separate
355 auxiliary CPU embedded into Tegra to perform power management work,
356 and controls related features such as clocks, resets, power domains,
357 PMIC I2C bus, etc. This driver provides the core low-level
358 communication path by which feature-specific drivers (such as clock)
359 can make requests to the BPMP. This driver is similar to an MFD
360 driver in the Linux kernel.
363 bool "Enable support for test drivers"
366 This enables drivers and uclasses that provides a way of testing the
367 operations of memory allocation and driver/uclass methods in driver
368 model. This should only be enabled for testing as it is not useful for
372 bool "Enable TWL4030 LED controller"
374 Enable this to add support for the TWL4030 LED controller.
376 config WINBOND_W83627
377 bool "Enable Winbond Super I/O driver"
379 If you say Y here, you will get support for the Winbond
380 W83627 Super I/O driver. This can be used to enable the
381 legacy UART or other devices in the Winbond Super IO chips
387 Hidden option to enable QEMU fw_cfg interface and uclass. This will
388 be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
394 Hidden option to enable PIO QEMU fw_cfg interface. This will be
395 selected by the appropriate QEMU board.
401 Hidden option to enable MMIO QEMU fw_cfg interface. This will be
402 selected by the appropriate QEMU board.
405 bool "Enable driver for generic I2C-attached EEPROMs"
408 Enable a generic driver for EEPROMs attached via I2C.
411 config SPL_I2C_EEPROM
412 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
413 depends on MISC && SPL && SPL_DM
415 This option is an SPL-variant of the I2C_EEPROM option.
416 See the help of I2C_EEPROM for details.
418 config SYS_I2C_EEPROM_ADDR
419 hex "Chip address of the EEPROM device"
420 depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
425 config SYS_I2C_EEPROM_ADDR_OVERFLOW
426 hex "EEPROM Address Overflow"
429 EEPROM chips that implement "address overflow" are ones
430 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
431 address and the extra bits end up in the "chip address" bit
432 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
437 config GDSYS_RXAUI_CTRL
438 bool "Enable gdsys RXAUI control driver"
441 Support gdsys FPGA's RXAUI control.
444 bool "Enable gdsys IOEP driver"
447 Support gdsys FPGA's IO endpoint driver.
449 config MPC83XX_SERDES
450 bool "Enable MPC83xx serdes driver"
453 Support for serdes found on MPC83xx SoCs.
456 bool "Enable loader driver for file system"
458 This is file system generic loader which can be used to load
459 the file image from the storage into target such as memory.
461 The consumer driver would then use this loader to program whatever,
465 bool "Enable loader driver for file system"
467 This is file system generic loader which can be used to load
468 the file image from the storage into target such as memory.
470 The consumer driver would then use this loader to program whatever,
474 bool "Enable gdsys SOC driver"
477 Support for gdsys IHS SOC, a simple bus associated with each gdsys
478 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
479 register maps are contained within the FPGA's register map.
482 bool "Enable IHS FPGA driver"
485 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
486 gdsys devices, which supply the majority of the functionality offered
487 by the devices. This driver supports both CON and CPU variants of the
488 devices, depending on the device tree entry.
490 bool "Enable K3 ESM driver"
493 Support ESM (Error Signaling Module) on TI K3 SoCs.
495 config MICROCHIP_FLEXCOM
496 bool "Enable Microchip Flexcom driver"
499 The Atmel Flexcom is just a wrapper which embeds a SPI controller,
500 an I2C controller and an USART.
501 Only one function can be used at a time and is chosen at boot time
502 according to the device tree.
505 depends on ARCH_K3 && SPL_DM_REGULATOR
506 bool "AVS class 0 support for K3 devices"
508 K3 devices have the optimized voltage values for the main voltage
509 domains stored in efuse within the VTM IP. This driver reads the
510 optimized voltage from the efuse, so that it can be programmed
511 to the PMIC on board.
514 bool "Enable PMIC ESM driver"
517 Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
518 typically to reboot the board in error condition.
524 bool "Enable Kontron sl28cpld multi-function driver"
527 Support for the Kontron sl28cpld management controller. This is
528 the base driver which provides common access methods for the