2 # Multifunction miscellaneous devices
5 menu "Multifunction device drivers"
8 bool "Enable Driver Model for Misc drivers"
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
17 bool "Altera Sysid support"
20 Select this to enable a sysid for Altera devices. Please find
21 details on the "Embedded Peripherals IP User Guide" of Altera.
24 bool "Support for Atmel ATSHA204A module"
27 Enable support for I2C connected Atmel's ATSHA204A
28 CryptoAuthentication module found for example on the Turris Omnia
32 bool "Rockchip e-fuse support"
35 Enable (read-only) access for the e-fuse block found in Rockchip
36 SoCs: accesses can either be made using byte addressing and a length
37 or through child-nodes that are generated based on the e-fuse map
38 retrieved from the DTS.
40 This driver currently supports the RK3399 only, but can easily be
41 extended (by porting the read function from the Linux kernel sources)
42 to support other recent Rockchip devices.
44 config VEXPRESS_CONFIG
45 bool "Enable support for Arm Versatile Express config bus"
48 If you say Y here, you will get support for accessing the
49 configuration bus on the Arm Versatile Express boards via
53 bool "Enable crosec command"
56 Enable command-line access to the Chrome OS EC (Embedded
57 Controller). This provides the 'crosec' command which has
58 a number of sub-commands for performing EC tasks such as
59 updating its flash, accessing a small saved context area
60 and talking to the I2C bus behind the EC (if there is one).
63 bool "Enable Chrome OS EC"
65 Enable access to the Chrome OS EC. This is a separate
66 microcontroller typically available on a SPI bus on Chromebooks. It
67 provides access to the keyboard, some internal storage and may
68 control access to the battery and main PMIC depending on the
69 device. You can use the 'crosec' command to access it.
72 bool "Enable Chrome OS EC I2C driver"
75 Enable I2C access to the Chrome OS EC. This is used on older
76 ARM Chromebooks such as snow and spring before the standard bus
77 changed to SPI. The EC will accept commands across the I2C using
78 a special message protocol, and provide responses.
81 bool "Enable Chrome OS EC LPC driver"
84 Enable I2C access to the Chrome OS EC. This is used on x86
85 Chromebooks such as link and falco. The keyboard is provided
86 through a legacy port interface, so on x86 machines the main
87 function of the EC is power and thermal management.
89 config CROS_EC_SANDBOX
90 bool "Enable Chrome OS EC sandbox driver"
91 depends on CROS_EC && SANDBOX
93 Enable a sandbox emulation of the Chrome OS EC. This supports
94 keyboard (use the -l flag to enable the LCD), verified boot context,
95 EC flash read/write/erase support and a few other things. It is
96 enough to perform a Chrome OS verified boot on sandbox.
99 bool "Enable Chrome OS EC SPI driver"
102 Enable SPI access to the Chrome OS EC. This is used on newer
103 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
104 provides a faster and more robust interface than I2C but the bugs
105 are less interesting.
108 bool "Enable support for DS4510 CPU supervisor"
110 Enable support for the Maxim DS4510 CPU supervisor. It has an
111 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
112 and a configurable timer for the supervisor function. The device is
116 bool "Enable FSL SEC_MON Driver"
118 Freescale Security Monitor block is responsible for monitoring
120 Security Monitor can be transitioned on any security failures,
121 like software violations or hardware security violations.
124 bool "Ingenic JZ4780 eFUSE support"
125 depends on ARCH_JZ47XX
127 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
130 bool "Enable MXC OCOTP Driver"
131 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_VF610
134 If you say Y here, you will get support for the One Time
135 Programmable memory pages that are stored on the some
136 Freescale i.MX processors.
138 config NUVOTON_NCT6102D
139 bool "Enable Nuvoton NCT6102D Super I/O driver"
141 If you say Y here, you will get support for the Nuvoton
142 NCT6102D Super I/O driver. This can be used to enable or
143 disable the legacy UART, the watchdog or other devices
144 in the Nuvoton Super IO chips on X86 platforms.
147 bool "Enable power-sequencing drivers"
150 Power-sequencing drivers provide support for controlling power for
151 devices. They are typically referenced by a phandle from another
152 device. When the device is started up, its power sequence can be
156 bool "Enable power-sequencing drivers for SPL"
159 Power-sequencing drivers provide support for controlling power for
160 devices. They are typically referenced by a phandle from another
161 device. When the device is started up, its power sequence can be
165 bool "Enable PCA9551 LED driver"
167 Enable driver for PCA9551 LED controller. This controller
168 is connected via I2C. So I2C needs to be enabled.
170 config PCA9551_I2C_ADDR
171 hex "I2C address of PCA9551 LED controller"
172 depends on PCA9551_LED
175 The I2C address of the PCA9551 LED controller.
178 bool "Enable STM32MP fuse wrapper providing the fuse API"
179 depends on ARCH_STM32MP && MISC
180 default y if CMD_FUSE
182 If you say Y here, you will get support for the fuse API (OTP)
183 for STM32MP architecture.
184 This API is needed for CMD_FUSE.
187 bool "Enable RCC driver for the STM32 SoC's family"
188 depends on (STM32 || ARCH_STM32MP) && MISC
190 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
191 block) is responsible of the management of the clock and reset
193 This driver is similar to an MFD driver in the Linux kernel.
196 bool "Enable support for the Tegra CAR driver"
197 depends on TEGRA_NO_BPMP
199 The Tegra CAR (Clock and Reset Controller) is a HW module that
200 controls almost all clocks and resets in a Tegra SoC.
203 bool "Enable support for the Tegra186 BPMP driver"
206 The Tegra BPMP (Boot and Power Management Processor) is a separate
207 auxiliary CPU embedded into Tegra to perform power management work,
208 and controls related features such as clocks, resets, power domains,
209 PMIC I2C bus, etc. This driver provides the core low-level
210 communication path by which feature-specific drivers (such as clock)
211 can make requests to the BPMP. This driver is similar to an MFD
212 driver in the Linux kernel.
215 bool "Enable TWL4030 LED controller"
217 Enable this to add support for the TWL4030 LED controller.
219 config WINBOND_W83627
220 bool "Enable Winbond Super I/O driver"
222 If you say Y here, you will get support for the Winbond
223 W83627 Super I/O driver. This can be used to enable the
224 legacy UART or other devices in the Winbond Super IO chips
230 Hidden option to enable QEMU fw_cfg interface. This will be selected by
231 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
234 bool "Enable driver for generic I2C-attached EEPROMs"
237 Enable a generic driver for EEPROMs attached via I2C.
240 config SPL_I2C_EEPROM
241 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
242 depends on MISC && SPL && SPL_DM
244 This option is an SPL-variant of the I2C_EEPROM option.
245 See the help of I2C_EEPROM for details.
247 config ZYNQ_GEM_I2C_MAC_OFFSET
248 hex "Set the I2C MAC offset"
252 Set the MAC offset for i2C.
256 config SYS_I2C_EEPROM_ADDR
257 hex "Chip address of the EEPROM device"
260 config SYS_I2C_EEPROM_BUS
261 int "I2C bus of the EEPROM device."
264 config SYS_EEPROM_SIZE
265 int "Size in bytes of the EEPROM device"
268 config SYS_EEPROM_PAGE_WRITE_BITS
269 int "Number of bits used to address bytes in a single page"
272 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
273 A 64 byte page, for example would require six bits.
275 config SYS_EEPROM_PAGE_WRITE_DELAY_MS
276 int "Number of milliseconds to delay between page writes"
279 config SYS_I2C_EEPROM_ADDR_LEN
280 int "Length in bytes of the EEPROM memory array address"
283 Note: This is NOT the chip address length!
285 config SYS_I2C_EEPROM_ADDR_OVERFLOW
286 hex "EEPROM Address Overflow"
289 EEPROM chips that implement "address overflow" are ones
290 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
291 address and the extra bits end up in the "chip address" bit
292 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
297 config GDSYS_RXAUI_CTRL
298 bool "Enable gdsys RXAUI control driver"
301 Support gdsys FPGA's RXAUI control.
304 bool "Enable gdsys IOEP driver"
307 Support gdsys FPGA's IO endpoint driver.
309 config MPC83XX_SERDES
310 bool "Enable MPC83xx serdes driver"
313 Support for serdes found on MPC83xx SoCs.
316 bool "Enable loader driver for file system"
318 This is file system generic loader which can be used to load
319 the file image from the storage into target such as memory.
321 The consumer driver would then use this loader to program whatever,
325 bool "Enable gdsys SOC driver"
328 Support for gdsys IHS SOC, a simple bus associated with each gdsys
329 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
330 register maps are contained within the FPGA's register map.
333 bool "Enable IHS FPGA driver"
336 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
337 gdsys devices, which supply the majority of the functionality offered
338 by the devices. This driver supports both CON and CPU variants of the
339 devices, depending on the device tree entry.