2 # Multifunction miscellaneous devices
5 menu "Multifunction device drivers"
8 bool "Enable Driver Model for Misc drivers"
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
17 bool "Enable Driver Model for Misc drivers in SPL"
20 Enable driver model for miscellaneous devices. This class is
21 used only for those do not fit other more general classes. A
22 set of generic read, write and ioctl methods may be used to
26 bool "Enable Driver Model for Misc drivers in TPL"
29 Enable driver model for miscellaneous devices. This class is
30 used only for those do not fit other more general classes. A
31 set of generic read, write and ioctl methods may be used to
35 bool "Altera Sysid support"
38 Select this to enable a sysid for Altera devices. Please find
39 details on the "Embedded Peripherals IP User Guide" of Altera.
42 bool "Support for Atmel ATSHA204A module"
46 Enable support for I2C connected Atmel's ATSHA204A
47 CryptoAuthentication module found for example on the Turris Omnia
51 bool "Gateworks System Controller Support"
54 Enable access for the Gateworks System Controller used on Gateworks
55 boards to provide a boot watchdog, power control, temperature monitor,
56 voltage ADCs, and EEPROM.
59 bool "Rockchip e-fuse support"
62 Enable (read-only) access for the e-fuse block found in Rockchip
63 SoCs: accesses can either be made using byte addressing and a length
64 or through child-nodes that are generated based on the e-fuse map
65 retrieved from the DTS.
67 This driver currently supports the RK3399 only, but can easily be
68 extended (by porting the read function from the Linux kernel sources)
69 to support other recent Rockchip devices.
72 bool "Rockchip OTP Support"
75 Enable (read-only) access for the one-time-programmable memory block
76 found in Rockchip SoCs: accesses can either be made using byte
77 addressing and a length or through child-nodes that are generated
78 based on the e-fuse map retrieved from the DTS.
81 bool "SiFive eMemory OTP driver"
84 Enable support for reading and writing the eMemory OTP on the
87 config VEXPRESS_CONFIG
88 bool "Enable support for Arm Versatile Express config bus"
91 If you say Y here, you will get support for accessing the
92 configuration bus on the Arm Versatile Express boards via
96 bool "Enable crosec command"
99 Enable command-line access to the Chrome OS EC (Embedded
100 Controller). This provides the 'crosec' command which has
101 a number of sub-commands for performing EC tasks such as
102 updating its flash, accessing a small saved context area
103 and talking to the I2C bus behind the EC (if there is one).
106 bool "Enable Chrome OS EC"
108 Enable access to the Chrome OS EC. This is a separate
109 microcontroller typically available on a SPI bus on Chromebooks. It
110 provides access to the keyboard, some internal storage and may
111 control access to the battery and main PMIC depending on the
112 device. You can use the 'crosec' command to access it.
115 bool "Enable Chrome OS EC in SPL"
118 Enable access to the Chrome OS EC in SPL. This is a separate
119 microcontroller typically available on a SPI bus on Chromebooks. It
120 provides access to the keyboard, some internal storage and may
121 control access to the battery and main PMIC depending on the
122 device. You can use the 'crosec' command to access it.
125 bool "Enable Chrome OS EC in TPL"
128 Enable access to the Chrome OS EC in TPL. This is a separate
129 microcontroller typically available on a SPI bus on Chromebooks. It
130 provides access to the keyboard, some internal storage and may
131 control access to the battery and main PMIC depending on the
132 device. You can use the 'crosec' command to access it.
135 bool "Enable Chrome OS EC I2C driver"
138 Enable I2C access to the Chrome OS EC. This is used on older
139 ARM Chromebooks such as snow and spring before the standard bus
140 changed to SPI. The EC will accept commands across the I2C using
141 a special message protocol, and provide responses.
144 bool "Enable Chrome OS EC LPC driver"
147 Enable I2C access to the Chrome OS EC. This is used on x86
148 Chromebooks such as link and falco. The keyboard is provided
149 through a legacy port interface, so on x86 machines the main
150 function of the EC is power and thermal management.
152 config SPL_CROS_EC_LPC
153 bool "Enable Chrome OS EC LPC driver in SPL"
156 Enable I2C access to the Chrome OS EC. This is used on x86
157 Chromebooks such as link and falco. The keyboard is provided
158 through a legacy port interface, so on x86 machines the main
159 function of the EC is power and thermal management.
161 config TPL_CROS_EC_LPC
162 bool "Enable Chrome OS EC LPC driver in TPL"
165 Enable I2C access to the Chrome OS EC. This is used on x86
166 Chromebooks such as link and falco. The keyboard is provided
167 through a legacy port interface, so on x86 machines the main
168 function of the EC is power and thermal management.
170 config CROS_EC_SANDBOX
171 bool "Enable Chrome OS EC sandbox driver"
172 depends on CROS_EC && SANDBOX
174 Enable a sandbox emulation of the Chrome OS EC. This supports
175 keyboard (use the -l flag to enable the LCD), verified boot context,
176 EC flash read/write/erase support and a few other things. It is
177 enough to perform a Chrome OS verified boot on sandbox.
179 config SPL_CROS_EC_SANDBOX
180 bool "Enable Chrome OS EC sandbox driver in SPL"
181 depends on SPL_CROS_EC && SANDBOX
183 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
184 keyboard (use the -l flag to enable the LCD), verified boot context,
185 EC flash read/write/erase support and a few other things. It is
186 enough to perform a Chrome OS verified boot on sandbox.
188 config TPL_CROS_EC_SANDBOX
189 bool "Enable Chrome OS EC sandbox driver in TPL"
190 depends on TPL_CROS_EC && SANDBOX
192 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
193 keyboard (use the -l flag to enable the LCD), verified boot context,
194 EC flash read/write/erase support and a few other things. It is
195 enough to perform a Chrome OS verified boot on sandbox.
198 bool "Enable Chrome OS EC SPI driver"
201 Enable SPI access to the Chrome OS EC. This is used on newer
202 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
203 provides a faster and more robust interface than I2C but the bugs
204 are less interesting.
207 bool "Enable support for DS4510 CPU supervisor"
209 Enable support for the Maxim DS4510 CPU supervisor. It has an
210 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
211 and a configurable timer for the supervisor function. The device is
215 bool "Enable FSL SEC_MON Driver"
217 Freescale Security Monitor block is responsible for monitoring
219 Security Monitor can be transitioned on any security failures,
220 like software violations or hardware security violations.
223 bool "Interrupt controller"
225 This enables support for interrupt controllers, including ITSS.
226 Some devices have extra features, such as Apollo Lake. The
227 device has its own uclass since there are several operations
231 bool "Ingenic JZ4780 eFUSE support"
232 depends on ARCH_JZ47XX
234 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
237 bool "Enable MXC OCOTP Driver"
238 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
241 If you say Y here, you will get support for the One Time
242 Programmable memory pages that are stored on the some
243 Freescale i.MX processors.
246 bool "Enable MXC OCOTP driver in SPL"
247 depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
250 If you say Y here, you will get support for the One Time
251 Programmable memory pages, that are stored on some
252 Freescale i.MX processors, in SPL.
254 config NUVOTON_NCT6102D
255 bool "Enable Nuvoton NCT6102D Super I/O driver"
257 If you say Y here, you will get support for the Nuvoton
258 NCT6102D Super I/O driver. This can be used to enable or
259 disable the legacy UART, the watchdog or other devices
260 in the Nuvoton Super IO chips on X86 platforms.
263 bool "Intel Primary to Sideband Bridge"
264 depends on X86 || SANDBOX
266 This enables support for the Intel Primary to Sideband Bridge,
267 abbreviated to P2SB. The P2SB is used to access various peripherals
268 such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
269 space. The space is segmented into different channels and peripherals
270 are accessed by device-specific means within those channels. Devices
271 should be added in the device tree as subnodes of the P2SB. A
272 Peripheral Channel Register? (PCR) API is provided to access those
273 devices - see pcr_readl(), etc.
276 bool "Intel Primary to Sideband Bridge in SPL"
277 depends on SPL && (X86 || SANDBOX)
279 The Primary to Sideband Bridge is used to access various peripherals
280 through memory-mapped I/O in a large chunk of PCI space. The space is
281 segmented into different channels and peripherals are accessed by
282 device-specific means within those channels. Devices should be added
283 in the device tree as subnodes of the p2sb.
286 bool "Intel Primary to Sideband Bridge in TPL"
287 depends on TPL && (X86 || SANDBOX)
289 The Primary to Sideband Bridge is used to access various peripherals
290 through memory-mapped I/O in a large chunk of PCI space. The space is
291 segmented into different channels and peripherals are accessed by
292 device-specific means within those channels. Devices should be added
293 in the device tree as subnodes of the p2sb.
296 bool "Enable power-sequencing drivers"
299 Power-sequencing drivers provide support for controlling power for
300 devices. They are typically referenced by a phandle from another
301 device. When the device is started up, its power sequence can be
305 bool "Enable power-sequencing drivers for SPL"
308 Power-sequencing drivers provide support for controlling power for
309 devices. They are typically referenced by a phandle from another
310 device. When the device is started up, its power sequence can be
314 bool "Enable PCA9551 LED driver"
316 Enable driver for PCA9551 LED controller. This controller
317 is connected via I2C. So I2C needs to be enabled.
319 config PCA9551_I2C_ADDR
320 hex "I2C address of PCA9551 LED controller"
321 depends on PCA9551_LED
324 The I2C address of the PCA9551 LED controller.
327 bool "Enable STM32MP fuse wrapper providing the fuse API"
328 depends on ARCH_STM32MP && MISC
329 default y if CMD_FUSE
331 If you say Y here, you will get support for the fuse API (OTP)
332 for STM32MP architecture.
333 This API is needed for CMD_FUSE.
336 bool "Enable RCC driver for the STM32 SoC's family"
337 depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
339 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
340 block) is responsible of the management of the clock and reset
342 This driver is similar to an MFD driver in the Linux kernel.
345 bool "Enable support for the Tegra CAR driver"
346 depends on TEGRA_NO_BPMP
348 The Tegra CAR (Clock and Reset Controller) is a HW module that
349 controls almost all clocks and resets in a Tegra SoC.
352 bool "Enable support for the Tegra186 BPMP driver"
355 The Tegra BPMP (Boot and Power Management Processor) is a separate
356 auxiliary CPU embedded into Tegra to perform power management work,
357 and controls related features such as clocks, resets, power domains,
358 PMIC I2C bus, etc. This driver provides the core low-level
359 communication path by which feature-specific drivers (such as clock)
360 can make requests to the BPMP. This driver is similar to an MFD
361 driver in the Linux kernel.
364 bool "Enable support for test drivers"
367 This enables drivers and uclasses that provides a way of testing the
368 operations of memory allocation and driver/uclass methods in driver
369 model. This should only be enabled for testing as it is not useful for
373 bool "Enable TWL4030 LED controller"
375 Enable this to add support for the TWL4030 LED controller.
377 config WINBOND_W83627
378 bool "Enable Winbond Super I/O driver"
380 If you say Y here, you will get support for the Winbond
381 W83627 Super I/O driver. This can be used to enable the
382 legacy UART or other devices in the Winbond Super IO chips
388 Hidden option to enable QEMU fw_cfg interface and uclass. This will
389 be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
395 Hidden option to enable PIO QEMU fw_cfg interface. This will be
396 selected by the appropriate QEMU board.
402 Hidden option to enable MMIO QEMU fw_cfg interface. This will be
403 selected by the appropriate QEMU board.
406 bool "Enable driver for generic I2C-attached EEPROMs"
409 Enable a generic driver for EEPROMs attached via I2C.
412 config SPL_I2C_EEPROM
413 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
414 depends on MISC && SPL && SPL_DM
416 This option is an SPL-variant of the I2C_EEPROM option.
417 See the help of I2C_EEPROM for details.
419 config SYS_I2C_EEPROM_ADDR
420 hex "Chip address of the EEPROM device"
421 depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
426 config SYS_I2C_EEPROM_ADDR_OVERFLOW
427 hex "EEPROM Address Overflow"
430 EEPROM chips that implement "address overflow" are ones
431 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
432 address and the extra bits end up in the "chip address" bit
433 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
438 config GDSYS_RXAUI_CTRL
439 bool "Enable gdsys RXAUI control driver"
442 Support gdsys FPGA's RXAUI control.
445 bool "Enable gdsys IOEP driver"
448 Support gdsys FPGA's IO endpoint driver.
450 config MPC83XX_SERDES
451 bool "Enable MPC83xx serdes driver"
454 Support for serdes found on MPC83xx SoCs.
457 bool "Enable loader driver for file system"
459 This is file system generic loader which can be used to load
460 the file image from the storage into target such as memory.
462 The consumer driver would then use this loader to program whatever,
466 bool "Enable loader driver for file system"
468 This is file system generic loader which can be used to load
469 the file image from the storage into target such as memory.
471 The consumer driver would then use this loader to program whatever,
475 bool "Enable gdsys SOC driver"
478 Support for gdsys IHS SOC, a simple bus associated with each gdsys
479 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
480 register maps are contained within the FPGA's register map.
483 bool "Enable IHS FPGA driver"
486 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
487 gdsys devices, which supply the majority of the functionality offered
488 by the devices. This driver supports both CON and CPU variants of the
489 devices, depending on the device tree entry.
491 bool "Enable K3 ESM driver"
494 Support ESM (Error Signaling Module) on TI K3 SoCs.
496 config MICROCHIP_FLEXCOM
497 bool "Enable Microchip Flexcom driver"
500 The Atmel Flexcom is just a wrapper which embeds a SPI controller,
501 an I2C controller and an USART.
502 Only one function can be used at a time and is chosen at boot time
503 according to the device tree.
506 depends on ARCH_K3 && SPL_DM_REGULATOR
507 bool "AVS class 0 support for K3 devices"
509 K3 devices have the optimized voltage values for the main voltage
510 domains stored in efuse within the VTM IP. This driver reads the
511 optimized voltage from the efuse, so that it can be programmed
512 to the PMIC on board.
515 bool "Enable PMIC ESM driver"
518 Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
519 typically to reboot the board in error condition.
525 bool "Enable Kontron sl28cpld multi-function driver"
528 Support for the Kontron sl28cpld management controller. This is
529 the base driver which provides common access methods for the