2 # Multifunction miscellaneous devices
5 menu "Multifunction device drivers"
8 bool "Enable Driver Model for Misc drivers"
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
17 bool "Enable Driver Model for Misc drivers in SPL"
20 Enable driver model for miscellaneous devices. This class is
21 used only for those do not fit other more general classes. A
22 set of generic read, write and ioctl methods may be used to
26 bool "Enable Driver Model for Misc drivers in TPL"
29 Enable driver model for miscellaneous devices. This class is
30 used only for those do not fit other more general classes. A
31 set of generic read, write and ioctl methods may be used to
35 bool "Altera Sysid support"
38 Select this to enable a sysid for Altera devices. Please find
39 details on the "Embedded Peripherals IP User Guide" of Altera.
42 bool "Support for Atmel ATSHA204A module"
46 Enable support for I2C connected Atmel's ATSHA204A
47 CryptoAuthentication module found for example on the Turris Omnia
51 bool "Gateworks System Controller Support"
54 Enable access for the Gateworks System Controller used on Gateworks
55 boards to provide a boot watchdog, power control, temperature monitor,
56 voltage ADCs, and EEPROM.
59 bool "Rockchip e-fuse support"
62 Enable (read-only) access for the e-fuse block found in Rockchip
63 SoCs: accesses can either be made using byte addressing and a length
64 or through child-nodes that are generated based on the e-fuse map
65 retrieved from the DTS.
67 This driver currently supports the RK3399 only, but can easily be
68 extended (by porting the read function from the Linux kernel sources)
69 to support other recent Rockchip devices.
72 bool "Rockchip OTP Support"
75 Enable (read-only) access for the one-time-programmable memory block
76 found in Rockchip SoCs: accesses can either be made using byte
77 addressing and a length or through child-nodes that are generated
78 based on the e-fuse map retrieved from the DTS.
81 bool "SiFive eMemory OTP driver"
84 Enable support for reading and writing the eMemory OTP on the
87 config VEXPRESS_CONFIG
88 bool "Enable support for Arm Versatile Express config bus"
91 If you say Y here, you will get support for accessing the
92 configuration bus on the Arm Versatile Express boards via
96 bool "Enable crosec command"
99 Enable command-line access to the Chrome OS EC (Embedded
100 Controller). This provides the 'crosec' command which has
101 a number of sub-commands for performing EC tasks such as
102 updating its flash, accessing a small saved context area
103 and talking to the I2C bus behind the EC (if there is one).
106 bool "Enable Chrome OS EC"
108 Enable access to the Chrome OS EC. This is a separate
109 microcontroller typically available on a SPI bus on Chromebooks. It
110 provides access to the keyboard, some internal storage and may
111 control access to the battery and main PMIC depending on the
112 device. You can use the 'crosec' command to access it.
115 bool "Enable Chrome OS EC in SPL"
118 Enable access to the Chrome OS EC in SPL. This is a separate
119 microcontroller typically available on a SPI bus on Chromebooks. It
120 provides access to the keyboard, some internal storage and may
121 control access to the battery and main PMIC depending on the
122 device. You can use the 'crosec' command to access it.
125 bool "Enable Chrome OS EC in TPL"
128 Enable access to the Chrome OS EC in TPL. This is a separate
129 microcontroller typically available on a SPI bus on Chromebooks. It
130 provides access to the keyboard, some internal storage and may
131 control access to the battery and main PMIC depending on the
132 device. You can use the 'crosec' command to access it.
135 bool "Enable Chrome OS EC in VPL"
138 Enable access to the Chrome OS EC in VPL. This is a separate
139 microcontroller typically available on a SPI bus on Chromebooks. It
140 provides access to the keyboard, some internal storage and may
141 control access to the battery and main PMIC depending on the
142 device. You can use the 'crosec' command to access it.
145 bool "Enable Chrome OS EC I2C driver"
148 Enable I2C access to the Chrome OS EC. This is used on older
149 ARM Chromebooks such as snow and spring before the standard bus
150 changed to SPI. The EC will accept commands across the I2C using
151 a special message protocol, and provide responses.
154 bool "Enable Chrome OS EC LPC driver"
157 Enable I2C access to the Chrome OS EC. This is used on x86
158 Chromebooks such as link and falco. The keyboard is provided
159 through a legacy port interface, so on x86 machines the main
160 function of the EC is power and thermal management.
162 config SPL_CROS_EC_LPC
163 bool "Enable Chrome OS EC LPC driver in SPL"
166 Enable I2C access to the Chrome OS EC. This is used on x86
167 Chromebooks such as link and falco. The keyboard is provided
168 through a legacy port interface, so on x86 machines the main
169 function of the EC is power and thermal management.
171 config TPL_CROS_EC_LPC
172 bool "Enable Chrome OS EC LPC driver in TPL"
175 Enable I2C access to the Chrome OS EC. This is used on x86
176 Chromebooks such as link and falco. The keyboard is provided
177 through a legacy port interface, so on x86 machines the main
178 function of the EC is power and thermal management.
180 config VPL_CROS_EC_LPC
181 bool "Enable Chrome OS EC LPC driver in VPL"
184 Enable I2C access to the Chrome OS EC. This is used on x86
185 Chromebooks such as link and falco. The keyboard is provided
186 through a legacy port interface, so on x86 machines the main
187 function of the EC is power and thermal management.
189 config CROS_EC_SANDBOX
190 bool "Enable Chrome OS EC sandbox driver"
191 depends on CROS_EC && SANDBOX
193 Enable a sandbox emulation of the Chrome OS EC. This supports
194 keyboard (use the -l flag to enable the LCD), verified boot context,
195 EC flash read/write/erase support and a few other things. It is
196 enough to perform a Chrome OS verified boot on sandbox.
198 config SPL_CROS_EC_SANDBOX
199 bool "Enable Chrome OS EC sandbox driver in SPL"
200 depends on SPL_CROS_EC && SANDBOX
202 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
203 keyboard (use the -l flag to enable the LCD), verified boot context,
204 EC flash read/write/erase support and a few other things. It is
205 enough to perform a Chrome OS verified boot on sandbox.
207 config TPL_CROS_EC_SANDBOX
208 bool "Enable Chrome OS EC sandbox driver in TPL"
209 depends on TPL_CROS_EC && SANDBOX
211 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
212 keyboard (use the -l flag to enable the LCD), verified boot context,
213 EC flash read/write/erase support and a few other things. It is
214 enough to perform a Chrome OS verified boot on sandbox.
216 config VPL_CROS_EC_SANDBOX
217 bool "Enable Chrome OS EC sandbox driver in VPL"
218 depends on VPL_CROS_EC && SANDBOX
220 Enable a sandbox emulation of the Chrome OS EC in VPL. This supports
221 keyboard (use the -l flag to enable the LCD), verified boot context,
222 EC flash read/write/erase support and a few other things. It is
223 enough to perform a Chrome OS verified boot on sandbox.
226 bool "Enable Chrome OS EC SPI driver"
229 Enable SPI access to the Chrome OS EC. This is used on newer
230 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
231 provides a faster and more robust interface than I2C but the bugs
232 are less interesting.
235 bool "Enable support for DS4510 CPU supervisor"
237 Enable support for the Maxim DS4510 CPU supervisor. It has an
238 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
239 and a configurable timer for the supervisor function. The device is
243 bool "Enable FSL SEC_MON Driver"
245 Freescale Security Monitor block is responsible for monitoring
247 Security Monitor can be transitioned on any security failures,
248 like software violations or hardware security violations.
251 bool "Interrupt controller"
253 This enables support for interrupt controllers, including ITSS.
254 Some devices have extra features, such as Apollo Lake. The
255 device has its own uclass since there are several operations
259 bool "Ingenic JZ4780 eFUSE support"
260 depends on ARCH_JZ47XX
262 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
265 bool "Enable MXC OCOTP Driver"
266 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
269 If you say Y here, you will get support for the One Time
270 Programmable memory pages that are stored on the some
271 Freescale i.MX processors.
274 bool "Enable MXC OCOTP driver in SPL"
275 depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
278 If you say Y here, you will get support for the One Time
279 Programmable memory pages, that are stored on some
280 Freescale i.MX processors, in SPL.
282 config NUVOTON_NCT6102D
283 bool "Enable Nuvoton NCT6102D Super I/O driver"
285 If you say Y here, you will get support for the Nuvoton
286 NCT6102D Super I/O driver. This can be used to enable or
287 disable the legacy UART, the watchdog or other devices
288 in the Nuvoton Super IO chips on X86 platforms.
291 bool "Intel Primary to Sideband Bridge"
292 depends on X86 || SANDBOX
294 This enables support for the Intel Primary to Sideband Bridge,
295 abbreviated to P2SB. The P2SB is used to access various peripherals
296 such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
297 space. The space is segmented into different channels and peripherals
298 are accessed by device-specific means within those channels. Devices
299 should be added in the device tree as subnodes of the P2SB. A
300 Peripheral Channel Register? (PCR) API is provided to access those
301 devices - see pcr_readl(), etc.
304 bool "Intel Primary to Sideband Bridge in SPL"
305 depends on SPL && (X86 || SANDBOX)
307 The Primary to Sideband Bridge is used to access various peripherals
308 through memory-mapped I/O in a large chunk of PCI space. The space is
309 segmented into different channels and peripherals are accessed by
310 device-specific means within those channels. Devices should be added
311 in the device tree as subnodes of the p2sb.
314 bool "Intel Primary to Sideband Bridge in TPL"
315 depends on TPL && (X86 || SANDBOX)
317 The Primary to Sideband Bridge is used to access various peripherals
318 through memory-mapped I/O in a large chunk of PCI space. The space is
319 segmented into different channels and peripherals are accessed by
320 device-specific means within those channels. Devices should be added
321 in the device tree as subnodes of the p2sb.
324 bool "Enable power-sequencing drivers"
327 Power-sequencing drivers provide support for controlling power for
328 devices. They are typically referenced by a phandle from another
329 device. When the device is started up, its power sequence can be
333 bool "Enable power-sequencing drivers for SPL"
336 Power-sequencing drivers provide support for controlling power for
337 devices. They are typically referenced by a phandle from another
338 device. When the device is started up, its power sequence can be
342 bool "Enable PCA9551 LED driver"
344 Enable driver for PCA9551 LED controller. This controller
345 is connected via I2C. So I2C needs to be enabled.
347 config PCA9551_I2C_ADDR
348 hex "I2C address of PCA9551 LED controller"
349 depends on PCA9551_LED
352 The I2C address of the PCA9551 LED controller.
355 bool "Enable STM32MP fuse wrapper providing the fuse API"
356 depends on ARCH_STM32MP && MISC
357 default y if CMD_FUSE
359 If you say Y here, you will get support for the fuse API (OTP)
360 for STM32MP architecture.
361 This API is needed for CMD_FUSE.
364 bool "Enable RCC driver for the STM32 SoC's family"
365 depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
367 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
368 block) is responsible of the management of the clock and reset
370 This driver is similar to an MFD driver in the Linux kernel.
373 bool "Enable support for the Tegra CAR driver"
374 depends on TEGRA_NO_BPMP
376 The Tegra CAR (Clock and Reset Controller) is a HW module that
377 controls almost all clocks and resets in a Tegra SoC.
380 bool "Enable support for the Tegra186 BPMP driver"
383 The Tegra BPMP (Boot and Power Management Processor) is a separate
384 auxiliary CPU embedded into Tegra to perform power management work,
385 and controls related features such as clocks, resets, power domains,
386 PMIC I2C bus, etc. This driver provides the core low-level
387 communication path by which feature-specific drivers (such as clock)
388 can make requests to the BPMP. This driver is similar to an MFD
389 driver in the Linux kernel.
392 bool "Enable support for test drivers"
395 This enables drivers and uclasses that provides a way of testing the
396 operations of memory allocation and driver/uclass methods in driver
397 model. This should only be enabled for testing as it is not useful for
401 bool "Enable TWL4030 LED controller"
403 Enable this to add support for the TWL4030 LED controller.
405 config WINBOND_W83627
406 bool "Enable Winbond Super I/O driver"
408 If you say Y here, you will get support for the Winbond
409 W83627 Super I/O driver. This can be used to enable the
410 legacy UART or other devices in the Winbond Super IO chips
416 Hidden option to enable QEMU fw_cfg interface and uclass. This will
417 be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
423 Hidden option to enable PIO QEMU fw_cfg interface. This will be
424 selected by the appropriate QEMU board.
430 Hidden option to enable MMIO QEMU fw_cfg interface. This will be
431 selected by the appropriate QEMU board.
434 bool "Enable driver for generic I2C-attached EEPROMs"
437 Enable a generic driver for EEPROMs attached via I2C.
440 config SPL_I2C_EEPROM
441 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
442 depends on MISC && SPL && SPL_DM
444 This option is an SPL-variant of the I2C_EEPROM option.
445 See the help of I2C_EEPROM for details.
447 config SYS_I2C_EEPROM_ADDR
448 hex "Chip address of the EEPROM device"
449 depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
454 config SYS_I2C_EEPROM_ADDR_OVERFLOW
455 hex "EEPROM Address Overflow"
458 EEPROM chips that implement "address overflow" are ones
459 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
460 address and the extra bits end up in the "chip address" bit
461 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
466 config GDSYS_RXAUI_CTRL
467 bool "Enable gdsys RXAUI control driver"
470 Support gdsys FPGA's RXAUI control.
473 bool "Enable gdsys IOEP driver"
476 Support gdsys FPGA's IO endpoint driver.
478 config MPC83XX_SERDES
479 bool "Enable MPC83xx serdes driver"
482 Support for serdes found on MPC83xx SoCs.
485 bool "Enable loader driver for file system"
487 This is file system generic loader which can be used to load
488 the file image from the storage into target such as memory.
490 The consumer driver would then use this loader to program whatever,
494 bool "Enable loader driver for file system"
496 This is file system generic loader which can be used to load
497 the file image from the storage into target such as memory.
499 The consumer driver would then use this loader to program whatever,
503 bool "Enable gdsys SOC driver"
506 Support for gdsys IHS SOC, a simple bus associated with each gdsys
507 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
508 register maps are contained within the FPGA's register map.
511 bool "Enable IHS FPGA driver"
514 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
515 gdsys devices, which supply the majority of the functionality offered
516 by the devices. This driver supports both CON and CPU variants of the
517 devices, depending on the device tree entry.
519 bool "Enable K3 ESM driver"
522 Support ESM (Error Signaling Module) on TI K3 SoCs.
524 config MICROCHIP_FLEXCOM
525 bool "Enable Microchip Flexcom driver"
528 The Atmel Flexcom is just a wrapper which embeds a SPI controller,
529 an I2C controller and an USART.
530 Only one function can be used at a time and is chosen at boot time
531 according to the device tree.
534 depends on ARCH_K3 && SPL_DM_REGULATOR
535 bool "AVS class 0 support for K3 devices"
537 K3 devices have the optimized voltage values for the main voltage
538 domains stored in efuse within the VTM IP. This driver reads the
539 optimized voltage from the efuse, so that it can be programmed
540 to the PMIC on board.
543 bool "Enable PMIC ESM driver"
546 Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
547 typically to reboot the board in error condition.
553 bool "Enable Kontron sl28cpld multi-function driver"
556 Support for the Kontron sl28cpld management controller. This is
557 the base driver which provides common access methods for the