2 # Multifunction miscellaneous devices
5 menu "Multifunction device drivers"
8 bool "Enable Driver Model for Misc drivers"
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
17 bool "Enable Driver Model for Misc drivers in SPL"
21 Enable driver model for miscellaneous devices. This class is
22 used only for those do not fit other more general classes. A
23 set of generic read, write and ioctl methods may be used to
27 bool "Enable Driver Model for Misc drivers in TPL"
31 Enable driver model for miscellaneous devices. This class is
32 used only for those do not fit other more general classes. A
33 set of generic read, write and ioctl methods may be used to
37 bool "Enable Driver Model for Misc drivers in VPL"
41 Enable driver model for miscellaneous devices. This class is
42 used only for those do not fit other more general classes. A
43 set of generic read, write and ioctl methods may be used to
47 bool "Altera Sysid support"
50 Select this to enable a sysid for Altera devices. Please find
51 details on the "Embedded Peripherals IP User Guide" of Altera.
54 bool "Support for Atmel ATSHA204A module"
58 Enable support for I2C connected Atmel's ATSHA204A
59 CryptoAuthentication module found for example on the Turris Omnia
63 bool "Gateworks System Controller Support"
66 Enable access for the Gateworks System Controller used on Gateworks
67 boards to provide a boot watchdog, power control, temperature monitor,
68 voltage ADCs, and EEPROM.
71 bool "Rockchip e-fuse support"
74 Enable (read-only) access for the e-fuse block found in Rockchip
75 SoCs: accesses can either be made using byte addressing and a length
76 or through child-nodes that are generated based on the e-fuse map
77 retrieved from the DTS.
79 This driver currently supports the RK3399 only, but can easily be
80 extended (by porting the read function from the Linux kernel sources)
81 to support other recent Rockchip devices.
84 bool "Rockchip OTP Support"
87 Enable (read-only) access for the one-time-programmable memory block
88 found in Rockchip SoCs: accesses can either be made using byte
89 addressing and a length or through child-nodes that are generated
90 based on the e-fuse map retrieved from the DTS.
93 bool "SiFive eMemory OTP driver"
96 Enable support for reading and writing the eMemory OTP on the
99 config VEXPRESS_CONFIG
100 bool "Enable support for Arm Versatile Express config bus"
103 If you say Y here, you will get support for accessing the
104 configuration bus on the Arm Versatile Express boards via
108 bool "Enable crosec command"
111 Enable command-line access to the Chrome OS EC (Embedded
112 Controller). This provides the 'crosec' command which has
113 a number of sub-commands for performing EC tasks such as
114 updating its flash, accessing a small saved context area
115 and talking to the I2C bus behind the EC (if there is one).
118 bool "Enable Chrome OS EC"
120 Enable access to the Chrome OS EC. This is a separate
121 microcontroller typically available on a SPI bus on Chromebooks. It
122 provides access to the keyboard, some internal storage and may
123 control access to the battery and main PMIC depending on the
124 device. You can use the 'crosec' command to access it.
127 bool "Enable Chrome OS EC in SPL"
130 Enable access to the Chrome OS EC in SPL. This is a separate
131 microcontroller typically available on a SPI bus on Chromebooks. It
132 provides access to the keyboard, some internal storage and may
133 control access to the battery and main PMIC depending on the
134 device. You can use the 'crosec' command to access it.
137 bool "Enable Chrome OS EC in TPL"
140 Enable access to the Chrome OS EC in TPL. This is a separate
141 microcontroller typically available on a SPI bus on Chromebooks. It
142 provides access to the keyboard, some internal storage and may
143 control access to the battery and main PMIC depending on the
144 device. You can use the 'crosec' command to access it.
147 bool "Enable Chrome OS EC in VPL"
150 Enable access to the Chrome OS EC in VPL. This is a separate
151 microcontroller typically available on a SPI bus on Chromebooks. It
152 provides access to the keyboard, some internal storage and may
153 control access to the battery and main PMIC depending on the
154 device. You can use the 'crosec' command to access it.
157 bool "Enable Chrome OS EC I2C driver"
160 Enable I2C access to the Chrome OS EC. This is used on older
161 ARM Chromebooks such as snow and spring before the standard bus
162 changed to SPI. The EC will accept commands across the I2C using
163 a special message protocol, and provide responses.
166 bool "Enable Chrome OS EC LPC driver"
169 Enable I2C access to the Chrome OS EC. This is used on x86
170 Chromebooks such as link and falco. The keyboard is provided
171 through a legacy port interface, so on x86 machines the main
172 function of the EC is power and thermal management.
174 config SPL_CROS_EC_LPC
175 bool "Enable Chrome OS EC LPC driver in SPL"
178 Enable I2C access to the Chrome OS EC. This is used on x86
179 Chromebooks such as link and falco. The keyboard is provided
180 through a legacy port interface, so on x86 machines the main
181 function of the EC is power and thermal management.
183 config TPL_CROS_EC_LPC
184 bool "Enable Chrome OS EC LPC driver in TPL"
187 Enable I2C access to the Chrome OS EC. This is used on x86
188 Chromebooks such as link and falco. The keyboard is provided
189 through a legacy port interface, so on x86 machines the main
190 function of the EC is power and thermal management.
192 config VPL_CROS_EC_LPC
193 bool "Enable Chrome OS EC LPC driver in VPL"
196 Enable I2C access to the Chrome OS EC. This is used on x86
197 Chromebooks such as link and falco. The keyboard is provided
198 through a legacy port interface, so on x86 machines the main
199 function of the EC is power and thermal management.
201 config CROS_EC_SANDBOX
202 bool "Enable Chrome OS EC sandbox driver"
203 depends on CROS_EC && SANDBOX
205 Enable a sandbox emulation of the Chrome OS EC. This supports
206 keyboard (use the -l flag to enable the LCD), verified boot context,
207 EC flash read/write/erase support and a few other things. It is
208 enough to perform a Chrome OS verified boot on sandbox.
210 config SPL_CROS_EC_SANDBOX
211 bool "Enable Chrome OS EC sandbox driver in SPL"
212 depends on SPL_CROS_EC && SANDBOX
214 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
215 keyboard (use the -l flag to enable the LCD), verified boot context,
216 EC flash read/write/erase support and a few other things. It is
217 enough to perform a Chrome OS verified boot on sandbox.
219 config TPL_CROS_EC_SANDBOX
220 bool "Enable Chrome OS EC sandbox driver in TPL"
221 depends on TPL_CROS_EC && SANDBOX
223 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
224 keyboard (use the -l flag to enable the LCD), verified boot context,
225 EC flash read/write/erase support and a few other things. It is
226 enough to perform a Chrome OS verified boot on sandbox.
228 config VPL_CROS_EC_SANDBOX
229 bool "Enable Chrome OS EC sandbox driver in VPL"
230 depends on VPL_CROS_EC && SANDBOX
232 Enable a sandbox emulation of the Chrome OS EC in VPL. This supports
233 keyboard (use the -l flag to enable the LCD), verified boot context,
234 EC flash read/write/erase support and a few other things. It is
235 enough to perform a Chrome OS verified boot on sandbox.
238 bool "Enable Chrome OS EC SPI driver"
241 Enable SPI access to the Chrome OS EC. This is used on newer
242 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
243 provides a faster and more robust interface than I2C but the bugs
244 are less interesting.
247 bool "Enable support for DS4510 CPU supervisor"
249 Enable support for the Maxim DS4510 CPU supervisor. It has an
250 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
251 and a configurable timer for the supervisor function. The device is
255 bool "Enable FSL SEC_MON Driver"
257 Freescale Security Monitor block is responsible for monitoring
259 Security Monitor can be transitioned on any security failures,
260 like software violations or hardware security violations.
263 bool "Interrupt controller"
265 This enables support for interrupt controllers, including ITSS.
266 Some devices have extra features, such as Apollo Lake. The
267 device has its own uclass since there are several operations
271 bool "Ingenic JZ4780 eFUSE support"
272 depends on ARCH_JZ47XX
274 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
277 bool "Enable MXC OCOTP Driver"
278 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
281 If you say Y here, you will get support for the One Time
282 Programmable memory pages that are stored on the some
283 Freescale i.MX processors.
286 bool "Enable MXC OCOTP driver in SPL"
287 depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
290 If you say Y here, you will get support for the One Time
291 Programmable memory pages, that are stored on some
292 Freescale i.MX processors, in SPL.
294 config NUVOTON_NCT6102D
295 bool "Enable Nuvoton NCT6102D Super I/O driver"
297 If you say Y here, you will get support for the Nuvoton
298 NCT6102D Super I/O driver. This can be used to enable or
299 disable the legacy UART, the watchdog or other devices
300 in the Nuvoton Super IO chips on X86 platforms.
303 bool "Intel Primary to Sideband Bridge"
304 depends on X86 || SANDBOX
306 This enables support for the Intel Primary to Sideband Bridge,
307 abbreviated to P2SB. The P2SB is used to access various peripherals
308 such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
309 space. The space is segmented into different channels and peripherals
310 are accessed by device-specific means within those channels. Devices
311 should be added in the device tree as subnodes of the P2SB. A
312 Peripheral Channel Register? (PCR) API is provided to access those
313 devices - see pcr_readl(), etc.
316 bool "Intel Primary to Sideband Bridge in SPL"
317 depends on SPL && (X86 || SANDBOX)
319 The Primary to Sideband Bridge is used to access various peripherals
320 through memory-mapped I/O in a large chunk of PCI space. The space is
321 segmented into different channels and peripherals are accessed by
322 device-specific means within those channels. Devices should be added
323 in the device tree as subnodes of the p2sb.
326 bool "Intel Primary to Sideband Bridge in TPL"
327 depends on TPL && (X86 || SANDBOX)
329 The Primary to Sideband Bridge is used to access various peripherals
330 through memory-mapped I/O in a large chunk of PCI space. The space is
331 segmented into different channels and peripherals are accessed by
332 device-specific means within those channels. Devices should be added
333 in the device tree as subnodes of the p2sb.
336 bool "Enable power-sequencing drivers"
339 Power-sequencing drivers provide support for controlling power for
340 devices. They are typically referenced by a phandle from another
341 device. When the device is started up, its power sequence can be
345 bool "Enable power-sequencing drivers for SPL"
348 Power-sequencing drivers provide support for controlling power for
349 devices. They are typically referenced by a phandle from another
350 device. When the device is started up, its power sequence can be
354 bool "Enable PCA9551 LED driver"
356 Enable driver for PCA9551 LED controller. This controller
357 is connected via I2C. So I2C needs to be enabled.
359 config PCA9551_I2C_ADDR
360 hex "I2C address of PCA9551 LED controller"
361 depends on PCA9551_LED
364 The I2C address of the PCA9551 LED controller.
367 bool "Enable STM32MP fuse wrapper providing the fuse API"
368 depends on ARCH_STM32MP && MISC
369 default y if CMD_FUSE
371 If you say Y here, you will get support for the fuse API (OTP)
372 for STM32MP architecture.
373 This API is needed for CMD_FUSE.
376 bool "Enable RCC driver for the STM32 SoC's family"
377 depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
379 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
380 block) is responsible of the management of the clock and reset
382 This driver is similar to an MFD driver in the Linux kernel.
385 bool "Enable support for the Tegra CAR driver"
386 depends on TEGRA_NO_BPMP
388 The Tegra CAR (Clock and Reset Controller) is a HW module that
389 controls almost all clocks and resets in a Tegra SoC.
392 bool "Enable support for the Tegra186 BPMP driver"
395 The Tegra BPMP (Boot and Power Management Processor) is a separate
396 auxiliary CPU embedded into Tegra to perform power management work,
397 and controls related features such as clocks, resets, power domains,
398 PMIC I2C bus, etc. This driver provides the core low-level
399 communication path by which feature-specific drivers (such as clock)
400 can make requests to the BPMP. This driver is similar to an MFD
401 driver in the Linux kernel.
404 bool "Enable support for test drivers"
407 This enables drivers and uclasses that provides a way of testing the
408 operations of memory allocation and driver/uclass methods in driver
409 model. This should only be enabled for testing as it is not useful for
413 bool "Enable TWL4030 LED controller"
415 Enable this to add support for the TWL4030 LED controller.
417 config WINBOND_W83627
418 bool "Enable Winbond Super I/O driver"
420 If you say Y here, you will get support for the Winbond
421 W83627 Super I/O driver. This can be used to enable the
422 legacy UART or other devices in the Winbond Super IO chips
428 Hidden option to enable QEMU fw_cfg interface and uclass. This will
429 be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
435 Hidden option to enable PIO QEMU fw_cfg interface. This will be
436 selected by the appropriate QEMU board.
442 Hidden option to enable MMIO QEMU fw_cfg interface. This will be
443 selected by the appropriate QEMU board.
446 bool "Enable driver for generic I2C-attached EEPROMs"
449 Enable a generic driver for EEPROMs attached via I2C.
452 config SPL_I2C_EEPROM
453 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
454 depends on MISC && SPL && SPL_DM
456 This option is an SPL-variant of the I2C_EEPROM option.
457 See the help of I2C_EEPROM for details.
459 config SYS_I2C_EEPROM_ADDR
460 hex "Chip address of the EEPROM device"
461 depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
466 config SYS_I2C_EEPROM_ADDR_OVERFLOW
467 hex "EEPROM Address Overflow"
470 EEPROM chips that implement "address overflow" are ones
471 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
472 address and the extra bits end up in the "chip address" bit
473 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
478 config GDSYS_RXAUI_CTRL
479 bool "Enable gdsys RXAUI control driver"
482 Support gdsys FPGA's RXAUI control.
485 bool "Enable gdsys IOEP driver"
488 Support gdsys FPGA's IO endpoint driver.
490 config MPC83XX_SERDES
491 bool "Enable MPC83xx serdes driver"
494 Support for serdes found on MPC83xx SoCs.
497 bool "Enable loader driver for file system"
499 This is file system generic loader which can be used to load
500 the file image from the storage into target such as memory.
502 The consumer driver would then use this loader to program whatever,
506 bool "Enable loader driver for file system"
508 This is file system generic loader which can be used to load
509 the file image from the storage into target such as memory.
511 The consumer driver would then use this loader to program whatever,
515 bool "Enable gdsys SOC driver"
518 Support for gdsys IHS SOC, a simple bus associated with each gdsys
519 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
520 register maps are contained within the FPGA's register map.
523 bool "Enable IHS FPGA driver"
526 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
527 gdsys devices, which supply the majority of the functionality offered
528 by the devices. This driver supports both CON and CPU variants of the
529 devices, depending on the device tree entry.
531 bool "Enable K3 ESM driver"
534 Support ESM (Error Signaling Module) on TI K3 SoCs.
536 config MICROCHIP_FLEXCOM
537 bool "Enable Microchip Flexcom driver"
540 The Atmel Flexcom is just a wrapper which embeds a SPI controller,
541 an I2C controller and an USART.
542 Only one function can be used at a time and is chosen at boot time
543 according to the device tree.
546 depends on ARCH_K3 && SPL_DM_REGULATOR
547 bool "AVS class 0 support for K3 devices"
549 K3 devices have the optimized voltage values for the main voltage
550 domains stored in efuse within the VTM IP. This driver reads the
551 optimized voltage from the efuse, so that it can be programmed
552 to the PMIC on board.
555 bool "Enable PMIC ESM driver"
558 Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
559 typically to reboot the board in error condition.
565 bool "Enable Kontron sl28cpld multi-function driver"
568 Support for the Kontron sl28cpld management controller. This is
569 the base driver which provides common access methods for the