2 # Multifunction miscellaneous devices
5 menu "Multifunction device drivers"
8 bool "Enable Driver Model for Misc drivers"
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
17 bool "Enable Driver Model for Misc drivers in SPL"
21 Enable driver model for miscellaneous devices. This class is
22 used only for those do not fit other more general classes. A
23 set of generic read, write and ioctl methods may be used to
27 bool "Enable Driver Model for Misc drivers in TPL"
31 Enable driver model for miscellaneous devices. This class is
32 used only for those do not fit other more general classes. A
33 set of generic read, write and ioctl methods may be used to
37 bool "Enable Driver Model for Misc drivers in VPL"
41 Enable driver model for miscellaneous devices. This class is
42 used only for those do not fit other more general classes. A
43 set of generic read, write and ioctl methods may be used to
49 This adds support for a common interface to different types of
50 non-volatile memory. Consumers can use nvmem-cells properties to look
51 up hardware configuration data such as MAC addresses and calibration
55 bool "NVMEM support in SPL"
57 This adds support for a common interface to different types of
58 non-volatile memory. Consumers can use nvmem-cells properties to look
59 up hardware configuration data such as MAC addresses and calibration
63 bool "Altera Sysid support"
66 Select this to enable a sysid for Altera devices. Please find
67 details on the "Embedded Peripherals IP User Guide" of Altera.
70 bool "Support for Atmel ATSHA204A module"
74 Enable support for I2C connected Atmel's ATSHA204A
75 CryptoAuthentication module found for example on the Turris Omnia
79 bool "Gateworks System Controller Support"
82 Enable access for the Gateworks System Controller used on Gateworks
83 boards to provide a boot watchdog, power control, temperature monitor,
84 voltage ADCs, and EEPROM.
87 bool "Rockchip e-fuse support"
90 Enable (read-only) access for the e-fuse block found in Rockchip
91 SoCs: accesses can either be made using byte addressing and a length
92 or through child-nodes that are generated based on the e-fuse map
93 retrieved from the DTS.
95 This driver currently supports the RK3399 only, but can easily be
96 extended (by porting the read function from the Linux kernel sources)
97 to support other recent Rockchip devices.
100 bool "Rockchip OTP Support"
103 Enable (read-only) access for the one-time-programmable memory block
104 found in Rockchip SoCs: accesses can either be made using byte
105 addressing and a length or through child-nodes that are generated
106 based on the e-fuse map retrieved from the DTS.
109 bool "SiFive eMemory OTP driver"
112 Enable support for reading and writing the eMemory OTP on the
115 config VEXPRESS_CONFIG
116 bool "Enable support for Arm Versatile Express config bus"
119 If you say Y here, you will get support for accessing the
120 configuration bus on the Arm Versatile Express boards via
124 bool "Enable crosec command"
127 Enable command-line access to the Chrome OS EC (Embedded
128 Controller). This provides the 'crosec' command which has
129 a number of sub-commands for performing EC tasks such as
130 updating its flash, accessing a small saved context area
131 and talking to the I2C bus behind the EC (if there is one).
134 bool "Enable Chrome OS EC"
136 Enable access to the Chrome OS EC. This is a separate
137 microcontroller typically available on a SPI bus on Chromebooks. It
138 provides access to the keyboard, some internal storage and may
139 control access to the battery and main PMIC depending on the
140 device. You can use the 'crosec' command to access it.
143 bool "Enable Chrome OS EC in SPL"
146 Enable access to the Chrome OS EC in SPL. This is a separate
147 microcontroller typically available on a SPI bus on Chromebooks. It
148 provides access to the keyboard, some internal storage and may
149 control access to the battery and main PMIC depending on the
150 device. You can use the 'crosec' command to access it.
153 bool "Enable Chrome OS EC in TPL"
156 Enable access to the Chrome OS EC in TPL. This is a separate
157 microcontroller typically available on a SPI bus on Chromebooks. It
158 provides access to the keyboard, some internal storage and may
159 control access to the battery and main PMIC depending on the
160 device. You can use the 'crosec' command to access it.
163 bool "Enable Chrome OS EC in VPL"
166 Enable access to the Chrome OS EC in VPL. This is a separate
167 microcontroller typically available on a SPI bus on Chromebooks. It
168 provides access to the keyboard, some internal storage and may
169 control access to the battery and main PMIC depending on the
170 device. You can use the 'crosec' command to access it.
173 bool "Enable Chrome OS EC I2C driver"
176 Enable I2C access to the Chrome OS EC. This is used on older
177 ARM Chromebooks such as snow and spring before the standard bus
178 changed to SPI. The EC will accept commands across the I2C using
179 a special message protocol, and provide responses.
182 bool "Enable Chrome OS EC LPC driver"
185 Enable I2C access to the Chrome OS EC. This is used on x86
186 Chromebooks such as link and falco. The keyboard is provided
187 through a legacy port interface, so on x86 machines the main
188 function of the EC is power and thermal management.
190 config SPL_CROS_EC_LPC
191 bool "Enable Chrome OS EC LPC driver in SPL"
192 depends on CROS_EC && SPL_MISC
194 Enable I2C access to the Chrome OS EC. This is used on x86
195 Chromebooks such as link and falco. The keyboard is provided
196 through a legacy port interface, so on x86 machines the main
197 function of the EC is power and thermal management.
199 config TPL_CROS_EC_LPC
200 bool "Enable Chrome OS EC LPC driver in TPL"
201 depends on CROS_EC && TPL_MISC
203 Enable I2C access to the Chrome OS EC. This is used on x86
204 Chromebooks such as link and falco. The keyboard is provided
205 through a legacy port interface, so on x86 machines the main
206 function of the EC is power and thermal management.
208 config VPL_CROS_EC_LPC
209 bool "Enable Chrome OS EC LPC driver in VPL"
210 depends on CROS_EC && VPL_MISC
212 Enable I2C access to the Chrome OS EC. This is used on x86
213 Chromebooks such as link and falco. The keyboard is provided
214 through a legacy port interface, so on x86 machines the main
215 function of the EC is power and thermal management.
217 config CROS_EC_SANDBOX
218 bool "Enable Chrome OS EC sandbox driver"
219 depends on CROS_EC && SANDBOX
221 Enable a sandbox emulation of the Chrome OS EC. This supports
222 keyboard (use the -l flag to enable the LCD), verified boot context,
223 EC flash read/write/erase support and a few other things. It is
224 enough to perform a Chrome OS verified boot on sandbox.
226 config SPL_CROS_EC_SANDBOX
227 bool "Enable Chrome OS EC sandbox driver in SPL"
228 depends on SPL_CROS_EC && SANDBOX
230 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
231 keyboard (use the -l flag to enable the LCD), verified boot context,
232 EC flash read/write/erase support and a few other things. It is
233 enough to perform a Chrome OS verified boot on sandbox.
235 config TPL_CROS_EC_SANDBOX
236 bool "Enable Chrome OS EC sandbox driver in TPL"
237 depends on TPL_CROS_EC && SANDBOX
239 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
240 keyboard (use the -l flag to enable the LCD), verified boot context,
241 EC flash read/write/erase support and a few other things. It is
242 enough to perform a Chrome OS verified boot on sandbox.
244 config VPL_CROS_EC_SANDBOX
245 bool "Enable Chrome OS EC sandbox driver in VPL"
246 depends on VPL_CROS_EC && SANDBOX
248 Enable a sandbox emulation of the Chrome OS EC in VPL. This supports
249 keyboard (use the -l flag to enable the LCD), verified boot context,
250 EC flash read/write/erase support and a few other things. It is
251 enough to perform a Chrome OS verified boot on sandbox.
254 bool "Enable Chrome OS EC SPI driver"
257 Enable SPI access to the Chrome OS EC. This is used on newer
258 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
259 provides a faster and more robust interface than I2C but the bugs
260 are less interesting.
263 bool "Enable support for DS4510 CPU supervisor"
265 Enable support for the Maxim DS4510 CPU supervisor. It has an
266 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
267 and a configurable timer for the supervisor function. The device is
271 bool "Enable FSL SEC_MON Driver"
273 Freescale Security Monitor block is responsible for monitoring
275 Security Monitor can be transitioned on any security failures,
276 like software violations or hardware security violations.
279 prompt "Security monitor interaction endianess"
280 depends on FSL_SEC_MON
281 default SYS_FSL_SEC_MON_BE if PPC
282 default SYS_FSL_SEC_MON_LE
284 config SYS_FSL_SEC_MON_LE
285 bool "Security monitor interactions are little endian"
287 config SYS_FSL_SEC_MON_BE
288 bool "Security monitor interactions are big endian"
293 bool "Interrupt controller"
295 This enables support for interrupt controllers, including ITSS.
296 Some devices have extra features, such as Apollo Lake. The
297 device has its own uclass since there are several operations
301 bool "Ingenic JZ4780 eFUSE support"
302 depends on ARCH_JZ47XX
304 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
307 bool "Layerscape Security Fuse Processor"
308 depends on FSL_LSCH2 || ARCH_LS1021A
312 This adds support for the Security Fuse Processor found on Layerscape
313 SoCs. It contains various fuses related to secure boot, including the
314 Super Root Key hash, One-Time-Programmable Master Key, Debug
315 Challenge/Response values, and others. Fuses are numbered according
316 to their four-byte offset from the start of the bank.
318 If you don't need to read/program fuses, say 'n'.
321 bool "Enable MXC OCOTP Driver"
322 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
325 If you say Y here, you will get support for the One Time
326 Programmable memory pages that are stored on the some
327 Freescale i.MX processors.
330 bool "Enable support espi or LPC for Host"
331 depends on REGMAP && SYSCON
333 Enable NPCM BMC espi or LPC support for Host reading and writing.
336 bool "Enable MXC OCOTP driver in SPL"
337 depends on SPL_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
340 If you say Y here, you will get support for the One Time
341 Programmable memory pages, that are stored on some
342 Freescale i.MX processors, in SPL.
345 bool "Nnvoton NPCM BMC On-Chip OTP Memory Support"
346 depends on (ARM && ARCH_NPCM)
349 Support NPCM BMC OTP memory (fuse).
350 To compile this driver as a module, choose M here: the module
351 will be called npcm_otp.
353 config NUVOTON_NCT6102D
354 bool "Enable Nuvoton NCT6102D Super I/O driver"
356 If you say Y here, you will get support for the Nuvoton
357 NCT6102D Super I/O driver. This can be used to enable or
358 disable the legacy UART, the watchdog or other devices
359 in the Nuvoton Super IO chips on X86 platforms.
362 bool "Intel Primary to Sideband Bridge"
363 depends on X86 || SANDBOX
365 This enables support for the Intel Primary to Sideband Bridge,
366 abbreviated to P2SB. The P2SB is used to access various peripherals
367 such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
368 space. The space is segmented into different channels and peripherals
369 are accessed by device-specific means within those channels. Devices
370 should be added in the device tree as subnodes of the P2SB. A
371 Peripheral Channel Register? (PCR) API is provided to access those
372 devices - see pcr_readl(), etc.
375 bool "Intel Primary to Sideband Bridge in SPL"
376 depends on SPL_MISC && (X86 || SANDBOX)
378 The Primary to Sideband Bridge is used to access various peripherals
379 through memory-mapped I/O in a large chunk of PCI space. The space is
380 segmented into different channels and peripherals are accessed by
381 device-specific means within those channels. Devices should be added
382 in the device tree as subnodes of the p2sb.
385 bool "Intel Primary to Sideband Bridge in TPL"
386 depends on TPL_MISC && (X86 || SANDBOX)
388 The Primary to Sideband Bridge is used to access various peripherals
389 through memory-mapped I/O in a large chunk of PCI space. The space is
390 segmented into different channels and peripherals are accessed by
391 device-specific means within those channels. Devices should be added
392 in the device tree as subnodes of the p2sb.
395 bool "Enable power-sequencing drivers"
398 Power-sequencing drivers provide support for controlling power for
399 devices. They are typically referenced by a phandle from another
400 device. When the device is started up, its power sequence can be
404 bool "Enable power-sequencing drivers for SPL"
405 depends on SPL_MISC && PWRSEQ
407 Power-sequencing drivers provide support for controlling power for
408 devices. They are typically referenced by a phandle from another
409 device. When the device is started up, its power sequence can be
413 bool "Enable PCA9551 LED driver"
415 Enable driver for PCA9551 LED controller. This controller
416 is connected via I2C. So I2C needs to be enabled.
418 config PCA9551_I2C_ADDR
419 hex "I2C address of PCA9551 LED controller"
420 depends on PCA9551_LED
423 The I2C address of the PCA9551 LED controller.
426 bool "Enable STM32MP fuse wrapper providing the fuse API"
427 depends on ARCH_STM32MP && MISC
428 default y if CMD_FUSE
430 If you say Y here, you will get support for the fuse API (OTP)
431 for STM32MP architecture.
432 This API is needed for CMD_FUSE.
435 bool "Enable RCC driver for the STM32 SoC's family"
436 depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
438 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
439 block) is responsible of the management of the clock and reset
441 This driver is similar to an MFD driver in the Linux kernel.
444 bool "Enable support for the Tegra CAR driver"
445 depends on TEGRA_NO_BPMP
447 The Tegra CAR (Clock and Reset Controller) is a HW module that
448 controls almost all clocks and resets in a Tegra SoC.
451 bool "Enable support for the Tegra186 BPMP driver"
454 The Tegra BPMP (Boot and Power Management Processor) is a separate
455 auxiliary CPU embedded into Tegra to perform power management work,
456 and controls related features such as clocks, resets, power domains,
457 PMIC I2C bus, etc. This driver provides the core low-level
458 communication path by which feature-specific drivers (such as clock)
459 can make requests to the BPMP. This driver is similar to an MFD
460 driver in the Linux kernel.
463 bool "Enable support for test drivers"
466 This enables drivers and uclasses that provides a way of testing the
467 operations of memory allocation and driver/uclass methods in driver
468 model. This should only be enabled for testing as it is not useful for
471 config USB_HUB_USB251XB
472 tristate "USB251XB Hub Controller Configuration Driver"
475 This option enables support for configuration via SMBus of the
476 Microchip USB251x/xBi USB 2.0 Hub Controller series. Configuration
477 parameters may be set in devicetree or platform data.
478 Say Y or M here if you need to configure such a device via SMBus.
481 bool "Enable TWL4030 LED controller"
483 Enable this to add support for the TWL4030 LED controller.
485 config WINBOND_W83627
486 bool "Enable Winbond Super I/O driver"
488 If you say Y here, you will get support for the Winbond
489 W83627 Super I/O driver. This can be used to enable the
490 legacy UART or other devices in the Winbond Super IO chips
496 Hidden option to enable QEMU fw_cfg interface and uclass. This will
497 be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
503 Hidden option to enable PIO QEMU fw_cfg interface. This will be
504 selected by the appropriate QEMU board.
510 Hidden option to enable MMIO QEMU fw_cfg interface. This will be
511 selected by the appropriate QEMU board.
514 bool "Enable driver for generic I2C-attached EEPROMs"
517 Enable a generic driver for EEPROMs attached via I2C.
520 config SPL_I2C_EEPROM
521 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
524 This option is an SPL-variant of the I2C_EEPROM option.
525 See the help of I2C_EEPROM for details.
527 config SYS_I2C_EEPROM_ADDR
528 hex "Chip address of the EEPROM device"
529 depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
534 config SYS_I2C_EEPROM_ADDR_OVERFLOW
535 hex "EEPROM Address Overflow"
538 EEPROM chips that implement "address overflow" are ones
539 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
540 address and the extra bits end up in the "chip address" bit
541 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
546 config GDSYS_RXAUI_CTRL
547 bool "Enable gdsys RXAUI control driver"
550 Support gdsys FPGA's RXAUI control.
553 bool "Enable gdsys IOEP driver"
556 Support gdsys FPGA's IO endpoint driver.
558 config MPC83XX_SERDES
559 bool "Enable MPC83xx serdes driver"
562 Support for serdes found on MPC83xx SoCs.
565 bool "Enable loader driver for file system"
567 This is file system generic loader which can be used to load
568 the file image from the storage into target such as memory.
570 The consumer driver would then use this loader to program whatever,
574 bool "Enable loader driver for file system"
577 This is file system generic loader which can be used to load
578 the file image from the storage into target such as memory.
580 The consumer driver would then use this loader to program whatever,
584 bool "Enable gdsys SOC driver"
587 Support for gdsys IHS SOC, a simple bus associated with each gdsys
588 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
589 register maps are contained within the FPGA's register map.
592 bool "Enable IHS FPGA driver"
595 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
596 gdsys devices, which supply the majority of the functionality offered
597 by the devices. This driver supports both CON and CPU variants of the
598 devices, depending on the device tree entry.
600 bool "Enable K3 ESM driver"
603 Support ESM (Error Signaling Module) on TI K3 SoCs.
605 config MICROCHIP_FLEXCOM
606 bool "Enable Microchip Flexcom driver"
609 The Atmel Flexcom is just a wrapper which embeds a SPI controller,
610 an I2C controller and an USART.
611 Only one function can be used at a time and is chosen at boot time
612 according to the device tree.
615 depends on ARCH_K3 && SPL_DM_REGULATOR
616 bool "AVS class 0 support for K3 devices"
618 K3 devices have the optimized voltage values for the main voltage
619 domains stored in efuse within the VTM IP. This driver reads the
620 optimized voltage from the efuse, so that it can be programmed
621 to the PMIC on board.
624 bool "Enable PMIC ESM driver"
627 Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
628 typically to reboot the board in error condition.
634 bool "Enable Kontron sl28cpld multi-function driver"
637 Support for the Kontron sl28cpld management controller. This is
638 the base driver which provides common access methods for the