2 # Multifunction miscellaneous devices
5 menu "Multifunction device drivers"
8 bool "Enable Driver Model for Misc drivers"
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
17 bool "Enable Driver Model for Misc drivers in SPL"
20 Enable driver model for miscellaneous devices. This class is
21 used only for those do not fit other more general classes. A
22 set of generic read, write and ioctl methods may be used to
26 bool "Enable Driver Model for Misc drivers in TPL"
29 Enable driver model for miscellaneous devices. This class is
30 used only for those do not fit other more general classes. A
31 set of generic read, write and ioctl methods may be used to
35 bool "Altera Sysid support"
38 Select this to enable a sysid for Altera devices. Please find
39 details on the "Embedded Peripherals IP User Guide" of Altera.
42 bool "Support for Atmel ATSHA204A module"
45 Enable support for I2C connected Atmel's ATSHA204A
46 CryptoAuthentication module found for example on the Turris Omnia
50 bool "Rockchip e-fuse support"
53 Enable (read-only) access for the e-fuse block found in Rockchip
54 SoCs: accesses can either be made using byte addressing and a length
55 or through child-nodes that are generated based on the e-fuse map
56 retrieved from the DTS.
58 This driver currently supports the RK3399 only, but can easily be
59 extended (by porting the read function from the Linux kernel sources)
60 to support other recent Rockchip devices.
62 config VEXPRESS_CONFIG
63 bool "Enable support for Arm Versatile Express config bus"
66 If you say Y here, you will get support for accessing the
67 configuration bus on the Arm Versatile Express boards via
71 bool "Enable crosec command"
74 Enable command-line access to the Chrome OS EC (Embedded
75 Controller). This provides the 'crosec' command which has
76 a number of sub-commands for performing EC tasks such as
77 updating its flash, accessing a small saved context area
78 and talking to the I2C bus behind the EC (if there is one).
81 bool "Enable Chrome OS EC"
83 Enable access to the Chrome OS EC. This is a separate
84 microcontroller typically available on a SPI bus on Chromebooks. It
85 provides access to the keyboard, some internal storage and may
86 control access to the battery and main PMIC depending on the
87 device. You can use the 'crosec' command to access it.
90 bool "Enable Chrome OS EC in SPL"
92 Enable access to the Chrome OS EC in SPL. This is a separate
93 microcontroller typically available on a SPI bus on Chromebooks. It
94 provides access to the keyboard, some internal storage and may
95 control access to the battery and main PMIC depending on the
96 device. You can use the 'crosec' command to access it.
99 bool "Enable Chrome OS EC in TPL"
101 Enable access to the Chrome OS EC in TPL. This is a separate
102 microcontroller typically available on a SPI bus on Chromebooks. It
103 provides access to the keyboard, some internal storage and may
104 control access to the battery and main PMIC depending on the
105 device. You can use the 'crosec' command to access it.
108 bool "Enable Chrome OS EC I2C driver"
111 Enable I2C access to the Chrome OS EC. This is used on older
112 ARM Chromebooks such as snow and spring before the standard bus
113 changed to SPI. The EC will accept commands across the I2C using
114 a special message protocol, and provide responses.
117 bool "Enable Chrome OS EC LPC driver"
120 Enable I2C access to the Chrome OS EC. This is used on x86
121 Chromebooks such as link and falco. The keyboard is provided
122 through a legacy port interface, so on x86 machines the main
123 function of the EC is power and thermal management.
125 config SPL_CROS_EC_LPC
126 bool "Enable Chrome OS EC LPC driver in SPL"
129 Enable I2C access to the Chrome OS EC. This is used on x86
130 Chromebooks such as link and falco. The keyboard is provided
131 through a legacy port interface, so on x86 machines the main
132 function of the EC is power and thermal management.
134 config TPL_CROS_EC_LPC
135 bool "Enable Chrome OS EC LPC driver in TPL"
138 Enable I2C access to the Chrome OS EC. This is used on x86
139 Chromebooks such as link and falco. The keyboard is provided
140 through a legacy port interface, so on x86 machines the main
141 function of the EC is power and thermal management.
143 config CROS_EC_SANDBOX
144 bool "Enable Chrome OS EC sandbox driver"
145 depends on CROS_EC && SANDBOX
147 Enable a sandbox emulation of the Chrome OS EC. This supports
148 keyboard (use the -l flag to enable the LCD), verified boot context,
149 EC flash read/write/erase support and a few other things. It is
150 enough to perform a Chrome OS verified boot on sandbox.
152 config SPL_CROS_EC_SANDBOX
153 bool "Enable Chrome OS EC sandbox driver in SPL"
154 depends on SPL_CROS_EC && SANDBOX
156 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
157 keyboard (use the -l flag to enable the LCD), verified boot context,
158 EC flash read/write/erase support and a few other things. It is
159 enough to perform a Chrome OS verified boot on sandbox.
161 config TPL_CROS_EC_SANDBOX
162 bool "Enable Chrome OS EC sandbox driver in TPL"
163 depends on TPL_CROS_EC && SANDBOX
165 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
166 keyboard (use the -l flag to enable the LCD), verified boot context,
167 EC flash read/write/erase support and a few other things. It is
168 enough to perform a Chrome OS verified boot on sandbox.
171 bool "Enable Chrome OS EC SPI driver"
174 Enable SPI access to the Chrome OS EC. This is used on newer
175 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
176 provides a faster and more robust interface than I2C but the bugs
177 are less interesting.
180 bool "Enable support for DS4510 CPU supervisor"
182 Enable support for the Maxim DS4510 CPU supervisor. It has an
183 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
184 and a configurable timer for the supervisor function. The device is
188 bool "Enable FSL SEC_MON Driver"
190 Freescale Security Monitor block is responsible for monitoring
192 Security Monitor can be transitioned on any security failures,
193 like software violations or hardware security violations.
196 bool "Ingenic JZ4780 eFUSE support"
197 depends on ARCH_JZ47XX
199 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
202 bool "Enable MXC OCOTP Driver"
203 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_VF610
206 If you say Y here, you will get support for the One Time
207 Programmable memory pages that are stored on the some
208 Freescale i.MX processors.
210 config NUVOTON_NCT6102D
211 bool "Enable Nuvoton NCT6102D Super I/O driver"
213 If you say Y here, you will get support for the Nuvoton
214 NCT6102D Super I/O driver. This can be used to enable or
215 disable the legacy UART, the watchdog or other devices
216 in the Nuvoton Super IO chips on X86 platforms.
219 bool "Enable power-sequencing drivers"
222 Power-sequencing drivers provide support for controlling power for
223 devices. They are typically referenced by a phandle from another
224 device. When the device is started up, its power sequence can be
228 bool "Enable power-sequencing drivers for SPL"
231 Power-sequencing drivers provide support for controlling power for
232 devices. They are typically referenced by a phandle from another
233 device. When the device is started up, its power sequence can be
237 bool "Enable PCA9551 LED driver"
239 Enable driver for PCA9551 LED controller. This controller
240 is connected via I2C. So I2C needs to be enabled.
242 config PCA9551_I2C_ADDR
243 hex "I2C address of PCA9551 LED controller"
244 depends on PCA9551_LED
247 The I2C address of the PCA9551 LED controller.
250 bool "Enable STM32MP fuse wrapper providing the fuse API"
251 depends on ARCH_STM32MP && MISC
252 default y if CMD_FUSE
254 If you say Y here, you will get support for the fuse API (OTP)
255 for STM32MP architecture.
256 This API is needed for CMD_FUSE.
259 bool "Enable RCC driver for the STM32 SoC's family"
260 depends on (STM32 || ARCH_STM32MP) && MISC
262 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
263 block) is responsible of the management of the clock and reset
265 This driver is similar to an MFD driver in the Linux kernel.
268 bool "Enable support for the Tegra CAR driver"
269 depends on TEGRA_NO_BPMP
271 The Tegra CAR (Clock and Reset Controller) is a HW module that
272 controls almost all clocks and resets in a Tegra SoC.
275 bool "Enable support for the Tegra186 BPMP driver"
278 The Tegra BPMP (Boot and Power Management Processor) is a separate
279 auxiliary CPU embedded into Tegra to perform power management work,
280 and controls related features such as clocks, resets, power domains,
281 PMIC I2C bus, etc. This driver provides the core low-level
282 communication path by which feature-specific drivers (such as clock)
283 can make requests to the BPMP. This driver is similar to an MFD
284 driver in the Linux kernel.
287 bool "Enable TWL4030 LED controller"
289 Enable this to add support for the TWL4030 LED controller.
291 config WINBOND_W83627
292 bool "Enable Winbond Super I/O driver"
294 If you say Y here, you will get support for the Winbond
295 W83627 Super I/O driver. This can be used to enable the
296 legacy UART or other devices in the Winbond Super IO chips
302 Hidden option to enable QEMU fw_cfg interface. This will be selected by
303 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
306 bool "Enable driver for generic I2C-attached EEPROMs"
309 Enable a generic driver for EEPROMs attached via I2C.
312 config SPL_I2C_EEPROM
313 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
314 depends on MISC && SPL && SPL_DM
316 This option is an SPL-variant of the I2C_EEPROM option.
317 See the help of I2C_EEPROM for details.
319 config ZYNQ_GEM_I2C_MAC_OFFSET
320 hex "Set the I2C MAC offset"
324 Set the MAC offset for i2C.
328 config SYS_I2C_EEPROM_ADDR
329 hex "Chip address of the EEPROM device"
332 config SYS_I2C_EEPROM_BUS
333 int "I2C bus of the EEPROM device."
336 config SYS_EEPROM_SIZE
337 int "Size in bytes of the EEPROM device"
340 config SYS_EEPROM_PAGE_WRITE_BITS
341 int "Number of bits used to address bytes in a single page"
344 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
345 A 64 byte page, for example would require six bits.
347 config SYS_EEPROM_PAGE_WRITE_DELAY_MS
348 int "Number of milliseconds to delay between page writes"
351 config SYS_I2C_EEPROM_ADDR_LEN
352 int "Length in bytes of the EEPROM memory array address"
355 Note: This is NOT the chip address length!
357 config SYS_I2C_EEPROM_ADDR_OVERFLOW
358 hex "EEPROM Address Overflow"
361 EEPROM chips that implement "address overflow" are ones
362 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
363 address and the extra bits end up in the "chip address" bit
364 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
369 config GDSYS_RXAUI_CTRL
370 bool "Enable gdsys RXAUI control driver"
373 Support gdsys FPGA's RXAUI control.
376 bool "Enable gdsys IOEP driver"
379 Support gdsys FPGA's IO endpoint driver.
381 config MPC83XX_SERDES
382 bool "Enable MPC83xx serdes driver"
385 Support for serdes found on MPC83xx SoCs.
388 bool "Enable loader driver for file system"
390 This is file system generic loader which can be used to load
391 the file image from the storage into target such as memory.
393 The consumer driver would then use this loader to program whatever,
397 bool "Enable gdsys SOC driver"
400 Support for gdsys IHS SOC, a simple bus associated with each gdsys
401 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
402 register maps are contained within the FPGA's register map.
405 bool "Enable IHS FPGA driver"
408 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
409 gdsys devices, which supply the majority of the functionality offered
410 by the devices. This driver supports both CON and CPU variants of the
411 devices, depending on the device tree entry.