2 # Multifunction miscellaneous devices
5 menu "Multifunction device drivers"
8 bool "Enable Driver Model for Misc drivers"
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
17 bool "Enable Driver Model for Misc drivers in SPL"
20 Enable driver model for miscellaneous devices. This class is
21 used only for those do not fit other more general classes. A
22 set of generic read, write and ioctl methods may be used to
26 bool "Enable Driver Model for Misc drivers in TPL"
29 Enable driver model for miscellaneous devices. This class is
30 used only for those do not fit other more general classes. A
31 set of generic read, write and ioctl methods may be used to
35 bool "Altera Sysid support"
38 Select this to enable a sysid for Altera devices. Please find
39 details on the "Embedded Peripherals IP User Guide" of Altera.
42 bool "Support for Atmel ATSHA204A module"
45 Enable support for I2C connected Atmel's ATSHA204A
46 CryptoAuthentication module found for example on the Turris Omnia
50 bool "Rockchip e-fuse support"
53 Enable (read-only) access for the e-fuse block found in Rockchip
54 SoCs: accesses can either be made using byte addressing and a length
55 or through child-nodes that are generated based on the e-fuse map
56 retrieved from the DTS.
58 This driver currently supports the RK3399 only, but can easily be
59 extended (by porting the read function from the Linux kernel sources)
60 to support other recent Rockchip devices.
63 bool "Rockchip OTP Support"
66 Enable (read-only) access for the one-time-programmable memory block
67 found in Rockchip SoCs: accesses can either be made using byte
68 addressing and a length or through child-nodes that are generated
69 based on the e-fuse map retrieved from the DTS.
72 bool "SiFive eMemory OTP driver"
75 Enable support for reading and writing the eMemory OTP on the
78 config VEXPRESS_CONFIG
79 bool "Enable support for Arm Versatile Express config bus"
82 If you say Y here, you will get support for accessing the
83 configuration bus on the Arm Versatile Express boards via
87 bool "Enable crosec command"
90 Enable command-line access to the Chrome OS EC (Embedded
91 Controller). This provides the 'crosec' command which has
92 a number of sub-commands for performing EC tasks such as
93 updating its flash, accessing a small saved context area
94 and talking to the I2C bus behind the EC (if there is one).
97 bool "Enable Chrome OS EC"
99 Enable access to the Chrome OS EC. This is a separate
100 microcontroller typically available on a SPI bus on Chromebooks. It
101 provides access to the keyboard, some internal storage and may
102 control access to the battery and main PMIC depending on the
103 device. You can use the 'crosec' command to access it.
106 bool "Enable Chrome OS EC in SPL"
109 Enable access to the Chrome OS EC in SPL. This is a separate
110 microcontroller typically available on a SPI bus on Chromebooks. It
111 provides access to the keyboard, some internal storage and may
112 control access to the battery and main PMIC depending on the
113 device. You can use the 'crosec' command to access it.
116 bool "Enable Chrome OS EC in TPL"
119 Enable access to the Chrome OS EC in TPL. This is a separate
120 microcontroller typically available on a SPI bus on Chromebooks. It
121 provides access to the keyboard, some internal storage and may
122 control access to the battery and main PMIC depending on the
123 device. You can use the 'crosec' command to access it.
126 bool "Enable Chrome OS EC I2C driver"
129 Enable I2C access to the Chrome OS EC. This is used on older
130 ARM Chromebooks such as snow and spring before the standard bus
131 changed to SPI. The EC will accept commands across the I2C using
132 a special message protocol, and provide responses.
135 bool "Enable Chrome OS EC LPC driver"
138 Enable I2C access to the Chrome OS EC. This is used on x86
139 Chromebooks such as link and falco. The keyboard is provided
140 through a legacy port interface, so on x86 machines the main
141 function of the EC is power and thermal management.
143 config SPL_CROS_EC_LPC
144 bool "Enable Chrome OS EC LPC driver in SPL"
147 Enable I2C access to the Chrome OS EC. This is used on x86
148 Chromebooks such as link and falco. The keyboard is provided
149 through a legacy port interface, so on x86 machines the main
150 function of the EC is power and thermal management.
152 config TPL_CROS_EC_LPC
153 bool "Enable Chrome OS EC LPC driver in TPL"
156 Enable I2C access to the Chrome OS EC. This is used on x86
157 Chromebooks such as link and falco. The keyboard is provided
158 through a legacy port interface, so on x86 machines the main
159 function of the EC is power and thermal management.
161 config CROS_EC_SANDBOX
162 bool "Enable Chrome OS EC sandbox driver"
163 depends on CROS_EC && SANDBOX
165 Enable a sandbox emulation of the Chrome OS EC. This supports
166 keyboard (use the -l flag to enable the LCD), verified boot context,
167 EC flash read/write/erase support and a few other things. It is
168 enough to perform a Chrome OS verified boot on sandbox.
170 config SPL_CROS_EC_SANDBOX
171 bool "Enable Chrome OS EC sandbox driver in SPL"
172 depends on SPL_CROS_EC && SANDBOX
174 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
175 keyboard (use the -l flag to enable the LCD), verified boot context,
176 EC flash read/write/erase support and a few other things. It is
177 enough to perform a Chrome OS verified boot on sandbox.
179 config TPL_CROS_EC_SANDBOX
180 bool "Enable Chrome OS EC sandbox driver in TPL"
181 depends on TPL_CROS_EC && SANDBOX
183 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
184 keyboard (use the -l flag to enable the LCD), verified boot context,
185 EC flash read/write/erase support and a few other things. It is
186 enough to perform a Chrome OS verified boot on sandbox.
189 bool "Enable Chrome OS EC SPI driver"
192 Enable SPI access to the Chrome OS EC. This is used on newer
193 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
194 provides a faster and more robust interface than I2C but the bugs
195 are less interesting.
198 bool "Enable support for DS4510 CPU supervisor"
200 Enable support for the Maxim DS4510 CPU supervisor. It has an
201 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
202 and a configurable timer for the supervisor function. The device is
206 bool "Enable FSL SEC_MON Driver"
208 Freescale Security Monitor block is responsible for monitoring
210 Security Monitor can be transitioned on any security failures,
211 like software violations or hardware security violations.
214 bool "Interrupt controller"
216 This enables support for interrupt controllers, including ITSS.
217 Some devices have extra features, such as Apollo Lake. The
218 device has its own uclass since there are several operations
222 bool "Ingenic JZ4780 eFUSE support"
223 depends on ARCH_JZ47XX
225 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
228 bool "Enable MXC OCOTP Driver"
229 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
232 If you say Y here, you will get support for the One Time
233 Programmable memory pages that are stored on the some
234 Freescale i.MX processors.
237 bool "Enable MXC OCOTP driver in SPL"
238 depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
241 If you say Y here, you will get support for the One Time
242 Programmable memory pages, that are stored on some
243 Freescale i.MX processors, in SPL.
245 config NUVOTON_NCT6102D
246 bool "Enable Nuvoton NCT6102D Super I/O driver"
248 If you say Y here, you will get support for the Nuvoton
249 NCT6102D Super I/O driver. This can be used to enable or
250 disable the legacy UART, the watchdog or other devices
251 in the Nuvoton Super IO chips on X86 platforms.
254 bool "Intel Primary to Sideband Bridge"
255 depends on X86 || SANDBOX
257 This enables support for the Intel Primary to Sideband Bridge,
258 abbreviated to P2SB. The P2SB is used to access various peripherals
259 such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
260 space. The space is segmented into different channels and peripherals
261 are accessed by device-specific means within those channels. Devices
262 should be added in the device tree as subnodes of the P2SB. A
263 Peripheral Channel Register? (PCR) API is provided to access those
264 devices - see pcr_readl(), etc.
267 bool "Intel Primary to Sideband Bridge in SPL"
268 depends on SPL && (X86 || SANDBOX)
270 The Primary to Sideband Bridge is used to access various peripherals
271 through memory-mapped I/O in a large chunk of PCI space. The space is
272 segmented into different channels and peripherals are accessed by
273 device-specific means within those channels. Devices should be added
274 in the device tree as subnodes of the p2sb.
277 bool "Intel Primary to Sideband Bridge in TPL"
278 depends on TPL && (X86 || SANDBOX)
280 The Primary to Sideband Bridge is used to access various peripherals
281 through memory-mapped I/O in a large chunk of PCI space. The space is
282 segmented into different channels and peripherals are accessed by
283 device-specific means within those channels. Devices should be added
284 in the device tree as subnodes of the p2sb.
287 bool "Enable power-sequencing drivers"
290 Power-sequencing drivers provide support for controlling power for
291 devices. They are typically referenced by a phandle from another
292 device. When the device is started up, its power sequence can be
296 bool "Enable power-sequencing drivers for SPL"
299 Power-sequencing drivers provide support for controlling power for
300 devices. They are typically referenced by a phandle from another
301 device. When the device is started up, its power sequence can be
305 bool "Enable PCA9551 LED driver"
307 Enable driver for PCA9551 LED controller. This controller
308 is connected via I2C. So I2C needs to be enabled.
310 config PCA9551_I2C_ADDR
311 hex "I2C address of PCA9551 LED controller"
312 depends on PCA9551_LED
315 The I2C address of the PCA9551 LED controller.
318 bool "Enable STM32MP fuse wrapper providing the fuse API"
319 depends on ARCH_STM32MP && MISC
320 default y if CMD_FUSE
322 If you say Y here, you will get support for the fuse API (OTP)
323 for STM32MP architecture.
324 This API is needed for CMD_FUSE.
327 bool "Enable RCC driver for the STM32 SoC's family"
328 depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
330 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
331 block) is responsible of the management of the clock and reset
333 This driver is similar to an MFD driver in the Linux kernel.
336 bool "Enable support for the Tegra CAR driver"
337 depends on TEGRA_NO_BPMP
339 The Tegra CAR (Clock and Reset Controller) is a HW module that
340 controls almost all clocks and resets in a Tegra SoC.
343 bool "Enable support for the Tegra186 BPMP driver"
346 The Tegra BPMP (Boot and Power Management Processor) is a separate
347 auxiliary CPU embedded into Tegra to perform power management work,
348 and controls related features such as clocks, resets, power domains,
349 PMIC I2C bus, etc. This driver provides the core low-level
350 communication path by which feature-specific drivers (such as clock)
351 can make requests to the BPMP. This driver is similar to an MFD
352 driver in the Linux kernel.
355 bool "Enable support for test drivers"
358 This enables drivers and uclasses that provides a way of testing the
359 operations of memory allocation and driver/uclass methods in driver
360 model. This should only be enabled for testing as it is not useful for
364 bool "Enable TWL4030 LED controller"
366 Enable this to add support for the TWL4030 LED controller.
368 config WINBOND_W83627
369 bool "Enable Winbond Super I/O driver"
371 If you say Y here, you will get support for the Winbond
372 W83627 Super I/O driver. This can be used to enable the
373 legacy UART or other devices in the Winbond Super IO chips
379 Hidden option to enable QEMU fw_cfg interface and uclass. This will
380 be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
386 Hidden option to enable PIO QEMU fw_cfg interface. This will be
387 selected by the appropriate QEMU board.
393 Hidden option to enable MMIO QEMU fw_cfg interface. This will be
394 selected by the appropriate QEMU board.
397 bool "Enable driver for generic I2C-attached EEPROMs"
400 Enable a generic driver for EEPROMs attached via I2C.
403 config SPL_I2C_EEPROM
404 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
405 depends on MISC && SPL && SPL_DM
407 This option is an SPL-variant of the I2C_EEPROM option.
408 See the help of I2C_EEPROM for details.
410 config SYS_I2C_EEPROM_ADDR
411 hex "Chip address of the EEPROM device"
412 depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
417 config SYS_I2C_EEPROM_ADDR_OVERFLOW
418 hex "EEPROM Address Overflow"
421 EEPROM chips that implement "address overflow" are ones
422 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
423 address and the extra bits end up in the "chip address" bit
424 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
429 config GDSYS_RXAUI_CTRL
430 bool "Enable gdsys RXAUI control driver"
433 Support gdsys FPGA's RXAUI control.
436 bool "Enable gdsys IOEP driver"
439 Support gdsys FPGA's IO endpoint driver.
441 config MPC83XX_SERDES
442 bool "Enable MPC83xx serdes driver"
445 Support for serdes found on MPC83xx SoCs.
448 bool "Enable loader driver for file system"
450 This is file system generic loader which can be used to load
451 the file image from the storage into target such as memory.
453 The consumer driver would then use this loader to program whatever,
457 bool "Enable loader driver for file system"
459 This is file system generic loader which can be used to load
460 the file image from the storage into target such as memory.
462 The consumer driver would then use this loader to program whatever,
466 bool "Enable gdsys SOC driver"
469 Support for gdsys IHS SOC, a simple bus associated with each gdsys
470 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
471 register maps are contained within the FPGA's register map.
474 bool "Enable IHS FPGA driver"
477 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
478 gdsys devices, which supply the majority of the functionality offered
479 by the devices. This driver supports both CON and CPU variants of the
480 devices, depending on the device tree entry.
482 bool "Enable K3 ESM driver"
485 Support ESM (Error Signaling Module) on TI K3 SoCs.
487 config MICROCHIP_FLEXCOM
488 bool "Enable Microchip Flexcom driver"
491 The Atmel Flexcom is just a wrapper which embeds a SPI controller,
492 an I2C controller and an USART.
493 Only one function can be used at a time and is chosen at boot time
494 according to the device tree.
497 depends on ARCH_K3 && SPL_DM_REGULATOR
498 bool "AVS class 0 support for K3 devices"
500 K3 devices have the optimized voltage values for the main voltage
501 domains stored in efuse within the VTM IP. This driver reads the
502 optimized voltage from the efuse, so that it can be programmed
503 to the PMIC on board.
506 bool "Enable PMIC ESM driver"
509 Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
510 typically to reboot the board in error condition.