drivers/mfd/wm831x-irq.c

   1 /*
   2  * wm831x-irq.c  --  Interrupt controller support for Wolfson WM831x PMICs
   3  *
   4  * Copyright 2009 Wolfson Microelectronics PLC.
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  *
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/i2c.h>
  18 #include <linux/irq.h>
  19 #include <linux/mfd/core.h>
  20 #include <linux/interrupt.h>
  21
  22 #include <linux/mfd/wm831x/core.h>
  23 #include <linux/mfd/wm831x/pdata.h>
  24 #include <linux/mfd/wm831x/irq.h>
  25
  26 #include <linux/delay.h>
  27
  28 /*
  29  * Since generic IRQs don't currently support interrupt controllers on
  30  * interrupt driven buses we don't use genirq but instead provide an
  31  * interface that looks very much like the standard ones.  This leads
  32  * to some bodges, including storing interrupt handler information in
  33  * the static irq_data table we use to look up the data for individual
  34  * interrupts, but hopefully won't last too long.
  35  */
  36
  37 struct wm831x_irq_data {
  38         int primary;
  39         int reg;
  40         int mask;
  41         irq_handler_t handler;
  42         void *handler_data;
  43 };
  44
  45 static struct wm831x_irq_data wm831x_irqs[] = {
  46         [WM831X_IRQ_TEMP_THW] = {
  47                 .primary = WM831X_TEMP_INT,
  48                 .reg = 1,
  49                 .mask = WM831X_TEMP_THW_EINT,
  50         },
  51         [WM831X_IRQ_GPIO_1] = {
  52                 .primary = WM831X_GP_INT,
  53                 .reg = 5,
  54                 .mask = WM831X_GP1_EINT,
  55         },
  56         [WM831X_IRQ_GPIO_2] = {
  57                 .primary = WM831X_GP_INT,
  58                 .reg = 5,
  59                 .mask = WM831X_GP2_EINT,
  60         },
  61         [WM831X_IRQ_GPIO_3] = {
  62                 .primary = WM831X_GP_INT,
  63                 .reg = 5,
  64                 .mask = WM831X_GP3_EINT,
  65         },
  66         [WM831X_IRQ_GPIO_4] = {
  67                 .primary = WM831X_GP_INT,
  68                 .reg = 5,
  69                 .mask = WM831X_GP4_EINT,
  70         },
  71         [WM831X_IRQ_GPIO_5] = {
  72                 .primary = WM831X_GP_INT,
  73                 .reg = 5,
  74                 .mask = WM831X_GP5_EINT,
  75         },
  76         [WM831X_IRQ_GPIO_6] = {
  77                 .primary = WM831X_GP_INT,
  78                 .reg = 5,
  79                 .mask = WM831X_GP6_EINT,
  80         },
  81         [WM831X_IRQ_GPIO_7] = {
  82                 .primary = WM831X_GP_INT,
  83                 .reg = 5,
  84                 .mask = WM831X_GP7_EINT,
  85         },
  86         [WM831X_IRQ_GPIO_8] = {
  87                 .primary = WM831X_GP_INT,
  88                 .reg = 5,
  89                 .mask = WM831X_GP8_EINT,
  90         },
  91         [WM831X_IRQ_GPIO_9] = {
  92                 .primary = WM831X_GP_INT,
  93                 .reg = 5,
  94                 .mask = WM831X_GP9_EINT,
  95         },
  96         [WM831X_IRQ_GPIO_10] = {
  97                 .primary = WM831X_GP_INT,
  98                 .reg = 5,
  99                 .mask = WM831X_GP10_EINT,
 100         },
 101         [WM831X_IRQ_GPIO_11] = {
 102                 .primary = WM831X_GP_INT,
 103                 .reg = 5,
 104                 .mask = WM831X_GP11_EINT,
 105         },
 106         [WM831X_IRQ_GPIO_12] = {
 107                 .primary = WM831X_GP_INT,
 108                 .reg = 5,
 109                 .mask = WM831X_GP12_EINT,
 110         },
 111         [WM831X_IRQ_GPIO_13] = {
 112                 .primary = WM831X_GP_INT,
 113                 .reg = 5,
 114                 .mask = WM831X_GP13_EINT,
 115         },
 116         [WM831X_IRQ_GPIO_14] = {
 117                 .primary = WM831X_GP_INT,
 118                 .reg = 5,
 119                 .mask = WM831X_GP14_EINT,
 120         },
 121         [WM831X_IRQ_GPIO_15] = {
 122                 .primary = WM831X_GP_INT,
 123                 .reg = 5,
 124                 .mask = WM831X_GP15_EINT,
 125         },
 126         [WM831X_IRQ_GPIO_16] = {
 127                 .primary = WM831X_GP_INT,
 128                 .reg = 5,
 129                 .mask = WM831X_GP16_EINT,
 130         },
 131         [WM831X_IRQ_ON] = {
 132                 .primary = WM831X_ON_PIN_INT,
 133                 .reg = 1,
 134                 .mask = WM831X_ON_PIN_EINT,
 135         },
 136         [WM831X_IRQ_PPM_SYSLO] = {
 137                 .primary = WM831X_PPM_INT,
 138                 .reg = 1,
 139                 .mask = WM831X_PPM_SYSLO_EINT,
 140         },
 141         [WM831X_IRQ_PPM_PWR_SRC] = {
 142                 .primary = WM831X_PPM_INT,
 143                 .reg = 1,
 144                 .mask = WM831X_PPM_PWR_SRC_EINT,
 145         },
 146         [WM831X_IRQ_PPM_USB_CURR] = {
 147                 .primary = WM831X_PPM_INT,
 148                 .reg = 1,
 149                 .mask = WM831X_PPM_USB_CURR_EINT,
 150         },
 151         [WM831X_IRQ_WDOG_TO] = {
 152                 .primary = WM831X_WDOG_INT,
 153                 .reg = 1,
 154                 .mask = WM831X_WDOG_TO_EINT,
 155         },
 156         [WM831X_IRQ_RTC_PER] = {
 157                 .primary = WM831X_RTC_INT,
 158                 .reg = 1,
 159                 .mask = WM831X_RTC_PER_EINT,
 160         },
 161         [WM831X_IRQ_RTC_ALM] = {
 162                 .primary = WM831X_RTC_INT,
 163                 .reg = 1,
 164                 .mask = WM831X_RTC_ALM_EINT,
 165         },
 166         [WM831X_IRQ_CHG_BATT_HOT] = {
 167                 .primary = WM831X_CHG_INT,
 168                 .reg = 2,
 169                 .mask = WM831X_CHG_BATT_HOT_EINT,
 170         },
 171         [WM831X_IRQ_CHG_BATT_COLD] = {
 172                 .primary = WM831X_CHG_INT,
 173                 .reg = 2,
 174                 .mask = WM831X_CHG_BATT_COLD_EINT,
 175         },
 176         [WM831X_IRQ_CHG_BATT_FAIL] = {
 177                 .primary = WM831X_CHG_INT,
 178                 .reg = 2,
 179                 .mask = WM831X_CHG_BATT_FAIL_EINT,
 180         },
 181         [WM831X_IRQ_CHG_OV] = {
 182                 .primary = WM831X_CHG_INT,
 183                 .reg = 2,
 184                 .mask = WM831X_CHG_OV_EINT,
 185         },
 186         [WM831X_IRQ_CHG_END] = {
 187                 .primary = WM831X_CHG_INT,
 188                 .reg = 2,
 189                 .mask = WM831X_CHG_END_EINT,
 190         },
 191         [WM831X_IRQ_CHG_TO] = {
 192                 .primary = WM831X_CHG_INT,
 193                 .reg = 2,
 194                 .mask = WM831X_CHG_TO_EINT,
 195         },
 196         [WM831X_IRQ_CHG_MODE] = {
 197                 .primary = WM831X_CHG_INT,
 198                 .reg = 2,
 199                 .mask = WM831X_CHG_MODE_EINT,
 200         },
 201         [WM831X_IRQ_CHG_START] = {
 202                 .primary = WM831X_CHG_INT,
 203                 .reg = 2,
 204                 .mask = WM831X_CHG_START_EINT,
 205         },
 206         [WM831X_IRQ_TCHDATA] = {
 207                 .primary = WM831X_TCHDATA_INT,
 208                 .reg = 1,
 209                 .mask = WM831X_TCHDATA_EINT,
 210         },
 211         [WM831X_IRQ_TCHPD] = {
 212                 .primary = WM831X_TCHPD_INT,
 213                 .reg = 1,
 214                 .mask = WM831X_TCHPD_EINT,
 215         },
 216         [WM831X_IRQ_AUXADC_DATA] = {
 217                 .primary = WM831X_AUXADC_INT,
 218                 .reg = 1,
 219                 .mask = WM831X_AUXADC_DATA_EINT,
 220         },
 221         [WM831X_IRQ_AUXADC_DCOMP1] = {
 222                 .primary = WM831X_AUXADC_INT,
 223                 .reg = 1,
 224                 .mask = WM831X_AUXADC_DCOMP1_EINT,
 225         },
 226         [WM831X_IRQ_AUXADC_DCOMP2] = {
 227                 .primary = WM831X_AUXADC_INT,
 228                 .reg = 1,
 229                 .mask = WM831X_AUXADC_DCOMP2_EINT,
 230         },
 231         [WM831X_IRQ_AUXADC_DCOMP3] = {
 232                 .primary = WM831X_AUXADC_INT,
 233                 .reg = 1,
 234                 .mask = WM831X_AUXADC_DCOMP3_EINT,
 235         },
 236         [WM831X_IRQ_AUXADC_DCOMP4] = {
 237                 .primary = WM831X_AUXADC_INT,
 238                 .reg = 1,
 239                 .mask = WM831X_AUXADC_DCOMP4_EINT,
 240         },
 241         [WM831X_IRQ_CS1] = {
 242                 .primary = WM831X_CS_INT,
 243                 .reg = 2,
 244                 .mask = WM831X_CS1_EINT,
 245         },
 246         [WM831X_IRQ_CS2] = {
 247                 .primary = WM831X_CS_INT,
 248                 .reg = 2,
 249                 .mask = WM831X_CS2_EINT,
 250         },
 251         [WM831X_IRQ_HC_DC1] = {
 252                 .primary = WM831X_HC_INT,
 253                 .reg = 4,
 254                 .mask = WM831X_HC_DC1_EINT,
 255         },
 256         [WM831X_IRQ_HC_DC2] = {
 257                 .primary = WM831X_HC_INT,
 258                 .reg = 4,
 259                 .mask = WM831X_HC_DC2_EINT,
 260         },
 261         [WM831X_IRQ_UV_LDO1] = {
 262                 .primary = WM831X_UV_INT,
 263                 .reg = 3,
 264                 .mask = WM831X_UV_LDO1_EINT,
 265         },
 266         [WM831X_IRQ_UV_LDO2] = {
 267                 .primary = WM831X_UV_INT,
 268                 .reg = 3,
 269                 .mask = WM831X_UV_LDO2_EINT,
 270         },
 271         [WM831X_IRQ_UV_LDO3] = {
 272                 .primary = WM831X_UV_INT,
 273                 .reg = 3,
 274                 .mask = WM831X_UV_LDO3_EINT,
 275         },
 276         [WM831X_IRQ_UV_LDO4] = {
 277                 .primary = WM831X_UV_INT,
 278                 .reg = 3,
 279                 .mask = WM831X_UV_LDO4_EINT,
 280         },
 281         [WM831X_IRQ_UV_LDO5] = {
 282                 .primary = WM831X_UV_INT,
 283                 .reg = 3,
 284                 .mask = WM831X_UV_LDO5_EINT,
 285         },
 286         [WM831X_IRQ_UV_LDO6] = {
 287                 .primary = WM831X_UV_INT,
 288                 .reg = 3,
 289                 .mask = WM831X_UV_LDO6_EINT,
 290         },
 291         [WM831X_IRQ_UV_LDO7] = {
 292                 .primary = WM831X_UV_INT,
 293                 .reg = 3,
 294                 .mask = WM831X_UV_LDO7_EINT,
 295         },
 296         [WM831X_IRQ_UV_LDO8] = {
 297                 .primary = WM831X_UV_INT,
 298                 .reg = 3,
 299                 .mask = WM831X_UV_LDO8_EINT,
 300         },
 301         [WM831X_IRQ_UV_LDO9] = {
 302                 .primary = WM831X_UV_INT,
 303                 .reg = 3,
 304                 .mask = WM831X_UV_LDO9_EINT,
 305         },
 306         [WM831X_IRQ_UV_LDO10] = {
 307                 .primary = WM831X_UV_INT,
 308                 .reg = 3,
 309                 .mask = WM831X_UV_LDO10_EINT,
 310         },
 311         [WM831X_IRQ_UV_DC1] = {
 312                 .primary = WM831X_UV_INT,
 313                 .reg = 4,
 314                 .mask = WM831X_UV_DC1_EINT,
 315         },
 316         [WM831X_IRQ_UV_DC2] = {
 317                 .primary = WM831X_UV_INT,
 318                 .reg = 4,
 319                 .mask = WM831X_UV_DC2_EINT,
 320         },
 321         [WM831X_IRQ_UV_DC3] = {
 322                 .primary = WM831X_UV_INT,
 323                 .reg = 4,
 324                 .mask = WM831X_UV_DC3_EINT,
 325         },
 326         [WM831X_IRQ_UV_DC4] = {
 327                 .primary = WM831X_UV_INT,
 328                 .reg = 4,
 329                 .mask = WM831X_UV_DC4_EINT,
 330         },
 331 };
 332
 333 static inline int irq_data_to_status_reg(struct wm831x_irq_data *irq_data)
 334 {
 335         return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg;
 336 }
 337
 338 static inline int irq_data_to_mask_reg(struct wm831x_irq_data *irq_data)
 339 {
 340         return WM831X_INTERRUPT_STATUS_1_MASK - 1 + irq_data->reg;
 341 }
 342
 343 static inline struct wm831x_irq_data *irq_to_wm831x_irq(struct wm831x *wm831x,
 344                                                         int irq)
 345 {
 346         return &wm831x_irqs[irq - wm831x->irq_base];
 347 }
 348
 349 static void wm831x_irq_lock(unsigned int irq)
 350 {
 351         struct wm831x *wm831x = get_irq_chip_data(irq);
 352
 353         mutex_lock(&wm831x->irq_lock);
 354 }
 355
 356 static void wm831x_irq_sync_unlock(unsigned int irq)
 357 {
 358         struct wm831x *wm831x = get_irq_chip_data(irq);
 359         int i;
 360
 361         for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
 362                 /* If there's been a change in the mask write it back
 363                  * to the hardware. */
 364                 if (wm831x->irq_masks_cur[i] != wm831x->irq_masks_cache[i]) {
 365                         wm831x->irq_masks_cache[i] = wm831x->irq_masks_cur[i];
 366                         wm831x_reg_write(wm831x,
 367                                          WM831X_INTERRUPT_STATUS_1_MASK + i,
 368                                          wm831x->irq_masks_cur[i]);
 369                 }
 370         }
 371
 372         mutex_unlock(&wm831x->irq_lock);
 373 }
 374
 375 static void wm831x_irq_unmask(unsigned int irq)
 376 {
 377         struct wm831x *wm831x = get_irq_chip_data(irq);
 378         struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x, irq);
 379
 380         wm831x->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
 381 }
 382
 383 static void wm831x_irq_mask(unsigned int irq)
 384 {
 385         struct wm831x *wm831x = get_irq_chip_data(irq);
 386         struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x, irq);
 387
 388         wm831x->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
 389 }
 390
 391 static struct irq_chip wm831x_irq_chip = {
 392         .name = "wm831x",
 393         .bus_lock = wm831x_irq_lock,
 394         .bus_sync_unlock = wm831x_irq_sync_unlock,
 395         .mask = wm831x_irq_mask,
 396         .unmask = wm831x_irq_unmask,
 397 };
 398
 399 /* The processing of the primary interrupt occurs in a thread so that
 400  * we can interact with the device over I2C or SPI. */
 401 static irqreturn_t wm831x_irq_thread(int irq, void *data)
 402 {
 403         struct wm831x *wm831x = data;
 404         unsigned int i;
 405         int primary;
 406         int status_regs[WM831X_NUM_IRQ_REGS] = { 0 };
 407         int read[WM831X_NUM_IRQ_REGS] = { 0 };
 408         int *status;
 409
 410         primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS);
 411         if (primary < 0) {
 412                 dev_err(wm831x->dev, "Failed to read system interrupt: %d\n",
 413                         primary);
 414                 goto out;
 415         }
 416
 417         for (i = 0; i < ARRAY_SIZE(wm831x_irqs); i++) {
 418                 int offset = wm831x_irqs[i].reg - 1;
 419
 420                 if (!(primary & wm831x_irqs[i].primary))
 421                         continue;
 422
 423                 status = &status_regs[offset];
 424
 425                 /* Hopefully there should only be one register to read
 426                  * each time otherwise we ought to do a block read. */
 427                 if (!read[offset]) {
 428                         *status = wm831x_reg_read(wm831x,
 429                                      irq_data_to_status_reg(&wm831x_irqs[i]));
 430                         if (*status < 0) {
 431                                 dev_err(wm831x->dev,
 432                                         "Failed to read IRQ status: %d\n",
 433                                         *status);
 434                                 goto out;
 435                         }
 436
 437                         read[offset] = 1;
 438                 }
 439
 440                 /* Report it if it isn't masked, or forget the status. */
 441                 if ((*status & ~wm831x->irq_masks_cur[offset])
 442                     & wm831x_irqs[i].mask)
 443                         handle_nested_irq(wm831x->irq_base + i);
 444                 else
 445                         *status &= ~wm831x_irqs[i].mask;
 446         }
 447
 448 out:
 449         for (i = 0; i < ARRAY_SIZE(status_regs); i++) {
 450                 if (status_regs[i])
 451                         wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1 + i,
 452                                          status_regs[i]);
 453         }
 454
 455         return IRQ_HANDLED;
 456 }
 457
 458 int wm831x_irq_init(struct wm831x *wm831x, int irq)
 459 {
 460         struct wm831x_pdata *pdata = wm831x->dev->platform_data;
 461         int i, cur_irq, ret;
 462
 463         mutex_init(&wm831x->irq_lock);
 464
 465         if (!irq) {
 466                 dev_warn(wm831x->dev,
 467                          "No interrupt specified - functionality limited\n");
 468                 return 0;
 469         }
 470
 471         if (!pdata || !pdata->irq_base) {
 472                 dev_err(wm831x->dev,
 473                         "No interrupt base specified, no interrupts\n");
 474                 return 0;
 475         }
 476
 477         wm831x->irq = irq;
 478         wm831x->irq_base = pdata->irq_base;
 479
 480         /* Mask the individual interrupt sources */
 481         for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
 482                 wm831x->irq_masks_cur[i] = 0xffff;
 483                 wm831x->irq_masks_cache[i] = 0xffff;
 484                 wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i,
 485                                  0xffff);
 486         }
 487
 488         /* Register them with genirq */
 489         for (cur_irq = wm831x->irq_base;
 490              cur_irq < ARRAY_SIZE(wm831x_irqs) + wm831x->irq_base;
 491              cur_irq++) {
 492                 set_irq_chip_data(cur_irq, wm831x);
 493                 set_irq_chip_and_handler(cur_irq, &wm831x_irq_chip,
 494                                          handle_edge_irq);
 495                 set_irq_nested_thread(cur_irq, 1);
 496
 497                 /* ARM needs us to explicitly flag the IRQ as valid
 498                  * and will set them noprobe when we do so. */
 499 #ifdef CONFIG_ARM
 500                 set_irq_flags(cur_irq, IRQF_VALID);
 501 #else
 502                 set_irq_noprobe(cur_irq);
 503 #endif
 504         }
 505
 506         ret = request_threaded_irq(irq, NULL, wm831x_irq_thread,
 507                                    IRQF_TRIGGER_LOW | IRQF_ONESHOT,
 508                                    "wm831x", wm831x);
 509         if (ret != 0) {
 510                 dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n",
 511                         irq, ret);
 512                 return ret;
 513         }
 514
 515         /* Enable top level interrupts, we mask at secondary level */
 516         wm831x_reg_write(wm831x, WM831X_SYSTEM_INTERRUPTS_MASK, 0);
 517
 518         return 0;
 519 }
 520
 521 void wm831x_irq_exit(struct wm831x *wm831x)
 522 {
 523         if (wm831x->irq)
 524                 free_irq(wm831x->irq, wm831x);
 525 }