2 * twl4030-irq.c - TWL4030/TPS659x0 irq support
4 * Copyright (C) 2005-2006 Texas Instruments, Inc.
6 * Modifications to defer interrupt handling to a kernel thread:
7 * Copyright (C) 2006 MontaVista Software, Inc.
9 * Based on tlv320aic23.c:
10 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
12 * Code cleanup and modifications to IRQ handler.
13 * by syed khasim <x0khasim@ti.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 #include <linux/init.h>
31 #include <linux/interrupt.h>
32 #include <linux/irq.h>
33 #include <linux/kthread.h>
34 #include <linux/slab.h>
36 #include <linux/i2c/twl.h>
40 * TWL4030 IRQ handling has two stages in hardware, and thus in software.
41 * The Primary Interrupt Handler (PIH) stage exposes status bits saying
42 * which Secondary Interrupt Handler (SIH) stage is raising an interrupt.
43 * SIH modules are more traditional IRQ components, which support per-IRQ
44 * enable/disable and trigger controls; they do most of the work.
46 * These chips are designed to support IRQ handling from two different
47 * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status
48 * and mask registers in the PIH and SIH modules.
50 * We set up IRQs starting at a platform-specified base, always starting
51 * with PIH and the SIH for PWR_INT and then usually adding GPIO:
52 * base + 0 .. base + 7 PIH
53 * base + 8 .. base + 15 SIH for PWR_INT
54 * base + 16 .. base + 33 SIH for GPIO
57 /* PIH register offsets */
58 #define REG_PIH_ISR_P1 0x01
59 #define REG_PIH_ISR_P2 0x02
60 #define REG_PIH_SIR 0x03 /* for testing */
63 /* Linux could (eventually) use either IRQ line */
68 u8 module; /* module id */
69 u8 control_offset; /* for SIH_CTRL */
72 u8 bits; /* valid in isr/imr */
73 u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */
76 u8 bytes_edr; /* bytelen of EDR */
78 u8 irq_lines; /* number of supported irq lines */
80 /* SIR ignored -- set interrupt, for testing only */
85 /* + 2 bytes padding */
88 static const struct sih *sih_modules;
89 static int nr_sih_modules;
91 #define SIH_INITIALIZER(modname, nbits) \
92 .module = TWL4030_MODULE_ ## modname, \
93 .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \
95 .bytes_ixr = DIV_ROUND_UP(nbits, 8), \
96 .edr_offset = TWL4030_ ## modname ## _EDR, \
97 .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \
100 .isr_offset = TWL4030_ ## modname ## _ISR1, \
101 .imr_offset = TWL4030_ ## modname ## _IMR1, \
104 .isr_offset = TWL4030_ ## modname ## _ISR2, \
105 .imr_offset = TWL4030_ ## modname ## _IMR2, \
108 /* register naming policies are inconsistent ... */
109 #define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1
110 #define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD
111 #define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT
114 /* Order in this table matches order in PIH_ISR. That is,
115 * BIT(n) in PIH_ISR is sih_modules[n].
117 /* sih_modules_twl4030 is used both in twl4030 and twl5030 */
118 static const struct sih sih_modules_twl4030[6] = {
121 .module = TWL4030_MODULE_GPIO,
122 .control_offset = REG_GPIO_SIH_CTRL,
124 .bits = TWL4030_GPIO_MAX,
126 /* Note: *all* of these IRQs default to no-trigger */
127 .edr_offset = REG_GPIO_EDR1,
131 .isr_offset = REG_GPIO_ISR1A,
132 .imr_offset = REG_GPIO_IMR1A,
134 .isr_offset = REG_GPIO_ISR1B,
135 .imr_offset = REG_GPIO_IMR1B,
141 SIH_INITIALIZER(KEYPAD_KEYP, 4)
145 .module = TWL4030_MODULE_INTERRUPTS,
146 .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL,
149 .edr_offset = TWL4030_INTERRUPTS_BCIEDR1,
150 /* Note: most of these IRQs default to no-trigger */
154 .isr_offset = TWL4030_INTERRUPTS_BCIISR1A,
155 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A,
157 .isr_offset = TWL4030_INTERRUPTS_BCIISR1B,
158 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B,
163 SIH_INITIALIZER(MADC, 4)
166 /* USB doesn't use the same SIH organization */
172 SIH_INITIALIZER(INT_PWR, 8)
174 /* there are no SIH modules #6 or #7 ... */
177 static const struct sih sih_modules_twl5031[8] = {
180 .module = TWL4030_MODULE_GPIO,
181 .control_offset = REG_GPIO_SIH_CTRL,
183 .bits = TWL4030_GPIO_MAX,
185 /* Note: *all* of these IRQs default to no-trigger */
186 .edr_offset = REG_GPIO_EDR1,
190 .isr_offset = REG_GPIO_ISR1A,
191 .imr_offset = REG_GPIO_IMR1A,
193 .isr_offset = REG_GPIO_ISR1B,
194 .imr_offset = REG_GPIO_IMR1B,
200 SIH_INITIALIZER(KEYPAD_KEYP, 4)
204 .module = TWL5031_MODULE_INTERRUPTS,
205 .control_offset = TWL5031_INTERRUPTS_BCISIHCTRL,
208 .edr_offset = TWL5031_INTERRUPTS_BCIEDR1,
209 /* Note: most of these IRQs default to no-trigger */
213 .isr_offset = TWL5031_INTERRUPTS_BCIISR1,
214 .imr_offset = TWL5031_INTERRUPTS_BCIIMR1,
216 .isr_offset = TWL5031_INTERRUPTS_BCIISR2,
217 .imr_offset = TWL5031_INTERRUPTS_BCIIMR2,
222 SIH_INITIALIZER(MADC, 4)
225 /* USB doesn't use the same SIH organization */
231 SIH_INITIALIZER(INT_PWR, 8)
235 * ACI doesn't use the same SIH organization.
236 * For example, it supports only one interrupt line
239 .module = TWL5031_MODULE_ACCESSORY,
244 .isr_offset = TWL5031_ACIIDR_LSB,
245 .imr_offset = TWL5031_ACIIMR_LSB,
252 .module = TWL5031_MODULE_ACCESSORY,
253 .control_offset = TWL5031_ACCSIHCTRL,
256 .edr_offset = TWL5031_ACCEDR1,
257 /* Note: most of these IRQs default to no-trigger */
261 .isr_offset = TWL5031_ACCISR1,
262 .imr_offset = TWL5031_ACCIMR1,
264 .isr_offset = TWL5031_ACCISR2,
265 .imr_offset = TWL5031_ACCIMR2,
270 #undef TWL4030_MODULE_KEYPAD_KEYP
271 #undef TWL4030_MODULE_INT_PWR
272 #undef TWL4030_INT_PWR_EDR
274 /*----------------------------------------------------------------------*/
276 static unsigned twl4030_irq_base;
278 static struct completion irq_event;
281 * This thread processes interrupts reported by the Primary Interrupt Handler.
283 static int twl4030_irq_thread(void *data)
285 long irq = (long)data;
286 static unsigned i2c_errors;
287 static const unsigned max_i2c_errors = 100;
290 current->flags |= PF_NOFREEZE;
292 while (!kthread_should_stop()) {
297 /* Wait for IRQ, then read PIH irq status (also blocking) */
298 wait_for_completion_interruptible(&irq_event);
300 ret = twl_i2c_read_u8(TWL4030_MODULE_PIH, &pih_isr,
303 pr_warning("twl4030: I2C error %d reading PIH ISR\n",
305 if (++i2c_errors >= max_i2c_errors) {
306 printk(KERN_ERR "Maximum I2C error count"
307 " exceeded. Terminating %s.\n",
311 complete(&irq_event);
315 /* these handlers deal with the relevant SIH irq status */
317 for (module_irq = twl4030_irq_base;
319 pih_isr >>= 1, module_irq++) {
321 struct irq_desc *d = irq_to_desc(module_irq);
324 pr_err("twl4030: Invalid SIH IRQ: %d\n",
329 /* These can't be masked ... always warn
330 * if we get any surprises.
332 if (d->status & IRQ_DISABLED)
333 note_interrupt(module_irq, d,
336 d->handle_irq(module_irq, d);
348 * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt.
349 * This is a chained interrupt, so there is no desc->action method for it.
350 * Now we need to query the interrupt controller in the twl4030 to determine
351 * which module is generating the interrupt request. However, we can't do i2c
352 * transactions in interrupt context, so we must defer that work to a kernel
353 * thread. All we do here is acknowledge and mask the interrupt and wakeup
356 static irqreturn_t handle_twl4030_pih(int irq, void *devid)
358 /* Acknowledge, clear *AND* mask the interrupt... */
359 disable_irq_nosync(irq);
363 /*----------------------------------------------------------------------*/
366 * twl4030_init_sih_modules() ... start from a known state where no
367 * IRQs will be coming in, and where we can quickly enable them then
368 * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL.
370 * NOTE: we don't touch EDR registers here; they stay with hardware
371 * defaults or whatever the last value was. Note that when both EDR
372 * bits for an IRQ are clear, that's as if its IMR bit is set...
374 static int twl4030_init_sih_modules(unsigned line)
376 const struct sih *sih;
381 /* line 0 == int1_n signal; line 1 == int2_n signal */
387 /* disable all interrupts on our line */
388 memset(buf, 0xff, sizeof buf);
390 for (i = 0; i < nr_sih_modules; i++, sih++) {
392 /* skip USB -- it's funky */
396 /* Not all the SIH modules support multiple interrupt lines */
397 if (sih->irq_lines <= line)
400 status = twl_i2c_write(sih->module, buf,
401 sih->mask[line].imr_offset, sih->bytes_ixr);
403 pr_err("twl4030: err %d initializing %s %s\n",
404 status, sih->name, "IMR");
406 /* Maybe disable "exclusive" mode; buffer second pending irq;
407 * set Clear-On-Read (COR) bit.
409 * NOTE that sometimes COR polarity is documented as being
410 * inverted: for MADC and BCI, COR=1 means "clear on write".
411 * And for PWR_INT it's not documented...
414 status = twl_i2c_write_u8(sih->module,
415 TWL4030_SIH_CTRL_COR_MASK,
416 sih->control_offset);
418 pr_err("twl4030: err %d initializing %s %s\n",
419 status, sih->name, "SIH_CTRL");
424 for (i = 0; i < nr_sih_modules; i++, sih++) {
432 /* Not all the SIH modules support multiple interrupt lines */
433 if (sih->irq_lines <= line)
436 /* Clear pending interrupt status. Either the read was
437 * enough, or we need to write those bits. Repeat, in
438 * case an IRQ is pending (PENDDIS=0) ... that's not
439 * uncommon with PWR_INT.PWRON.
441 for (j = 0; j < 2; j++) {
442 status = twl_i2c_read(sih->module, rxbuf,
443 sih->mask[line].isr_offset, sih->bytes_ixr);
445 pr_err("twl4030: err %d initializing %s %s\n",
446 status, sih->name, "ISR");
449 status = twl_i2c_write(sih->module, buf,
450 sih->mask[line].isr_offset,
452 /* else COR=1 means read sufficed.
453 * (for most SIH modules...)
461 static inline void activate_irq(int irq)
464 /* ARM requires an extra step to clear IRQ_NOREQUEST, which it
465 * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE.
467 set_irq_flags(irq, IRQF_VALID);
469 /* same effect on other architectures */
470 set_irq_noprobe(irq);
474 /*----------------------------------------------------------------------*/
476 static DEFINE_SPINLOCK(sih_agent_lock);
478 static struct workqueue_struct *wq;
482 const struct sih *sih;
485 bool imr_change_pending;
486 struct work_struct mask_work;
489 struct work_struct edge_work;
492 static void twl4030_sih_do_mask(struct work_struct *work)
494 struct sih_agent *agent;
495 const struct sih *sih;
502 agent = container_of(work, struct sih_agent, mask_work);
504 /* see what work we have */
505 spin_lock_irq(&sih_agent_lock);
506 if (agent->imr_change_pending) {
508 /* byte[0] gets overwritten as we write ... */
509 imr.word = cpu_to_le32(agent->imr << 8);
510 agent->imr_change_pending = false;
513 spin_unlock_irq(&sih_agent_lock);
517 /* write the whole mask ... simpler than subsetting it */
518 status = twl_i2c_write(sih->module, imr.bytes,
519 sih->mask[irq_line].imr_offset, sih->bytes_ixr);
521 pr_err("twl4030: %s, %s --> %d\n", __func__,
525 static void twl4030_sih_do_edge(struct work_struct *work)
527 struct sih_agent *agent;
528 const struct sih *sih;
533 agent = container_of(work, struct sih_agent, edge_work);
535 /* see what work we have */
536 spin_lock_irq(&sih_agent_lock);
537 edge_change = agent->edge_change;
538 agent->edge_change = 0;
539 sih = edge_change ? agent->sih : NULL;
540 spin_unlock_irq(&sih_agent_lock);
544 /* Read, reserving first byte for write scratch. Yes, this
545 * could be cached for some speedup ... but be careful about
546 * any processor on the other IRQ line, EDR registers are
549 status = twl_i2c_read(sih->module, bytes + 1,
550 sih->edr_offset, sih->bytes_edr);
552 pr_err("twl4030: %s, %s --> %d\n", __func__,
557 /* Modify only the bits we know must change */
558 while (edge_change) {
559 int i = fls(edge_change) - 1;
560 struct irq_desc *d = irq_to_desc(i + agent->irq_base);
561 int byte = 1 + (i >> 2);
562 int off = (i & 0x3) * 2;
565 pr_err("twl4030: Invalid IRQ: %d\n",
566 i + agent->irq_base);
570 bytes[byte] &= ~(0x03 << off);
572 raw_spin_lock_irq(&d->lock);
573 if (d->status & IRQ_TYPE_EDGE_RISING)
574 bytes[byte] |= BIT(off + 1);
575 if (d->status & IRQ_TYPE_EDGE_FALLING)
576 bytes[byte] |= BIT(off + 0);
577 raw_spin_unlock_irq(&d->lock);
579 edge_change &= ~BIT(i);
583 status = twl_i2c_write(sih->module, bytes,
584 sih->edr_offset, sih->bytes_edr);
586 pr_err("twl4030: %s, %s --> %d\n", __func__,
590 /*----------------------------------------------------------------------*/
593 * All irq_chip methods get issued from code holding irq_desc[irq].lock,
594 * which can't perform the underlying I2C operations (because they sleep).
595 * So we must hand them off to a thread (workqueue) and cope with asynch
596 * completion, potentially including some re-ordering, of these requests.
599 static void twl4030_sih_mask(unsigned irq)
601 struct sih_agent *sih = get_irq_chip_data(irq);
604 spin_lock_irqsave(&sih_agent_lock, flags);
605 sih->imr |= BIT(irq - sih->irq_base);
606 sih->imr_change_pending = true;
607 queue_work(wq, &sih->mask_work);
608 spin_unlock_irqrestore(&sih_agent_lock, flags);
611 static void twl4030_sih_unmask(unsigned irq)
613 struct sih_agent *sih = get_irq_chip_data(irq);
616 spin_lock_irqsave(&sih_agent_lock, flags);
617 sih->imr &= ~BIT(irq - sih->irq_base);
618 sih->imr_change_pending = true;
619 queue_work(wq, &sih->mask_work);
620 spin_unlock_irqrestore(&sih_agent_lock, flags);
623 static int twl4030_sih_set_type(unsigned irq, unsigned trigger)
625 struct sih_agent *sih = get_irq_chip_data(irq);
626 struct irq_desc *desc = irq_to_desc(irq);
630 pr_err("twl4030: Invalid IRQ: %d\n", irq);
634 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
637 spin_lock_irqsave(&sih_agent_lock, flags);
638 if ((desc->status & IRQ_TYPE_SENSE_MASK) != trigger) {
639 desc->status &= ~IRQ_TYPE_SENSE_MASK;
640 desc->status |= trigger;
641 sih->edge_change |= BIT(irq - sih->irq_base);
642 queue_work(wq, &sih->edge_work);
644 spin_unlock_irqrestore(&sih_agent_lock, flags);
648 static struct irq_chip twl4030_sih_irq_chip = {
650 .mask = twl4030_sih_mask,
651 .unmask = twl4030_sih_unmask,
652 .set_type = twl4030_sih_set_type,
655 /*----------------------------------------------------------------------*/
657 static inline int sih_read_isr(const struct sih *sih)
665 /* FIXME need retry-on-error ... */
668 status = twl_i2c_read(sih->module, isr.bytes,
669 sih->mask[irq_line].isr_offset, sih->bytes_ixr);
671 return (status < 0) ? status : le32_to_cpu(isr.word);
675 * Generic handler for SIH interrupts ... we "know" this is called
676 * in task context, with IRQs enabled.
678 static void handle_twl4030_sih(unsigned irq, struct irq_desc *desc)
680 struct sih_agent *agent = get_irq_data(irq);
681 const struct sih *sih = agent->sih;
684 /* reading ISR acks the IRQs, using clear-on-read mode */
686 isr = sih_read_isr(sih);
690 pr_err("twl4030: %s SIH, read ISR error %d\n",
692 /* REVISIT: recover; eventually mask it all, etc */
702 generic_handle_irq(agent->irq_base + irq);
704 pr_err("twl4030: %s SIH, invalid ISR bit %d\n",
709 static unsigned twl4030_irq_next;
711 /* returns the first IRQ used by this SIH bank,
714 int twl4030_sih_setup(int module)
717 const struct sih *sih = NULL;
718 struct sih_agent *agent;
720 int status = -EINVAL;
721 unsigned irq_base = twl4030_irq_next;
723 /* only support modules with standard clear-on-read for now */
724 for (sih_mod = 0, sih = sih_modules;
725 sih_mod < nr_sih_modules;
727 if (sih->module == module && sih->set_cor) {
728 if (!WARN((irq_base + sih->bits) > NR_IRQS,
729 "irq %d for %s too big\n",
730 irq_base + sih->bits,
739 agent = kzalloc(sizeof *agent, GFP_KERNEL);
745 agent->irq_base = irq_base;
748 INIT_WORK(&agent->mask_work, twl4030_sih_do_mask);
749 INIT_WORK(&agent->edge_work, twl4030_sih_do_edge);
751 for (i = 0; i < sih->bits; i++) {
754 set_irq_chip_and_handler(irq, &twl4030_sih_irq_chip,
756 set_irq_chip_data(irq, agent);
761 twl4030_irq_next += i;
763 /* replace generic PIH handler (handle_simple_irq) */
764 irq = sih_mod + twl4030_irq_base;
765 set_irq_data(irq, agent);
766 set_irq_chained_handler(irq, handle_twl4030_sih);
768 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih->name,
769 irq, irq_base, twl4030_irq_next - 1);
774 /* FIXME need a call to reverse twl4030_sih_setup() ... */
777 /*----------------------------------------------------------------------*/
779 /* FIXME pass in which interrupt line we'll use ... */
780 #define twl_irq_line 0
782 int twl4030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end)
784 static struct irq_chip twl4030_irq_chip;
788 struct task_struct *task;
791 * Mask and clear all TWL4030 interrupts since initially we do
792 * not have any TWL4030 module interrupt handlers present
794 status = twl4030_init_sih_modules(twl_irq_line);
798 wq = create_singlethread_workqueue("twl4030-irqchip");
800 pr_err("twl4030: workqueue FAIL\n");
804 twl4030_irq_base = irq_base;
806 /* install an irq handler for each of the SIH modules;
807 * clone dummy irq_chip since PIH can't *do* anything
809 twl4030_irq_chip = dummy_irq_chip;
810 twl4030_irq_chip.name = "twl4030";
812 twl4030_sih_irq_chip.ack = dummy_irq_chip.ack;
814 for (i = irq_base; i < irq_end; i++) {
815 set_irq_chip_and_handler(i, &twl4030_irq_chip,
819 twl4030_irq_next = i;
820 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", "PIH",
821 irq_num, irq_base, twl4030_irq_next - 1);
823 /* ... and the PWR_INT module ... */
824 status = twl4030_sih_setup(TWL4030_MODULE_INT);
826 pr_err("twl4030: sih_setup PWR INT --> %d\n", status);
830 /* install an irq handler to demultiplex the TWL4030 interrupt */
833 init_completion(&irq_event);
835 status = request_irq(irq_num, handle_twl4030_pih, IRQF_DISABLED,
836 "TWL4030-PIH", &irq_event);
838 pr_err("twl4030: could not claim irq%d: %d\n", irq_num, status);
842 task = kthread_run(twl4030_irq_thread, (void *)(long)irq_num,
845 pr_err("twl4030: could not create irq %d thread!\n", irq_num);
846 status = PTR_ERR(task);
851 free_irq(irq_num, &irq_event);
853 /* clean up twl4030_sih_setup */
855 for (i = irq_base; i < irq_end; i++)
856 set_irq_chip_and_handler(i, NULL, NULL);
857 destroy_workqueue(wq);
862 int twl4030_exit_irq(void)
864 /* FIXME undo twl_init_irq() */
865 if (twl4030_irq_base) {
866 pr_err("twl4030: can't yet clean up IRQs?\n");
872 int twl4030_init_chip_irq(const char *chip)
874 if (!strcmp(chip, "twl5031")) {
875 sih_modules = sih_modules_twl5031;
876 nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031);
878 sih_modules = sih_modules_twl4030;
879 nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030);