drivers/mfd/rt5033_irq.c

   1 /* drivers/mfd/rt5033_irq.c
   2  * RT5033 Multifunction Device Driver
   3  * Charger / Buck / LDOs / FlashLED
   4  *
   5  * Copyright (C) 2013 Richtek Technology Corp.
   6  * Author: Patrick Chang <patrick_chang@richtek.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation; either version 2
  11  * of the License, or (at your option) any later version.
  12  */
  13 #include <linux/mfd/rt5033.h>
  14 #include <linux/mfd/rt5033_irq.h>
  15 #include <linux/gpio.h>
  16 #include <linux/device.h>
  17
  18 #define ALIAS_NAME "rt5033_mfd_irq"
  19
  20 #define RT5033_CHG_IRQ          0x60
  21 #define RT5033_LED_IRQ          0x66
  22 #define RT5033_PMIC_IRQ         0x68
  23 #define RT5033_OFF_EVENT        0x6B
  24
  25 #define RT5033_CHG_IRQ_CTRL     0x63
  26 #define RT5033_CHG_IRQ1_CTRL    RT5033_CHG_IRQ_CTRL
  27 #define RT5033_CHG_IRQ2_CTRL    (RT5033_CHG_IRQ_CTRL + 1)
  28 #define RT5033_CHG_IRQ3_CTRL    (RT5033_CHG_IRQ_CTRL + 2)
  29 #define RT5033_LED_IRQ_CTRL     0x67
  30 #define RT5033_PMIC_IRQ_CTRL    0x69
  31
  32 #define IRQ_NAME(irq) [irq] = irq##_NAME
  33 static const char *rt5033_irq_names[] = {
  34         IRQ_NAME(RT5033_ADPBAD_IRQ),
  35         IRQ_NAME(RT5033_PPBATLV_IRQ),
  36         IRQ_NAME(RT5033_CHTMRFI_IRQ),
  37         IRQ_NAME(RT5033_VINOVPI_IRQ),
  38         IRQ_NAME(RT5033_TSDI_IRQ),
  39         IRQ_NAME(RT5033_CHMIVRI_IRQ),
  40         IRQ_NAME(RT5033_CHTREGI_IRQ),
  41         IRQ_NAME(RT5033_IEOC_IRQ),
  42         IRQ_NAME(RT5033_CHRCHGI_IRQ),
  43         IRQ_NAME(RT5033_CHTERMI_IRQ),
  44         IRQ_NAME(RT5033_CHBATOVI_IRQ),
  45         IRQ_NAME(RT5033_CHRVPI_IRQ),
  46         IRQ_NAME(RT5033_BSTLOWVI_IRQ),
  47         IRQ_NAME(RT5033_BSTOLI_IRQ),
  48         IRQ_NAME(RT5033_BSTVMIDOVP_IRQ),
  49         IRQ_NAME(RT5033_VF_L_IRQ),
  50         IRQ_NAME(RT5033_LEDCS2_SHORT_IRQ),
  51         IRQ_NAME(RT5033_LEDCS1_SHORT_IRQ),
  52         IRQ_NAME(RT5033_BUCK_OCP_IRQ),
  53         IRQ_NAME(RT5033_BUCK_LV_IRQ),
  54         IRQ_NAME(RT5033_SAFE_LDO_LV_IRQ),
  55         IRQ_NAME(RT5033_LDO_LV_IRQ),
  56         IRQ_NAME(RT5033_OT_IRQ),
  57         IRQ_NAME(RT5033_VDDA_UV_IRQ),
  58 };
  59
  60 const char *rt5033_get_irq_name_by_index(int index)
  61 {
  62         return rt5033_irq_names[index];
  63 }
  64 EXPORT_SYMBOL(rt5033_get_irq_name_by_index);
  65
  66 enum RT5033_IRQ_OFFSET {
  67         RT5033_CHG_IRQ_OFFSET = 0,
  68         RT5033_CHG_IRQ1_OFFSET = 0,
  69         RT5033_CHG_IRQ2_OFFSET,
  70         RT5033_CHG_IRQ3_OFFSET,
  71         RT5033_LED_IRQ_OFFSET,
  72         RT5033_PMIC_IRQ_OFFSET,
  73 };
  74
  75 struct rt5033_irq_data {
  76         int mask;
  77         int offset;
  78 };
  79
  80 static const u8 rt5033_mask_reg[] = {
  81         RT5033_CHG_IRQ1_CTRL,
  82         RT5033_CHG_IRQ2_CTRL,
  83         RT5033_CHG_IRQ3_CTRL,
  84         RT5033_LED_IRQ_CTRL,
  85         RT5033_PMIC_IRQ_CTRL,
  86 };
  87
  88 #define DECLARE_IRQ_CTRL(idx, _offset, _mask)           \
  89         [(idx)] = { .offset = (_offset), .mask = (_mask) }
  90
  91 static const struct rt5033_irq_data rt5033_irqs[] = {
  92         DECLARE_IRQ_CTRL(RT5033_ADPBAD_IRQ, 0, 1 << 0),
  93         DECLARE_IRQ_CTRL(RT5033_PPBATLV_IRQ, 0, 1 << 4),
  94         DECLARE_IRQ_CTRL(RT5033_CHTERMI_IRQ, 0, 1 << 5),
  95         DECLARE_IRQ_CTRL(RT5033_VINOVPI_IRQ, 0, 1 << 6),
  96         DECLARE_IRQ_CTRL(RT5033_TSDI_IRQ, 0, 1 << 7),
  97         DECLARE_IRQ_CTRL(RT5033_CHMIVRI_IRQ, 1, 1 << 0),
  98         DECLARE_IRQ_CTRL(RT5033_CHTREGI_IRQ, 1, 1 << 1),
  99         DECLARE_IRQ_CTRL(RT5033_CHTMRFI_IRQ, 1, 1 << 2),
 100         DECLARE_IRQ_CTRL(RT5033_CHRCHGI_IRQ, 1, 1 << 3),
 101         DECLARE_IRQ_CTRL(RT5033_IEOC_IRQ, 1, 1 << 4),
 102         DECLARE_IRQ_CTRL(RT5033_CHBATOVI_IRQ, 1, 1 << 5),
 103         DECLARE_IRQ_CTRL(RT5033_CHRVPI_IRQ, 1, 1 << 7),
 104
 105         DECLARE_IRQ_CTRL(RT5033_BSTLOWVI_IRQ, 2, 1 << 5),
 106         DECLARE_IRQ_CTRL(RT5033_BSTOLI_IRQ, 2, 1 << 6),
 107         DECLARE_IRQ_CTRL(RT5033_BSTVMIDOVP_IRQ, 2, 1 << 7),
 108
 109         DECLARE_IRQ_CTRL(RT5033_VF_L_IRQ, 3, 1 << 3),
 110         DECLARE_IRQ_CTRL(RT5033_LEDCS2_SHORT_IRQ, 3, 1 << 6),
 111         DECLARE_IRQ_CTRL(RT5033_LEDCS1_SHORT_IRQ, 3, 1 << 7),
 112
 113         DECLARE_IRQ_CTRL(RT5033_BUCK_OCP_IRQ, 4, 1 << 2),
 114         DECLARE_IRQ_CTRL(RT5033_BUCK_LV_IRQ, 4, 1 << 3),
 115         DECLARE_IRQ_CTRL(RT5033_SAFE_LDO_LV_IRQ, 4, 1 << 4),
 116         DECLARE_IRQ_CTRL(RT5033_LDO_LV_IRQ, 4, 1 << 5),
 117         DECLARE_IRQ_CTRL(RT5033_OT_IRQ, 4, 1 << 6),
 118         DECLARE_IRQ_CTRL(RT5033_VDDA_UV_IRQ, 4, 1 << 7),
 119 };
 120
 121
 122 static void rt5033_irq_lock(struct irq_data *data)
 123 {
 124         rt5033_mfd_chip_t *chip = irq_get_chip_data(data->irq);
 125         mutex_lock(&chip->irq_lock);
 126 }
 127
 128 static void rt5033_irq_sync_unlock(struct irq_data *data)
 129 {
 130         rt5033_mfd_chip_t *chip = irq_get_chip_data(data->irq);
 131         rt5033_block_write_device(chip->i2c_client,
 132                         RT5033_CHG_IRQ_CTRL,
 133                         RT5033_CHG_IRQ_REGS_NR,
 134                         chip->irq_masks_cache +
 135                         RT5033_CHG_IRQ_OFFSET);
 136
 137         rt5033_block_write_device(chip->i2c_client,
 138                         RT5033_LED_IRQ_CTRL,
 139                         RT5033_LED_IRQ_REGS_NR,
 140                         chip->irq_masks_cache +
 141                         RT5033_LED_IRQ_OFFSET);
 142
 143         rt5033_block_write_device(chip->i2c_client,
 144                         RT5033_PMIC_IRQ_CTRL,
 145                         RT5033_PMIC_IRQ_REGS_NR,
 146                         chip->irq_masks_cache +
 147                         RT5033_PMIC_IRQ_OFFSET);
 148
 149         mutex_unlock(&chip->irq_lock);
 150 }
 151
 152         static const inline struct rt5033_irq_data *
 153 irq_to_rt5033_irq(rt5033_mfd_chip_t *chip, int irq)
 154 {
 155         return &rt5033_irqs[irq - chip->irq_base];
 156 }
 157
 158 static void rt5033_irq_mask(struct irq_data *data)
 159 {
 160         rt5033_mfd_chip_t *chip = irq_get_chip_data(data->irq);
 161         const struct rt5033_irq_data *irq_data = irq_to_rt5033_irq(chip,
 162                         data->irq);
 163
 164         chip->irq_masks_cache[irq_data->offset] |= irq_data->mask;
 165 }
 166
 167
 168 static void rt5033_irq_unmask(struct irq_data *data)
 169 {
 170         rt5033_mfd_chip_t *chip = irq_get_chip_data(data->irq);
 171         const struct rt5033_irq_data *irq_data = irq_to_rt5033_irq(chip,
 172                         data->irq);
 173
 174         chip->irq_masks_cache[irq_data->offset] &= ~irq_data->mask;
 175 }
 176
 177 static struct irq_chip rt5033_irq_chip = {
 178         .name                   = "rt5033",
 179         .irq_bus_lock           = rt5033_irq_lock,
 180         .irq_bus_sync_unlock    = rt5033_irq_sync_unlock,
 181         .irq_mask               = rt5033_irq_mask,
 182         .irq_unmask             = rt5033_irq_unmask,
 183 };
 184
 185 rt5033_irq_status_t *rt5033_get_irq_status(rt5033_mfd_chip_t *mfd_chip,
 186                 rt5033_irq_status_sel_t sel)
 187 {
 188
 189         int index;
 190
 191         switch(sel) {
 192                 case RT5033_PREV_STATUS:
 193                         index = mfd_chip->irq_status_index ^ 0x01;
 194                         break;
 195                 case RT5033_NOW_STATUS:
 196                 default:
 197                         index = mfd_chip->irq_status_index;
 198         }
 199
 200         return &mfd_chip->irq_status[index];
 201 }
 202 EXPORT_SYMBOL(rt5033_get_irq_status);
 203
 204 static int rt5033_read_irq_status(rt5033_mfd_chip_t *chip)
 205 {
 206         int ret;
 207         struct i2c_client *iic = chip->i2c_client;
 208         rt5033_irq_status_t *now_irq_status;
 209
 210         now_irq_status = rt5033_get_irq_status(chip, RT5033_NOW_STATUS);
 211
 212 #ifdef CONFIG_CHARGER_RT5033
 213         ret = rt5033_block_read_device(iic, RT5033_CHG_IRQ,
 214                         sizeof(now_irq_status->chg_irq_status),
 215                         now_irq_status->chg_irq_status);
 216         if (ret < 0) {
 217                 dev_err(chip->dev,
 218                                 "Failed on reading CHG irq status\n");
 219                 return ret;
 220         }
 221
 222         printk("charger irq = 0x%x 0x%x 0x%x\n", (int)now_irq_status->chg_irq_status[0],
 223                         (int)now_irq_status->chg_irq_status[1],
 224                         now_irq_status->chg_irq_status[2]);
 225 #endif
 226 #ifdef CONFIG_FLED_RT5033
 227         ret = rt5033_block_read_device(iic, RT5033_LED_IRQ,
 228                         sizeof(now_irq_status->fled_irq_status),
 229                         now_irq_status->fled_irq_status);
 230         if (ret < 0) {
 231                 dev_err(chip->dev,
 232                                 "Failed on reading FlashLED irq status\n");
 233                 return ret;
 234         }
 235         printk("fled irq = 0x%x\n", (int)now_irq_status->fled_irq_status[0]);
 236 #endif /* CONFIG_FLED_RT5033 */
 237
 238 #ifdef CONFIG_REGULATOR_RT5033
 239         ret = rt5033_block_read_device(iic, RT5033_PMIC_IRQ,
 240                         sizeof(now_irq_status->pmic_irq_status),
 241                         now_irq_status->pmic_irq_status);
 242         if (ret < 0) {
 243                 dev_err(chip->dev,
 244                                 "Failed on reading PMIC irq status\n");
 245                 return ret;
 246         }
 247         printk("regulator irq = 0x%x\n", (int)now_irq_status->pmic_irq_status[0]);
 248 #endif /* CONFIG_REGULATOR_RT5033 */
 249
 250         return 0;
 251 }
 252
 253 static void rt5033_irq_work(rt5033_mfd_chip_t *chip)
 254 {
 255         int ret;
 256         int i;
 257         rt5033_irq_status_t *status;
 258         pr_info("%s : handle IRQ event\n", __func__);
 259         ret = rt5033_read_irq_status(chip);
 260         if (ret < 0) {
 261                 pr_err("%s :Error : can't read irq status (%d)\n",
 262                                 __func__, ret);
 263                 return;
 264         }
 265         status = rt5033_get_irq_status(chip, RT5033_NOW_STATUS);
 266
 267         for (i = 0; i < RT5033_IRQ_REGS_NR; i++)
 268                 status->regs[i] &= ~chip->irq_masks_cache[i];
 269
 270         for (i = 0; i < RT5033_IRQS_NR; i++) {
 271                 if (status->regs[rt5033_irqs[i].offset] & rt5033_irqs[i].mask) {
 272                         pr_info("%s : Trigger IRQ %s, irq : %d \n",
 273                                         __func__, rt5033_get_irq_name_by_index(i),
 274                                         chip->irq_base + i);
 275
 276                         handle_nested_irq(chip->irq_base + i);
 277                 }
 278         }
 279
 280         chip->irq_status_index ^= 0x01; // exchange irq index;
 281 }
 282
 283 static irqreturn_t rt5033_irq_handler(int irq, void *data)
 284 {
 285         rt5033_mfd_chip_t *chip = data;
 286
 287
 288         printk("RT5033 IRQ triggered\n");
 289         wake_lock_timeout(&chip->irq_wake_lock, msecs_to_jiffies(500));
 290         mutex_lock(&chip->suspend_flag_lock);
 291         if (chip->suspend_flag) {
 292                 printk("I2C host controller might not be ready,"
 293                                 " pend this IRQ event...\n");
 294                 chip->pending_irq = true;
 295         } else
 296                 rt5033_irq_work(chip);
 297         mutex_unlock(&chip->suspend_flag_lock);;
 298         return IRQ_HANDLED;
 299 }
 300
 301 static int rt5033_irq_ctrl_regs[] = {
 302         RT5033_CHG_IRQ1_CTRL,
 303         RT5033_CHG_IRQ2_CTRL,
 304         RT5033_CHG_IRQ3_CTRL,
 305         RT5033_LED_IRQ_CTRL,
 306         RT5033_PMIC_IRQ_CTRL,
 307 };
 308
 309 static uint8_t rt5033_irqs_ctrl_mask_all_val[] = {
 310         0xf1,
 311         0xbf,
 312         0xf0,
 313         0xc8,
 314         0xfc,
 315 };
 316
 317 static int rt5033_mask_all_irqs(struct i2c_client *iic)
 318 {
 319         int rc;
 320         int i;
 321
 322         rt5033_mfd_chip_t *chip = i2c_get_clientdata(iic);
 323
 324         for (i = 0; i < ARRAY_SIZE(rt5033_irq_ctrl_regs); i++) {
 325                 rc = rt5033_reg_write(iic, rt5033_irq_ctrl_regs[i],
 326                                 rt5033_irqs_ctrl_mask_all_val[i]);
 327                 chip->irq_masks_cache[i] = rt5033_irqs_ctrl_mask_all_val[i];
 328                 if (rc < 0) {
 329                         pr_info("Error : can't write reg[0x%x] = 0x%x\n",
 330                                         rt5033_irq_ctrl_regs[i],
 331                                         rt5033_irqs_ctrl_mask_all_val[i]);
 332                         return rc;
 333                 }
 334         }
 335
 336         return 0;
 337 }
 338
 339 static int rt5033_irq_init_read(rt5033_mfd_chip_t *chip)
 340 {
 341         int ret;
 342         ret = rt5033_read_irq_status(chip);
 343         chip->irq_status_index ^= 0x01;
 344
 345         return ret;
 346 }
 347
 348 int rt5033_init_irq(rt5033_mfd_chip_t *chip)
 349 {
 350         int i, ret, curr_irq;
 351         ret = rt5033_mask_all_irqs(chip->i2c_client);
 352
 353         if (ret < 0) {
 354                 pr_err("%s : Can't mask all irqs(%d)\n", __func__, ret);
 355                 goto err_mask_all_irqs;
 356         }
 357
 358         rt5033_irq_init_read(chip);
 359         mutex_init(&chip->irq_lock);
 360
 361         /* Register with genirq */
 362         for (i = 0; i < RT5033_IRQS_NR; i++) {
 363                 curr_irq = i + chip->irq_base;
 364                 irq_set_chip_data(curr_irq, chip);
 365                 irq_set_chip_and_handler(curr_irq, &rt5033_irq_chip,
 366                                 handle_simple_irq);
 367                 irq_set_nested_thread(curr_irq, 1);
 368 #ifdef CONFIG_ARM
 369                 set_irq_flags(curr_irq, IRQF_VALID);
 370 #else
 371                 irq_set_noprobe(curr_irq);
 372 #endif
 373         }
 374
 375         ret = gpio_request(chip->pdata->irq_gpio, "rt5033_mfd_irq");
 376         if (ret < 0) {
 377                 pr_err("%s : Request GPIO %d failed\n",
 378                                 __func__, (int)chip->pdata->irq_gpio);
 379                 goto err_gpio_request;
 380         }
 381
 382         ret = gpio_direction_input(chip->pdata->irq_gpio);
 383         if (ret < 0) {
 384                 pr_err("Set GPIO direction to input : failed\n");
 385                 goto err_set_gpio_input;
 386         }
 387
 388         chip->irq = gpio_to_irq(chip->pdata->irq_gpio);
 389         ret = request_threaded_irq(chip->irq, NULL, rt5033_irq_handler,
 390                         IRQF_TRIGGER_FALLING | IRQF_ONESHOT | IRQF_NO_SUSPEND,
 391                         "rt5033", chip);
 392         if (ret < 0) {
 393                 pr_err("%s : Failed : request IRQ (%d)\n", __func__, ret);
 394                 goto err_request_irq;
 395
 396         }
 397
 398         ret = enable_irq_wake(chip->irq);
 399         if (ret < 0) {
 400                 pr_info("%s : enable_irq_wake(%d) failed for (%d)\n",
 401                                 __func__, chip->irq, ret);
 402         }
 403
 404
 405         return ret;
 406 err_request_irq:
 407 err_set_gpio_input:
 408         gpio_free(chip->pdata->irq_gpio);
 409 err_gpio_request:
 410         for (curr_irq = chip->irq_base;
 411                         curr_irq < chip->irq_base + RT5033_IRQS_NR;
 412                         curr_irq++) {
 413 #ifdef CONFIG_ARM
 414                 set_irq_flags(curr_irq, 0);
 415 #endif
 416                 irq_set_chip_and_handler(curr_irq, NULL, NULL);
 417                 irq_set_chip_data(curr_irq, NULL);
 418         }
 419
 420         mutex_destroy(&chip->irq_lock);
 421 err_mask_all_irqs:
 422         return ret;
 423
 424 }
 425
 426 int rt5033_exit_irq(rt5033_mfd_chip_t *chip)
 427 {
 428         int curr_irq;
 429
 430         for (curr_irq = chip->irq_base;
 431                         curr_irq < chip->irq_base + RT5033_IRQS_NR;
 432                         curr_irq++) {
 433 #ifdef CONFIG_ARM
 434                 set_irq_flags(curr_irq, 0);
 435 #endif
 436                 irq_set_chip_and_handler(curr_irq, NULL, NULL);
 437                 irq_set_chip_data(curr_irq, NULL);
 438         }
 439
 440         if (chip->irq)
 441                 free_irq(chip->irq, chip);
 442         mutex_destroy(&chip->irq_lock);
 443         return 0;
 444 }
 445 #ifdef CONFIG_PM
 446 int rt5033_irq_suspend(rt5033_mfd_chip_t *chip)
 447 {
 448         mutex_lock(&chip->suspend_flag_lock);
 449         chip->suspend_flag = true;
 450         mutex_unlock(&chip->suspend_flag_lock);
 451         return 0;
 452 }
 453 int rt5033_irq_resume(rt5033_mfd_chip_t *chip)
 454 {
 455         mutex_lock(&chip->suspend_flag_lock);
 456         if (chip->pending_irq) {
 457                 pr_info("%s : there is pending IRQ event\n",
 458                                 __func__);
 459                 rt5033_irq_work(chip);
 460                 chip->pending_irq = false;
 461         }
 462         chip->suspend_flag = false;
 463         mutex_unlock(&chip->suspend_flag_lock);
 464         return 0;
 465 }
 466 #endif /* CONFIG_PM */