1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-22 Raspberry Pi Ltd.
8 #include <linux/clkdev.h>
9 #include <linux/clk-provider.h>
10 #include <linux/completion.h>
11 #include <linux/etherdevice.h>
12 #include <linux/err.h>
13 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/irqchip/chained_irq.h>
17 #include <linux/irqdomain.h>
18 #include <linux/mfd/core.h>
19 #include <linux/mmc/host.h>
20 #include <linux/module.h>
21 #include <linux/msi.h>
22 #include <linux/of_platform.h>
23 #include <linux/pci.h>
24 #include <linux/platform_device.h>
25 #include <linux/rp1_platform.h>
26 #include <linux/reset.h>
27 #include <linux/slab.h>
29 #include <dt-bindings/mfd/rp1.h>
32 * 1. Occasional shutdown crash - RP1 being closed before its children?
33 * 2. DT mode interrupt handling.
36 #define RP1_DRIVER_NAME "rp1"
38 #define PCI_VENDOR_ID_RPI 0x1de4
39 #define PCI_DEVICE_ID_RP1_C0 0x0001
40 #define PCI_DEVICE_REV_RP1_C0 2
42 #define RP1_ACTUAL_IRQS RP1_INT_END
43 #define RP1_IRQS RP1_ACTUAL_IRQS
45 #define RP1_SYSCLK_RATE 200000000
46 #define RP1_SYSCLK_FPGA_RATE 60000000
48 // Don't want to include the whole sysinfo reg header
49 #define SYSINFO_CHIP_ID_OFFSET 0x00000000
50 #define SYSINFO_PLATFORM_OFFSET 0x00000004
56 // MSIX CFG registers start at 0x8
57 #define MSIX_CFG(x) (0x8 + (4 * (x)))
59 #define MSIX_CFG_IACK_EN BIT(3)
60 #define MSIX_CFG_IACK BIT(2)
61 #define MSIX_CFG_TEST BIT(1)
62 #define MSIX_CFG_ENABLE BIT(0)
64 #define INTSTATL 0x108
65 #define INTSTATH 0x10c
70 resource_size_t bar_start;
71 resource_size_t bar_end;
73 struct irq_domain *domain;
74 struct irq_data *pcie_irqds[64];
75 void __iomem *msix_cfg_regs;
78 static bool rp1_level_triggered_irq[RP1_ACTUAL_IRQS] = { 0 };
80 static struct rp1_dev *g_rp1;
81 static u32 g_chip_id, g_platform;
83 static void dump_bar(struct pci_dev *pdev, unsigned int bar)
86 "bar%d len 0x%llx, start 0x%llx, end 0x%llx, flags, 0x%lx\n",
88 pci_resource_len(pdev, bar),
89 pci_resource_start(pdev, bar),
90 pci_resource_end(pdev, bar),
91 pci_resource_flags(pdev, bar));
94 static void msix_cfg_set(struct rp1_dev *rp1, unsigned int hwirq, u32 value)
96 writel(value, rp1->msix_cfg_regs + REG_SET + MSIX_CFG(hwirq));
99 static void msix_cfg_clr(struct rp1_dev *rp1, unsigned int hwirq, u32 value)
101 writel(value, rp1->msix_cfg_regs + REG_CLR + MSIX_CFG(hwirq));
104 static void rp1_mask_irq(struct irq_data *irqd)
106 struct rp1_dev *rp1 = irqd->domain->host_data;
107 struct irq_data *pcie_irqd = rp1->pcie_irqds[irqd->hwirq];
109 pci_msi_mask_irq(pcie_irqd);
112 static void rp1_unmask_irq(struct irq_data *irqd)
114 struct rp1_dev *rp1 = irqd->domain->host_data;
115 struct irq_data *pcie_irqd = rp1->pcie_irqds[irqd->hwirq];
117 pci_msi_unmask_irq(pcie_irqd);
120 static int rp1_irq_set_type(struct irq_data *irqd, unsigned int type)
122 struct rp1_dev *rp1 = irqd->domain->host_data;
123 unsigned int hwirq = (unsigned int)irqd->hwirq;
127 case IRQ_TYPE_LEVEL_HIGH:
128 dev_dbg(rp1->dev, "MSIX IACK EN for irq %d\n", hwirq);
129 msix_cfg_set(rp1, hwirq, MSIX_CFG_IACK_EN);
130 rp1_level_triggered_irq[hwirq] = true;
132 case IRQ_TYPE_EDGE_RISING:
133 msix_cfg_clr(rp1, hwirq, MSIX_CFG_IACK_EN);
134 rp1_level_triggered_irq[hwirq] = false;
144 static struct irq_chip rp1_irq_chip = {
145 .name = "rp1_irq_chip",
146 .irq_mask = rp1_mask_irq,
147 .irq_unmask = rp1_unmask_irq,
148 .irq_set_type = rp1_irq_set_type,
151 static void rp1_chained_handle_irq(struct irq_desc *desc)
153 struct irq_chip *chip = irq_desc_get_chip(desc);
154 struct rp1_dev *rp1 = desc->irq_data.chip_data;
155 unsigned int hwirq = desc->irq_data.hwirq & 0x3f;
160 chained_irq_enter(chip, desc);
162 new_irq = irq_linear_revmap(rp1->domain, hwirq);
163 generic_handle_irq(new_irq);
164 if (rp1_level_triggered_irq[hwirq])
165 msix_cfg_set(rp1, hwirq, MSIX_CFG_IACK);
167 chained_irq_exit(chip, desc);
170 static int rp1_irq_xlate(struct irq_domain *d, struct device_node *node,
171 const u32 *intspec, unsigned int intsize,
172 unsigned long *out_hwirq, unsigned int *out_type)
174 struct rp1_dev *rp1 = d->host_data;
175 struct irq_data *pcie_irqd;
180 ret = irq_domain_xlate_twocell(d, node, intspec, intsize,
183 pcie_irq = pci_irq_vector(rp1->pdev, hwirq);
184 pcie_irqd = irq_get_irq_data(pcie_irq);
185 rp1->pcie_irqds[hwirq] = pcie_irqd;
191 static int rp1_irq_activate(struct irq_domain *d, struct irq_data *irqd,
194 struct rp1_dev *rp1 = d->host_data;
195 struct irq_data *pcie_irqd;
197 pcie_irqd = rp1->pcie_irqds[irqd->hwirq];
198 msix_cfg_set(rp1, (unsigned int)irqd->hwirq, MSIX_CFG_ENABLE);
199 return irq_domain_activate_irq(pcie_irqd, reserve);
202 static void rp1_irq_deactivate(struct irq_domain *d, struct irq_data *irqd)
204 struct rp1_dev *rp1 = d->host_data;
205 struct irq_data *pcie_irqd;
207 pcie_irqd = rp1->pcie_irqds[irqd->hwirq];
208 msix_cfg_clr(rp1, (unsigned int)irqd->hwirq, MSIX_CFG_ENABLE);
209 return irq_domain_deactivate_irq(pcie_irqd);
212 static const struct irq_domain_ops rp1_domain_ops = {
213 .xlate = rp1_irq_xlate,
214 .activate = rp1_irq_activate,
215 .deactivate = rp1_irq_deactivate,
218 static inline dma_addr_t rp1_io_to_phys(struct rp1_dev *rp1, unsigned int offset)
220 return rp1->bar_start + offset;
223 static u32 rp1_reg_read(struct rp1_dev *rp1, unsigned int base_addr, u32 offset)
225 dma_addr_t phys = rp1_io_to_phys(rp1, base_addr);
226 void __iomem *regblock = ioremap(phys, 0x1000);
227 u32 value = readl(regblock + offset);
233 void rp1_get_platform(u32 *chip_id, u32 *platform)
236 *chip_id = g_chip_id;
238 *platform = g_platform;
240 EXPORT_SYMBOL_GPL(rp1_get_platform);
242 static int rp1_probe(struct pci_dev *pdev, const struct pci_device_id *id)
244 struct reset_control *reset;
245 struct platform_device *pcie_pdev;
246 struct device_node *rp1_node;
251 reset = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
253 return PTR_ERR(reset);
254 reset_control_reset(reset);
259 if (pci_resource_len(pdev, 1) <= 0x10000) {
261 "Not initialised - is the firmware running?\n");
265 /* enable pci device */
266 err = pcim_enable_device(pdev);
268 dev_err(&pdev->dev, "Enabling PCI device has failed: %d",
273 pci_set_master(pdev);
275 err = pci_alloc_irq_vectors(pdev, RP1_IRQS, RP1_IRQS,
277 if (err != RP1_IRQS) {
278 dev_err(&pdev->dev, "pci_alloc_irq_vectors failed - %d\n", err);
282 rp1 = devm_kzalloc(&pdev->dev, sizeof(*rp1), GFP_KERNEL);
287 rp1->dev = &pdev->dev;
289 pci_set_drvdata(pdev, rp1);
291 rp1->bar_start = pci_resource_start(pdev, 1);
292 rp1->bar_end = pci_resource_end(pdev, 1);
295 g_chip_id = rp1_reg_read(rp1, RP1_SYSINFO_BASE, SYSINFO_CHIP_ID_OFFSET);
296 g_platform = rp1_reg_read(rp1, RP1_SYSINFO_BASE, SYSINFO_PLATFORM_OFFSET);
297 dev_info(&pdev->dev, "chip_id 0x%x%s\n", g_chip_id,
298 (g_platform & RP1_PLATFORM_FPGA) ? " FPGA" : "");
299 if (g_chip_id != RP1_C0_CHIP_ID) {
300 dev_err(&pdev->dev, "wrong chip id (%x)\n", g_chip_id);
304 rp1_node = of_find_node_by_name(NULL, "rp1");
306 dev_err(&pdev->dev, "failed to find RP1 DT node\n");
310 pcie_pdev = of_find_device_by_node(rp1_node->parent);
311 rp1->domain = irq_domain_add_linear(rp1_node, RP1_IRQS,
312 &rp1_domain_ops, rp1);
316 /* TODO can this go in the rp1 device tree entry? */
317 rp1->msix_cfg_regs = ioremap(rp1_io_to_phys(rp1, RP1_PCIE_APBS_BASE), 0x1000);
319 for (i = 0; i < RP1_IRQS; i++) {
320 int irq = irq_create_mapping(rp1->domain, i);
323 dev_err(&pdev->dev, "failed to create irq mapping\n");
327 irq_set_chip_data(irq, rp1);
328 irq_set_chip_and_handler(irq, &rp1_irq_chip, handle_level_irq);
330 irq_set_chained_handler(pci_irq_vector(pdev, i),
331 rp1_chained_handle_irq);
335 of_platform_populate(rp1_node, NULL, NULL, &pcie_pdev->dev);
337 of_node_put(rp1_node);
342 static void rp1_remove(struct pci_dev *pdev)
344 struct rp1_dev *rp1 = pci_get_drvdata(pdev);
346 mfd_remove_devices(&pdev->dev);
348 clk_unregister(rp1->sys_clk);
351 static const struct pci_device_id dev_id_table[] = {
352 { PCI_DEVICE(PCI_VENDOR_ID_RPI, PCI_DEVICE_ID_RP1_C0), },
356 static struct pci_driver rp1_driver = {
357 .name = RP1_DRIVER_NAME,
358 .id_table = dev_id_table,
360 .remove = rp1_remove,
363 module_pci_driver(rp1_driver);
365 MODULE_AUTHOR("Phil Elwell <phil@raspberrypi.com>");
366 MODULE_DESCRIPTION("RP1 wrapper");
367 MODULE_LICENSE("GPL");