2 * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Keshava Munegowda <keshava_mgowda@ti.com>
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 of
9 * the License as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/types.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/clk.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/spinlock.h>
27 #include <linux/gpio.h>
28 #include <linux/platform_device.h>
29 #include <linux/platform_data/usb-omap.h>
30 #include <linux/pm_runtime.h>
34 #define USBHS_DRIVER_NAME "usbhs_omap"
35 #define OMAP_EHCI_DEVICE "ehci-omap"
36 #define OMAP_OHCI_DEVICE "ohci-omap3"
38 /* OMAP USBHOST Register addresses */
40 /* UHH Register Set */
41 #define OMAP_UHH_REVISION (0x00)
42 #define OMAP_UHH_SYSCONFIG (0x10)
43 #define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
44 #define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
45 #define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
46 #define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
47 #define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
48 #define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
50 #define OMAP_UHH_SYSSTATUS (0x14)
51 #define OMAP_UHH_HOSTCONFIG (0x40)
52 #define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
53 #define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
54 #define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
55 #define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
56 #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
57 #define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
58 #define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
59 #define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
60 #define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
61 #define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
62 #define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
63 #define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31)
65 /* OMAP4-specific defines */
66 #define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2)
67 #define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2)
68 #define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4)
69 #define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4)
70 #define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0)
72 #define OMAP4_P1_MODE_CLEAR (3 << 16)
73 #define OMAP4_P1_MODE_TLL (1 << 16)
74 #define OMAP4_P1_MODE_HSIC (3 << 16)
75 #define OMAP4_P2_MODE_CLEAR (3 << 18)
76 #define OMAP4_P2_MODE_TLL (1 << 18)
77 #define OMAP4_P2_MODE_HSIC (3 << 18)
79 #define OMAP_UHH_DEBUG_CSR (0x44)
81 /* Values of UHH_REVISION - Note: these are not given in the TRM */
82 #define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */
83 #define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */
85 #define is_omap_usbhs_rev1(x) (x->usbhs_rev == OMAP_USBHS_REV1)
86 #define is_omap_usbhs_rev2(x) (x->usbhs_rev == OMAP_USBHS_REV2)
88 #define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY)
89 #define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
90 #define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC)
93 struct usbhs_hcd_omap {
95 struct clk **utmi_clk;
97 struct clk *xclk60mhsp1_ck;
98 struct clk *xclk60mhsp2_ck;
99 struct clk *utmi_p1_gfclk;
100 struct clk *utmi_p2_gfclk;
101 struct clk *init_60m_fclk;
102 struct clk *ehci_logic_fck;
104 void __iomem *uhh_base;
106 struct usbhs_omap_platform_data *pdata;
111 /*-------------------------------------------------------------------------*/
113 const char usbhs_driver_name[] = USBHS_DRIVER_NAME;
114 static u64 usbhs_dmamask = DMA_BIT_MASK(32);
116 /*-------------------------------------------------------------------------*/
118 static inline void usbhs_write(void __iomem *base, u32 reg, u32 val)
120 __raw_writel(val, base + reg);
123 static inline u32 usbhs_read(void __iomem *base, u32 reg)
125 return __raw_readl(base + reg);
128 static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val)
130 __raw_writeb(val, base + reg);
133 static inline u8 usbhs_readb(void __iomem *base, u8 reg)
135 return __raw_readb(base + reg);
138 /*-------------------------------------------------------------------------*/
140 static struct platform_device *omap_usbhs_alloc_child(const char *name,
141 struct resource *res, int num_resources, void *pdata,
142 size_t pdata_size, struct device *dev)
144 struct platform_device *child;
147 child = platform_device_alloc(name, 0);
150 dev_err(dev, "platform_device_alloc %s failed\n", name);
154 ret = platform_device_add_resources(child, res, num_resources);
156 dev_err(dev, "platform_device_add_resources failed\n");
160 ret = platform_device_add_data(child, pdata, pdata_size);
162 dev_err(dev, "platform_device_add_data failed\n");
166 child->dev.dma_mask = &usbhs_dmamask;
167 dma_set_coherent_mask(&child->dev, DMA_BIT_MASK(32));
168 child->dev.parent = dev;
170 ret = platform_device_add(child);
172 dev_err(dev, "platform_device_add failed\n");
179 platform_device_put(child);
185 static int omap_usbhs_alloc_children(struct platform_device *pdev)
187 struct device *dev = &pdev->dev;
188 struct usbhs_omap_platform_data *pdata = dev->platform_data;
189 struct platform_device *ehci;
190 struct platform_device *ohci;
191 struct resource *res;
192 struct resource resources[2];
195 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci");
197 dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n");
203 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq");
205 dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n");
211 ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, pdata,
212 sizeof(*pdata), dev);
215 dev_err(dev, "omap_usbhs_alloc_child failed\n");
220 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci");
222 dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n");
228 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq");
230 dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n");
236 ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, pdata,
237 sizeof(*pdata), dev);
239 dev_err(dev, "omap_usbhs_alloc_child failed\n");
247 platform_device_unregister(ehci);
253 static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
256 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
257 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
258 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
259 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
260 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
261 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
262 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
263 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
264 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
265 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
273 static int usbhs_runtime_resume(struct device *dev)
275 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
276 struct usbhs_omap_platform_data *pdata = omap->pdata;
280 dev_dbg(dev, "usbhs_runtime_resume\n");
283 spin_lock_irqsave(&omap->lock, flags);
285 if (!IS_ERR(omap->ehci_logic_fck))
286 clk_enable(omap->ehci_logic_fck);
288 for (i = 0; i < omap->nports; i++) {
289 if (!is_ehci_tll_mode(pdata->port_mode[i]) ||
290 IS_ERR(omap->utmi_clk[i]))
293 r = clk_enable(omap->utmi_clk[i]);
295 dev_err(dev, "Can't enable port %d clk : %d\n", i, r);
298 spin_unlock_irqrestore(&omap->lock, flags);
303 static int usbhs_runtime_suspend(struct device *dev)
305 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
306 struct usbhs_omap_platform_data *pdata = omap->pdata;
310 dev_dbg(dev, "usbhs_runtime_suspend\n");
312 spin_lock_irqsave(&omap->lock, flags);
314 for (i = 0; i < omap->nports; i++) {
315 if (is_ehci_tll_mode(pdata->port_mode[i]) &&
316 !IS_ERR(omap->utmi_clk[i]))
317 clk_disable(omap->utmi_clk[i]);
320 if (!IS_ERR(omap->ehci_logic_fck))
321 clk_disable(omap->ehci_logic_fck);
323 spin_unlock_irqrestore(&omap->lock, flags);
329 static void omap_usbhs_init(struct device *dev)
331 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
332 struct usbhs_omap_platform_data *pdata = omap->pdata;
336 dev_dbg(dev, "starting TI HSUSB Controller\n");
338 if (pdata->phy_reset) {
339 if (gpio_is_valid(pdata->reset_gpio_port[0]))
340 gpio_request_one(pdata->reset_gpio_port[0],
341 GPIOF_OUT_INIT_LOW, "USB1 PHY reset");
343 if (gpio_is_valid(pdata->reset_gpio_port[1]))
344 gpio_request_one(pdata->reset_gpio_port[1],
345 GPIOF_OUT_INIT_LOW, "USB2 PHY reset");
347 /* Hold the PHY in RESET for enough time till DIR is high */
351 pm_runtime_get_sync(dev);
352 spin_lock_irqsave(&omap->lock, flags);
354 reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
355 /* setup ULPI bypass and burst configurations */
356 reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
357 | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
358 | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
359 reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK;
360 reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
362 if (is_omap_usbhs_rev1(omap)) {
363 if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED)
364 reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
365 if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED)
366 reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
367 if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED)
368 reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
370 /* Bypass the TLL module for PHY mode operation */
371 if (pdata->single_ulpi_bypass) {
372 dev_dbg(dev, "OMAP3 ES version <= ES2.1\n");
373 if (is_ehci_phy_mode(pdata->port_mode[0]) ||
374 is_ehci_phy_mode(pdata->port_mode[1]) ||
375 is_ehci_phy_mode(pdata->port_mode[2]))
376 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
378 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
380 dev_dbg(dev, "OMAP3 ES version > ES2.1\n");
381 if (is_ehci_phy_mode(pdata->port_mode[0]))
382 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
384 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
385 if (is_ehci_phy_mode(pdata->port_mode[1]))
386 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
388 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
389 if (is_ehci_phy_mode(pdata->port_mode[2]))
390 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
392 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
394 } else if (is_omap_usbhs_rev2(omap)) {
395 /* Clear port mode fields for PHY mode*/
396 reg &= ~OMAP4_P1_MODE_CLEAR;
397 reg &= ~OMAP4_P2_MODE_CLEAR;
399 if (is_ehci_tll_mode(pdata->port_mode[0]) ||
400 (is_ohci_port(pdata->port_mode[0])))
401 reg |= OMAP4_P1_MODE_TLL;
402 else if (is_ehci_hsic_mode(pdata->port_mode[0]))
403 reg |= OMAP4_P1_MODE_HSIC;
405 if (is_ehci_tll_mode(pdata->port_mode[1]) ||
406 (is_ohci_port(pdata->port_mode[1])))
407 reg |= OMAP4_P2_MODE_TLL;
408 else if (is_ehci_hsic_mode(pdata->port_mode[1]))
409 reg |= OMAP4_P2_MODE_HSIC;
412 usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
413 dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
415 spin_unlock_irqrestore(&omap->lock, flags);
417 pm_runtime_put_sync(dev);
418 if (pdata->phy_reset) {
419 /* Hold the PHY in RESET for enough time till
420 * PHY is settled and ready
424 if (gpio_is_valid(pdata->reset_gpio_port[0]))
425 gpio_set_value_cansleep
426 (pdata->reset_gpio_port[0], 1);
428 if (gpio_is_valid(pdata->reset_gpio_port[1]))
429 gpio_set_value_cansleep
430 (pdata->reset_gpio_port[1], 1);
434 static void omap_usbhs_deinit(struct device *dev)
436 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
437 struct usbhs_omap_platform_data *pdata = omap->pdata;
439 if (pdata->phy_reset) {
440 if (gpio_is_valid(pdata->reset_gpio_port[0]))
441 gpio_free(pdata->reset_gpio_port[0]);
443 if (gpio_is_valid(pdata->reset_gpio_port[1]))
444 gpio_free(pdata->reset_gpio_port[1]);
450 * usbhs_omap_probe - initialize TI-based HCDs
452 * Allocates basic resources for this USB host controller.
454 static int usbhs_omap_probe(struct platform_device *pdev)
456 struct device *dev = &pdev->dev;
457 struct usbhs_omap_platform_data *pdata = dev->platform_data;
458 struct usbhs_hcd_omap *omap;
459 struct resource *res;
465 dev_err(dev, "Missing platform data\n");
469 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
471 dev_err(dev, "Memory allocation failed\n");
475 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh");
476 omap->uhh_base = devm_request_and_ioremap(dev, res);
477 if (!omap->uhh_base) {
478 dev_err(dev, "Resource request/ioremap failed\n");
479 return -EADDRNOTAVAIL;
482 spin_lock_init(&omap->lock);
486 pm_runtime_enable(dev);
488 platform_set_drvdata(pdev, omap);
489 pm_runtime_get_sync(dev);
491 omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
493 /* we need to call runtime suspend before we update omap->nports
494 * to prevent unbalanced clk_disable()
496 pm_runtime_put_sync(dev);
499 * If platform data contains nports then use that
500 * else make out number of ports from USBHS revision
503 omap->nports = pdata->nports;
505 switch (omap->usbhs_rev) {
506 case OMAP_USBHS_REV1:
509 case OMAP_USBHS_REV2:
513 omap->nports = OMAP3_HS_USB_PORTS;
515 "USB HOST Rev:0x%d not recognized, assuming %d ports\n",
516 omap->usbhs_rev, omap->nports);
521 i = sizeof(struct clk *) * omap->nports;
522 omap->utmi_clk = devm_kzalloc(dev, i, GFP_KERNEL);
523 if (!omap->utmi_clk) {
524 dev_err(dev, "Memory allocation failed\n");
529 need_logic_fck = false;
530 for (i = 0; i < omap->nports; i++) {
531 if (is_ehci_phy_mode(i) || is_ehci_tll_mode(i) ||
532 is_ehci_hsic_mode(i))
533 need_logic_fck |= true;
536 omap->ehci_logic_fck = ERR_PTR(-EINVAL);
537 if (need_logic_fck) {
538 omap->ehci_logic_fck = clk_get(dev, "ehci_logic_fck");
539 if (IS_ERR(omap->ehci_logic_fck)) {
540 ret = PTR_ERR(omap->ehci_logic_fck);
541 dev_dbg(dev, "ehci_logic_fck failed:%d\n", ret);
545 omap->utmi_p1_gfclk = clk_get(dev, "utmi_p1_gfclk");
546 if (IS_ERR(omap->utmi_p1_gfclk)) {
547 ret = PTR_ERR(omap->utmi_p1_gfclk);
548 dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret);
552 omap->utmi_p2_gfclk = clk_get(dev, "utmi_p2_gfclk");
553 if (IS_ERR(omap->utmi_p2_gfclk)) {
554 ret = PTR_ERR(omap->utmi_p2_gfclk);
555 dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
559 omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
560 if (IS_ERR(omap->xclk60mhsp1_ck)) {
561 ret = PTR_ERR(omap->xclk60mhsp1_ck);
562 dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
563 goto err_xclk60mhsp1;
566 omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
567 if (IS_ERR(omap->xclk60mhsp2_ck)) {
568 ret = PTR_ERR(omap->xclk60mhsp2_ck);
569 dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
570 goto err_xclk60mhsp2;
573 omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
574 if (IS_ERR(omap->init_60m_fclk)) {
575 ret = PTR_ERR(omap->init_60m_fclk);
576 dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
580 for (i = 0; i < omap->nports; i++) {
581 char clkname[] = "usb_host_hs_utmi_px_clk";
583 /* clock names are indexed from 1*/
584 snprintf(clkname, sizeof(clkname),
585 "usb_host_hs_utmi_p%d_clk", i + 1);
587 /* If a clock is not found we won't bail out as not all
588 * platforms have all clocks and we can function without
591 omap->utmi_clk[i] = clk_get(dev, clkname);
592 if (IS_ERR(omap->utmi_clk[i]))
593 dev_dbg(dev, "Failed to get clock : %s : %ld\n",
594 clkname, PTR_ERR(omap->utmi_clk[i]));
597 if (is_ehci_phy_mode(pdata->port_mode[0])) {
598 /* for OMAP3 , the clk set paretn fails */
599 ret = clk_set_parent(omap->utmi_p1_gfclk,
600 omap->xclk60mhsp1_ck);
602 dev_err(dev, "xclk60mhsp1_ck set parent"
603 "failed error:%d\n", ret);
604 } else if (is_ehci_tll_mode(pdata->port_mode[0])) {
605 ret = clk_set_parent(omap->utmi_p1_gfclk,
606 omap->init_60m_fclk);
608 dev_err(dev, "init_60m_fclk set parent"
609 "failed error:%d\n", ret);
612 if (is_ehci_phy_mode(pdata->port_mode[1])) {
613 ret = clk_set_parent(omap->utmi_p2_gfclk,
614 omap->xclk60mhsp2_ck);
616 dev_err(dev, "xclk60mhsp2_ck set parent"
617 "failed error:%d\n", ret);
618 } else if (is_ehci_tll_mode(pdata->port_mode[1])) {
619 ret = clk_set_parent(omap->utmi_p2_gfclk,
620 omap->init_60m_fclk);
622 dev_err(dev, "init_60m_fclk set parent"
623 "failed error:%d\n", ret);
626 omap_usbhs_init(dev);
627 ret = omap_usbhs_alloc_children(pdev);
629 dev_err(dev, "omap_usbhs_alloc_children failed\n");
636 omap_usbhs_deinit(&pdev->dev);
638 for (i = 0; i < omap->nports; i++)
639 if (!IS_ERR(omap->utmi_clk[i]))
640 clk_put(omap->utmi_clk[i]);
642 clk_put(omap->init_60m_fclk);
645 clk_put(omap->xclk60mhsp2_ck);
648 clk_put(omap->xclk60mhsp1_ck);
651 clk_put(omap->utmi_p2_gfclk);
654 clk_put(omap->utmi_p1_gfclk);
657 if (!IS_ERR(omap->ehci_logic_fck))
658 clk_put(omap->ehci_logic_fck);
661 pm_runtime_disable(dev);
667 * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
668 * @pdev: USB Host Controller being removed
670 * Reverses the effect of usbhs_omap_probe().
672 static int usbhs_omap_remove(struct platform_device *pdev)
674 struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
677 omap_usbhs_deinit(&pdev->dev);
679 for (i = 0; i < omap->nports; i++)
680 if (!IS_ERR(omap->utmi_clk[i]))
681 clk_put(omap->utmi_clk[i]);
683 clk_put(omap->init_60m_fclk);
684 clk_put(omap->utmi_p1_gfclk);
685 clk_put(omap->utmi_p2_gfclk);
686 clk_put(omap->xclk60mhsp2_ck);
687 clk_put(omap->xclk60mhsp1_ck);
689 if (!IS_ERR(omap->ehci_logic_fck))
690 clk_put(omap->ehci_logic_fck);
692 pm_runtime_disable(&pdev->dev);
697 static const struct dev_pm_ops usbhsomap_dev_pm_ops = {
698 .runtime_suspend = usbhs_runtime_suspend,
699 .runtime_resume = usbhs_runtime_resume,
702 static struct platform_driver usbhs_omap_driver = {
704 .name = (char *)usbhs_driver_name,
705 .owner = THIS_MODULE,
706 .pm = &usbhsomap_dev_pm_ops,
708 .remove = __exit_p(usbhs_omap_remove),
711 MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
712 MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
713 MODULE_LICENSE("GPL v2");
714 MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI");
716 static int __init omap_usbhs_drvinit(void)
718 return platform_driver_probe(&usbhs_omap_driver, usbhs_omap_probe);
722 * init before ehci and ohci drivers;
723 * The usbhs core driver should be initialized much before
724 * the omap ehci and ohci probe functions are called.
725 * This usbhs core driver should be initialized after
728 fs_initcall_sync(omap_usbhs_drvinit);
730 static void __exit omap_usbhs_drvexit(void)
732 platform_driver_unregister(&usbhs_omap_driver);
734 module_exit(omap_usbhs_drvexit);