2 * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Keshava Munegowda <keshava_mgowda@ti.com>
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 of
9 * the License as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/types.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/clk.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/gpio.h>
27 #include <linux/platform_device.h>
28 #include <linux/platform_data/usb-omap.h>
29 #include <linux/pm_runtime.h>
33 #define USBHS_DRIVER_NAME "usbhs_omap"
34 #define OMAP_EHCI_DEVICE "ehci-omap"
35 #define OMAP_OHCI_DEVICE "ohci-omap3"
37 /* OMAP USBHOST Register addresses */
39 /* UHH Register Set */
40 #define OMAP_UHH_REVISION (0x00)
41 #define OMAP_UHH_SYSCONFIG (0x10)
42 #define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
43 #define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
44 #define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
45 #define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
46 #define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
47 #define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
49 #define OMAP_UHH_SYSSTATUS (0x14)
50 #define OMAP_UHH_HOSTCONFIG (0x40)
51 #define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
52 #define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
53 #define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
54 #define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
55 #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
56 #define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
57 #define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
58 #define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
59 #define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
60 #define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
61 #define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
62 #define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31)
64 /* OMAP4-specific defines */
65 #define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2)
66 #define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2)
67 #define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4)
68 #define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4)
69 #define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0)
71 #define OMAP4_P1_MODE_CLEAR (3 << 16)
72 #define OMAP4_P1_MODE_TLL (1 << 16)
73 #define OMAP4_P1_MODE_HSIC (3 << 16)
74 #define OMAP4_P2_MODE_CLEAR (3 << 18)
75 #define OMAP4_P2_MODE_TLL (1 << 18)
76 #define OMAP4_P2_MODE_HSIC (3 << 18)
78 #define OMAP_UHH_DEBUG_CSR (0x44)
80 /* Values of UHH_REVISION - Note: these are not given in the TRM */
81 #define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */
82 #define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */
84 #define is_omap_usbhs_rev1(x) (x->usbhs_rev == OMAP_USBHS_REV1)
85 #define is_omap_usbhs_rev2(x) (x->usbhs_rev == OMAP_USBHS_REV2)
87 #define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY)
88 #define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
89 #define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC)
92 struct usbhs_hcd_omap {
94 struct clk **utmi_clk;
95 struct clk **hsic60m_clk;
96 struct clk **hsic480m_clk;
98 struct clk *xclk60mhsp1_ck;
99 struct clk *xclk60mhsp2_ck;
100 struct clk *utmi_p1_gfclk;
101 struct clk *utmi_p2_gfclk;
102 struct clk *init_60m_fclk;
103 struct clk *ehci_logic_fck;
105 void __iomem *uhh_base;
107 struct usbhs_omap_platform_data *pdata;
111 /*-------------------------------------------------------------------------*/
113 const char usbhs_driver_name[] = USBHS_DRIVER_NAME;
114 static u64 usbhs_dmamask = DMA_BIT_MASK(32);
116 /*-------------------------------------------------------------------------*/
118 static inline void usbhs_write(void __iomem *base, u32 reg, u32 val)
120 __raw_writel(val, base + reg);
123 static inline u32 usbhs_read(void __iomem *base, u32 reg)
125 return __raw_readl(base + reg);
128 static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val)
130 __raw_writeb(val, base + reg);
133 static inline u8 usbhs_readb(void __iomem *base, u8 reg)
135 return __raw_readb(base + reg);
138 /*-------------------------------------------------------------------------*/
140 static struct platform_device *omap_usbhs_alloc_child(const char *name,
141 struct resource *res, int num_resources, void *pdata,
142 size_t pdata_size, struct device *dev)
144 struct platform_device *child;
147 child = platform_device_alloc(name, 0);
150 dev_err(dev, "platform_device_alloc %s failed\n", name);
154 ret = platform_device_add_resources(child, res, num_resources);
156 dev_err(dev, "platform_device_add_resources failed\n");
160 ret = platform_device_add_data(child, pdata, pdata_size);
162 dev_err(dev, "platform_device_add_data failed\n");
166 child->dev.dma_mask = &usbhs_dmamask;
167 dma_set_coherent_mask(&child->dev, DMA_BIT_MASK(32));
168 child->dev.parent = dev;
170 ret = platform_device_add(child);
172 dev_err(dev, "platform_device_add failed\n");
179 platform_device_put(child);
185 static int omap_usbhs_alloc_children(struct platform_device *pdev)
187 struct device *dev = &pdev->dev;
188 struct usbhs_omap_platform_data *pdata = dev->platform_data;
189 struct platform_device *ehci;
190 struct platform_device *ohci;
191 struct resource *res;
192 struct resource resources[2];
195 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci");
197 dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n");
203 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq");
205 dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n");
211 ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, pdata,
212 sizeof(*pdata), dev);
215 dev_err(dev, "omap_usbhs_alloc_child failed\n");
220 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci");
222 dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n");
228 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq");
230 dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n");
236 ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, pdata,
237 sizeof(*pdata), dev);
239 dev_err(dev, "omap_usbhs_alloc_child failed\n");
247 platform_device_unregister(ehci);
253 static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
256 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
257 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
258 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
259 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
260 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
261 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
262 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
263 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
264 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
265 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
273 static int usbhs_runtime_resume(struct device *dev)
275 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
276 struct usbhs_omap_platform_data *pdata = omap->pdata;
279 dev_dbg(dev, "usbhs_runtime_resume\n");
283 if (!IS_ERR(omap->ehci_logic_fck))
284 clk_enable(omap->ehci_logic_fck);
286 for (i = 0; i < omap->nports; i++) {
287 switch (pdata->port_mode[i]) {
288 case OMAP_EHCI_PORT_MODE_HSIC:
289 if (!IS_ERR(omap->hsic60m_clk[i])) {
290 r = clk_enable(omap->hsic60m_clk[i]);
293 "Can't enable port %d hsic60m clk:%d\n",
298 if (!IS_ERR(omap->hsic480m_clk[i])) {
299 r = clk_enable(omap->hsic480m_clk[i]);
302 "Can't enable port %d hsic480m clk:%d\n",
306 /* Fall through as HSIC mode needs utmi_clk */
308 case OMAP_EHCI_PORT_MODE_TLL:
309 if (!IS_ERR(omap->utmi_clk[i])) {
310 r = clk_enable(omap->utmi_clk[i]);
313 "Can't enable port %d clk : %d\n",
326 static int usbhs_runtime_suspend(struct device *dev)
328 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
329 struct usbhs_omap_platform_data *pdata = omap->pdata;
332 dev_dbg(dev, "usbhs_runtime_suspend\n");
334 for (i = 0; i < omap->nports; i++) {
335 switch (pdata->port_mode[i]) {
336 case OMAP_EHCI_PORT_MODE_HSIC:
337 if (!IS_ERR(omap->hsic60m_clk[i]))
338 clk_disable(omap->hsic60m_clk[i]);
340 if (!IS_ERR(omap->hsic480m_clk[i]))
341 clk_disable(omap->hsic480m_clk[i]);
342 /* Fall through as utmi_clks were used in HSIC mode */
344 case OMAP_EHCI_PORT_MODE_TLL:
345 if (!IS_ERR(omap->utmi_clk[i]))
346 clk_disable(omap->utmi_clk[i]);
353 if (!IS_ERR(omap->ehci_logic_fck))
354 clk_disable(omap->ehci_logic_fck);
361 static unsigned omap_usbhs_rev1_hostconfig(struct usbhs_hcd_omap *omap,
364 struct usbhs_omap_platform_data *pdata = omap->pdata;
367 for (i = 0; i < omap->nports; i++) {
368 switch (pdata->port_mode[i]) {
369 case OMAP_USBHS_PORT_MODE_UNUSED:
370 reg &= ~(OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS << i);
372 case OMAP_EHCI_PORT_MODE_PHY:
373 if (pdata->single_ulpi_bypass)
377 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
379 reg &= ~(OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS
383 if (pdata->single_ulpi_bypass)
387 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
389 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS
395 if (pdata->single_ulpi_bypass) {
396 /* bypass ULPI only if none of the ports use PHY mode */
397 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
399 for (i = 0; i < omap->nports; i++) {
400 if (is_ehci_phy_mode(pdata->port_mode[i])) {
401 reg &= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
410 static unsigned omap_usbhs_rev2_hostconfig(struct usbhs_hcd_omap *omap,
413 struct usbhs_omap_platform_data *pdata = omap->pdata;
416 for (i = 0; i < omap->nports; i++) {
417 /* Clear port mode fields for PHY mode */
418 reg &= ~(OMAP4_P1_MODE_CLEAR << 2 * i);
420 if (is_ehci_tll_mode(pdata->port_mode[i]) ||
421 (is_ohci_port(pdata->port_mode[i])))
422 reg |= OMAP4_P1_MODE_TLL << 2 * i;
423 else if (is_ehci_hsic_mode(pdata->port_mode[i]))
424 reg |= OMAP4_P1_MODE_HSIC << 2 * i;
430 static void omap_usbhs_init(struct device *dev)
432 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
433 struct usbhs_omap_platform_data *pdata = omap->pdata;
436 dev_dbg(dev, "starting TI HSUSB Controller\n");
438 if (pdata->phy_reset) {
439 if (gpio_is_valid(pdata->reset_gpio_port[0]))
440 gpio_request_one(pdata->reset_gpio_port[0],
441 GPIOF_OUT_INIT_LOW, "USB1 PHY reset");
443 if (gpio_is_valid(pdata->reset_gpio_port[1]))
444 gpio_request_one(pdata->reset_gpio_port[1],
445 GPIOF_OUT_INIT_LOW, "USB2 PHY reset");
447 /* Hold the PHY in RESET for enough time till DIR is high */
451 pm_runtime_get_sync(dev);
453 reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
454 /* setup ULPI bypass and burst configurations */
455 reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
456 | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
457 | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
458 reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK;
459 reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
461 switch (omap->usbhs_rev) {
462 case OMAP_USBHS_REV1:
463 omap_usbhs_rev1_hostconfig(omap, reg);
466 case OMAP_USBHS_REV2:
467 omap_usbhs_rev2_hostconfig(omap, reg);
470 default: /* newer revisions */
471 omap_usbhs_rev2_hostconfig(omap, reg);
475 usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
476 dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
478 pm_runtime_put_sync(dev);
479 if (pdata->phy_reset) {
480 /* Hold the PHY in RESET for enough time till
481 * PHY is settled and ready
485 if (gpio_is_valid(pdata->reset_gpio_port[0]))
486 gpio_set_value_cansleep
487 (pdata->reset_gpio_port[0], 1);
489 if (gpio_is_valid(pdata->reset_gpio_port[1]))
490 gpio_set_value_cansleep
491 (pdata->reset_gpio_port[1], 1);
495 static void omap_usbhs_deinit(struct device *dev)
497 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
498 struct usbhs_omap_platform_data *pdata = omap->pdata;
500 if (pdata->phy_reset) {
501 if (gpio_is_valid(pdata->reset_gpio_port[0]))
502 gpio_free(pdata->reset_gpio_port[0]);
504 if (gpio_is_valid(pdata->reset_gpio_port[1]))
505 gpio_free(pdata->reset_gpio_port[1]);
511 * usbhs_omap_probe - initialize TI-based HCDs
513 * Allocates basic resources for this USB host controller.
515 static int usbhs_omap_probe(struct platform_device *pdev)
517 struct device *dev = &pdev->dev;
518 struct usbhs_omap_platform_data *pdata = dev->platform_data;
519 struct usbhs_hcd_omap *omap;
520 struct resource *res;
526 dev_err(dev, "Missing platform data\n");
530 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
532 dev_err(dev, "Memory allocation failed\n");
536 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh");
537 omap->uhh_base = devm_request_and_ioremap(dev, res);
538 if (!omap->uhh_base) {
539 dev_err(dev, "Resource request/ioremap failed\n");
540 return -EADDRNOTAVAIL;
545 pm_runtime_enable(dev);
547 platform_set_drvdata(pdev, omap);
548 pm_runtime_get_sync(dev);
550 omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
552 /* we need to call runtime suspend before we update omap->nports
553 * to prevent unbalanced clk_disable()
555 pm_runtime_put_sync(dev);
558 * If platform data contains nports then use that
559 * else make out number of ports from USBHS revision
562 omap->nports = pdata->nports;
564 switch (omap->usbhs_rev) {
565 case OMAP_USBHS_REV1:
568 case OMAP_USBHS_REV2:
572 omap->nports = OMAP3_HS_USB_PORTS;
574 "USB HOST Rev:0x%d not recognized, assuming %d ports\n",
575 omap->usbhs_rev, omap->nports);
580 i = sizeof(struct clk *) * omap->nports;
581 omap->utmi_clk = devm_kzalloc(dev, i, GFP_KERNEL);
582 omap->hsic480m_clk = devm_kzalloc(dev, i, GFP_KERNEL);
583 omap->hsic60m_clk = devm_kzalloc(dev, i, GFP_KERNEL);
585 if (!omap->utmi_clk || !omap->hsic480m_clk || !omap->hsic60m_clk) {
586 dev_err(dev, "Memory allocation failed\n");
591 need_logic_fck = false;
592 for (i = 0; i < omap->nports; i++) {
593 if (is_ehci_phy_mode(i) || is_ehci_tll_mode(i) ||
594 is_ehci_hsic_mode(i))
595 need_logic_fck |= true;
598 omap->ehci_logic_fck = ERR_PTR(-EINVAL);
599 if (need_logic_fck) {
600 omap->ehci_logic_fck = clk_get(dev, "ehci_logic_fck");
601 if (IS_ERR(omap->ehci_logic_fck)) {
602 ret = PTR_ERR(omap->ehci_logic_fck);
603 dev_dbg(dev, "ehci_logic_fck failed:%d\n", ret);
607 omap->utmi_p1_gfclk = clk_get(dev, "utmi_p1_gfclk");
608 if (IS_ERR(omap->utmi_p1_gfclk)) {
609 ret = PTR_ERR(omap->utmi_p1_gfclk);
610 dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret);
614 omap->utmi_p2_gfclk = clk_get(dev, "utmi_p2_gfclk");
615 if (IS_ERR(omap->utmi_p2_gfclk)) {
616 ret = PTR_ERR(omap->utmi_p2_gfclk);
617 dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
621 omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
622 if (IS_ERR(omap->xclk60mhsp1_ck)) {
623 ret = PTR_ERR(omap->xclk60mhsp1_ck);
624 dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
625 goto err_xclk60mhsp1;
628 omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
629 if (IS_ERR(omap->xclk60mhsp2_ck)) {
630 ret = PTR_ERR(omap->xclk60mhsp2_ck);
631 dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
632 goto err_xclk60mhsp2;
635 omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
636 if (IS_ERR(omap->init_60m_fclk)) {
637 ret = PTR_ERR(omap->init_60m_fclk);
638 dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
642 for (i = 0; i < omap->nports; i++) {
645 /* clock names are indexed from 1*/
646 snprintf(clkname, sizeof(clkname),
647 "usb_host_hs_utmi_p%d_clk", i + 1);
649 /* If a clock is not found we won't bail out as not all
650 * platforms have all clocks and we can function without
653 omap->utmi_clk[i] = clk_get(dev, clkname);
654 if (IS_ERR(omap->utmi_clk[i]))
655 dev_dbg(dev, "Failed to get clock : %s : %ld\n",
656 clkname, PTR_ERR(omap->utmi_clk[i]));
658 snprintf(clkname, sizeof(clkname),
659 "usb_host_hs_hsic480m_p%d_clk", i + 1);
660 omap->hsic480m_clk[i] = clk_get(dev, clkname);
661 if (IS_ERR(omap->hsic480m_clk[i]))
662 dev_dbg(dev, "Failed to get clock : %s : %ld\n",
663 clkname, PTR_ERR(omap->hsic480m_clk[i]));
665 snprintf(clkname, sizeof(clkname),
666 "usb_host_hs_hsic60m_p%d_clk", i + 1);
667 omap->hsic60m_clk[i] = clk_get(dev, clkname);
668 if (IS_ERR(omap->hsic60m_clk[i]))
669 dev_dbg(dev, "Failed to get clock : %s : %ld\n",
670 clkname, PTR_ERR(omap->hsic60m_clk[i]));
673 if (is_ehci_phy_mode(pdata->port_mode[0])) {
674 /* for OMAP3 , the clk set paretn fails */
675 ret = clk_set_parent(omap->utmi_p1_gfclk,
676 omap->xclk60mhsp1_ck);
678 dev_err(dev, "xclk60mhsp1_ck set parent"
679 "failed error:%d\n", ret);
680 } else if (is_ehci_tll_mode(pdata->port_mode[0])) {
681 ret = clk_set_parent(omap->utmi_p1_gfclk,
682 omap->init_60m_fclk);
684 dev_err(dev, "init_60m_fclk set parent"
685 "failed error:%d\n", ret);
688 if (is_ehci_phy_mode(pdata->port_mode[1])) {
689 ret = clk_set_parent(omap->utmi_p2_gfclk,
690 omap->xclk60mhsp2_ck);
692 dev_err(dev, "xclk60mhsp2_ck set parent"
693 "failed error:%d\n", ret);
694 } else if (is_ehci_tll_mode(pdata->port_mode[1])) {
695 ret = clk_set_parent(omap->utmi_p2_gfclk,
696 omap->init_60m_fclk);
698 dev_err(dev, "init_60m_fclk set parent"
699 "failed error:%d\n", ret);
702 omap_usbhs_init(dev);
703 ret = omap_usbhs_alloc_children(pdev);
705 dev_err(dev, "omap_usbhs_alloc_children failed\n");
712 omap_usbhs_deinit(&pdev->dev);
714 for (i = 0; i < omap->nports; i++) {
715 if (!IS_ERR(omap->utmi_clk[i]))
716 clk_put(omap->utmi_clk[i]);
717 if (!IS_ERR(omap->hsic60m_clk[i]))
718 clk_put(omap->hsic60m_clk[i]);
719 if (!IS_ERR(omap->hsic480m_clk[i]))
720 clk_put(omap->hsic480m_clk[i]);
723 clk_put(omap->init_60m_fclk);
726 clk_put(omap->xclk60mhsp2_ck);
729 clk_put(omap->xclk60mhsp1_ck);
732 clk_put(omap->utmi_p2_gfclk);
735 clk_put(omap->utmi_p1_gfclk);
738 if (!IS_ERR(omap->ehci_logic_fck))
739 clk_put(omap->ehci_logic_fck);
742 pm_runtime_disable(dev);
748 * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
749 * @pdev: USB Host Controller being removed
751 * Reverses the effect of usbhs_omap_probe().
753 static int usbhs_omap_remove(struct platform_device *pdev)
755 struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
758 omap_usbhs_deinit(&pdev->dev);
760 for (i = 0; i < omap->nports; i++) {
761 if (!IS_ERR(omap->utmi_clk[i]))
762 clk_put(omap->utmi_clk[i]);
763 if (!IS_ERR(omap->hsic60m_clk[i]))
764 clk_put(omap->hsic60m_clk[i]);
765 if (!IS_ERR(omap->hsic480m_clk[i]))
766 clk_put(omap->hsic480m_clk[i]);
769 clk_put(omap->init_60m_fclk);
770 clk_put(omap->utmi_p1_gfclk);
771 clk_put(omap->utmi_p2_gfclk);
772 clk_put(omap->xclk60mhsp2_ck);
773 clk_put(omap->xclk60mhsp1_ck);
775 if (!IS_ERR(omap->ehci_logic_fck))
776 clk_put(omap->ehci_logic_fck);
778 pm_runtime_disable(&pdev->dev);
783 static const struct dev_pm_ops usbhsomap_dev_pm_ops = {
784 .runtime_suspend = usbhs_runtime_suspend,
785 .runtime_resume = usbhs_runtime_resume,
788 static struct platform_driver usbhs_omap_driver = {
790 .name = (char *)usbhs_driver_name,
791 .owner = THIS_MODULE,
792 .pm = &usbhsomap_dev_pm_ops,
794 .remove = __exit_p(usbhs_omap_remove),
797 MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
798 MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
799 MODULE_LICENSE("GPL v2");
800 MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI");
802 static int __init omap_usbhs_drvinit(void)
804 return platform_driver_probe(&usbhs_omap_driver, usbhs_omap_probe);
808 * init before ehci and ohci drivers;
809 * The usbhs core driver should be initialized much before
810 * the omap ehci and ohci probe functions are called.
811 * This usbhs core driver should be initialized after
814 fs_initcall_sync(omap_usbhs_drvinit);
816 static void __exit omap_usbhs_drvexit(void)
818 platform_driver_unregister(&usbhs_omap_driver);
820 module_exit(omap_usbhs_drvexit);