2 * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Keshava Munegowda <keshava_mgowda@ti.com>
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 of
9 * the License as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/types.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/clk.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/spinlock.h>
27 #include <linux/gpio.h>
28 #include <linux/platform_device.h>
29 #include <linux/platform_data/usb-omap.h>
30 #include <linux/pm_runtime.h>
34 #define USBHS_DRIVER_NAME "usbhs_omap"
35 #define OMAP_EHCI_DEVICE "ehci-omap"
36 #define OMAP_OHCI_DEVICE "ohci-omap3"
38 /* OMAP USBHOST Register addresses */
40 /* UHH Register Set */
41 #define OMAP_UHH_REVISION (0x00)
42 #define OMAP_UHH_SYSCONFIG (0x10)
43 #define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
44 #define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
45 #define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
46 #define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
47 #define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
48 #define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
50 #define OMAP_UHH_SYSSTATUS (0x14)
51 #define OMAP_UHH_HOSTCONFIG (0x40)
52 #define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
53 #define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
54 #define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
55 #define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
56 #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
57 #define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
58 #define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
59 #define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
60 #define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
61 #define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
62 #define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
63 #define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31)
65 /* OMAP4-specific defines */
66 #define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2)
67 #define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2)
68 #define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4)
69 #define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4)
70 #define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0)
72 #define OMAP4_P1_MODE_CLEAR (3 << 16)
73 #define OMAP4_P1_MODE_TLL (1 << 16)
74 #define OMAP4_P1_MODE_HSIC (3 << 16)
75 #define OMAP4_P2_MODE_CLEAR (3 << 18)
76 #define OMAP4_P2_MODE_TLL (1 << 18)
77 #define OMAP4_P2_MODE_HSIC (3 << 18)
79 #define OMAP_UHH_DEBUG_CSR (0x44)
81 /* Values of UHH_REVISION - Note: these are not given in the TRM */
82 #define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */
83 #define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */
85 #define is_omap_usbhs_rev1(x) (x->usbhs_rev == OMAP_USBHS_REV1)
86 #define is_omap_usbhs_rev2(x) (x->usbhs_rev == OMAP_USBHS_REV2)
88 #define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY)
89 #define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
90 #define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC)
93 struct usbhs_hcd_omap {
96 struct clk *xclk60mhsp1_ck;
97 struct clk *xclk60mhsp2_ck;
98 struct clk *utmi_p1_fck;
99 struct clk *usbhost_p1_fck;
100 struct clk *utmi_p2_fck;
101 struct clk *usbhost_p2_fck;
102 struct clk *init_60m_fclk;
103 struct clk *ehci_logic_fck;
105 void __iomem *uhh_base;
107 struct usbhs_omap_platform_data *pdata;
112 /*-------------------------------------------------------------------------*/
114 const char usbhs_driver_name[] = USBHS_DRIVER_NAME;
115 static u64 usbhs_dmamask = DMA_BIT_MASK(32);
117 /*-------------------------------------------------------------------------*/
119 static inline void usbhs_write(void __iomem *base, u32 reg, u32 val)
121 __raw_writel(val, base + reg);
124 static inline u32 usbhs_read(void __iomem *base, u32 reg)
126 return __raw_readl(base + reg);
129 static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val)
131 __raw_writeb(val, base + reg);
134 static inline u8 usbhs_readb(void __iomem *base, u8 reg)
136 return __raw_readb(base + reg);
139 /*-------------------------------------------------------------------------*/
141 static struct platform_device *omap_usbhs_alloc_child(const char *name,
142 struct resource *res, int num_resources, void *pdata,
143 size_t pdata_size, struct device *dev)
145 struct platform_device *child;
148 child = platform_device_alloc(name, 0);
151 dev_err(dev, "platform_device_alloc %s failed\n", name);
155 ret = platform_device_add_resources(child, res, num_resources);
157 dev_err(dev, "platform_device_add_resources failed\n");
161 ret = platform_device_add_data(child, pdata, pdata_size);
163 dev_err(dev, "platform_device_add_data failed\n");
167 child->dev.dma_mask = &usbhs_dmamask;
168 dma_set_coherent_mask(&child->dev, DMA_BIT_MASK(32));
169 child->dev.parent = dev;
171 ret = platform_device_add(child);
173 dev_err(dev, "platform_device_add failed\n");
180 platform_device_put(child);
186 static int omap_usbhs_alloc_children(struct platform_device *pdev)
188 struct device *dev = &pdev->dev;
189 struct usbhs_omap_platform_data *pdata = dev->platform_data;
190 struct platform_device *ehci;
191 struct platform_device *ohci;
192 struct resource *res;
193 struct resource resources[2];
196 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci");
198 dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n");
204 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq");
206 dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n");
212 ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, pdata,
213 sizeof(*pdata), dev);
216 dev_err(dev, "omap_usbhs_alloc_child failed\n");
221 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci");
223 dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n");
229 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq");
231 dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n");
237 ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, pdata,
238 sizeof(*pdata), dev);
240 dev_err(dev, "omap_usbhs_alloc_child failed\n");
248 platform_device_unregister(ehci);
254 static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
257 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
258 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
259 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
260 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
261 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
262 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
263 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
264 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
265 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
266 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
274 static int usbhs_runtime_resume(struct device *dev)
276 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
277 struct usbhs_omap_platform_data *pdata = omap->pdata;
280 dev_dbg(dev, "usbhs_runtime_resume\n");
283 spin_lock_irqsave(&omap->lock, flags);
285 if (omap->ehci_logic_fck && !IS_ERR(omap->ehci_logic_fck))
286 clk_enable(omap->ehci_logic_fck);
288 if (is_ehci_tll_mode(pdata->port_mode[0]))
289 clk_enable(omap->usbhost_p1_fck);
290 if (is_ehci_tll_mode(pdata->port_mode[1]))
291 clk_enable(omap->usbhost_p2_fck);
293 clk_enable(omap->utmi_p1_fck);
294 clk_enable(omap->utmi_p2_fck);
296 spin_unlock_irqrestore(&omap->lock, flags);
301 static int usbhs_runtime_suspend(struct device *dev)
303 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
304 struct usbhs_omap_platform_data *pdata = omap->pdata;
307 dev_dbg(dev, "usbhs_runtime_suspend\n");
309 spin_lock_irqsave(&omap->lock, flags);
311 if (is_ehci_tll_mode(pdata->port_mode[0]))
312 clk_disable(omap->usbhost_p1_fck);
313 if (is_ehci_tll_mode(pdata->port_mode[1]))
314 clk_disable(omap->usbhost_p2_fck);
316 clk_disable(omap->utmi_p2_fck);
317 clk_disable(omap->utmi_p1_fck);
319 if (omap->ehci_logic_fck && !IS_ERR(omap->ehci_logic_fck))
320 clk_disable(omap->ehci_logic_fck);
322 spin_unlock_irqrestore(&omap->lock, flags);
328 static void omap_usbhs_init(struct device *dev)
330 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
331 struct usbhs_omap_platform_data *pdata = omap->pdata;
335 dev_dbg(dev, "starting TI HSUSB Controller\n");
337 if (pdata->phy_reset) {
338 if (gpio_is_valid(pdata->reset_gpio_port[0]))
339 gpio_request_one(pdata->reset_gpio_port[0],
340 GPIOF_OUT_INIT_LOW, "USB1 PHY reset");
342 if (gpio_is_valid(pdata->reset_gpio_port[1]))
343 gpio_request_one(pdata->reset_gpio_port[1],
344 GPIOF_OUT_INIT_LOW, "USB2 PHY reset");
346 /* Hold the PHY in RESET for enough time till DIR is high */
350 pm_runtime_get_sync(dev);
351 spin_lock_irqsave(&omap->lock, flags);
353 reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
354 /* setup ULPI bypass and burst configurations */
355 reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
356 | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
357 | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
358 reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK;
359 reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
361 if (is_omap_usbhs_rev1(omap)) {
362 if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED)
363 reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
364 if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED)
365 reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
366 if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED)
367 reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
369 /* Bypass the TLL module for PHY mode operation */
370 if (pdata->single_ulpi_bypass) {
371 dev_dbg(dev, "OMAP3 ES version <= ES2.1\n");
372 if (is_ehci_phy_mode(pdata->port_mode[0]) ||
373 is_ehci_phy_mode(pdata->port_mode[1]) ||
374 is_ehci_phy_mode(pdata->port_mode[2]))
375 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
377 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
379 dev_dbg(dev, "OMAP3 ES version > ES2.1\n");
380 if (is_ehci_phy_mode(pdata->port_mode[0]))
381 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
383 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
384 if (is_ehci_phy_mode(pdata->port_mode[1]))
385 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
387 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
388 if (is_ehci_phy_mode(pdata->port_mode[2]))
389 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
391 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
393 } else if (is_omap_usbhs_rev2(omap)) {
394 /* Clear port mode fields for PHY mode*/
395 reg &= ~OMAP4_P1_MODE_CLEAR;
396 reg &= ~OMAP4_P2_MODE_CLEAR;
398 if (is_ehci_tll_mode(pdata->port_mode[0]) ||
399 (is_ohci_port(pdata->port_mode[0])))
400 reg |= OMAP4_P1_MODE_TLL;
401 else if (is_ehci_hsic_mode(pdata->port_mode[0]))
402 reg |= OMAP4_P1_MODE_HSIC;
404 if (is_ehci_tll_mode(pdata->port_mode[1]) ||
405 (is_ohci_port(pdata->port_mode[1])))
406 reg |= OMAP4_P2_MODE_TLL;
407 else if (is_ehci_hsic_mode(pdata->port_mode[1]))
408 reg |= OMAP4_P2_MODE_HSIC;
411 usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
412 dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
414 spin_unlock_irqrestore(&omap->lock, flags);
416 pm_runtime_put_sync(dev);
417 if (pdata->phy_reset) {
418 /* Hold the PHY in RESET for enough time till
419 * PHY is settled and ready
423 if (gpio_is_valid(pdata->reset_gpio_port[0]))
424 gpio_set_value_cansleep
425 (pdata->reset_gpio_port[0], 1);
427 if (gpio_is_valid(pdata->reset_gpio_port[1]))
428 gpio_set_value_cansleep
429 (pdata->reset_gpio_port[1], 1);
433 static void omap_usbhs_deinit(struct device *dev)
435 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
436 struct usbhs_omap_platform_data *pdata = omap->pdata;
438 if (pdata->phy_reset) {
439 if (gpio_is_valid(pdata->reset_gpio_port[0]))
440 gpio_free(pdata->reset_gpio_port[0]);
442 if (gpio_is_valid(pdata->reset_gpio_port[1]))
443 gpio_free(pdata->reset_gpio_port[1]);
449 * usbhs_omap_probe - initialize TI-based HCDs
451 * Allocates basic resources for this USB host controller.
453 static int usbhs_omap_probe(struct platform_device *pdev)
455 struct device *dev = &pdev->dev;
456 struct usbhs_omap_platform_data *pdata = dev->platform_data;
457 struct usbhs_hcd_omap *omap;
458 struct resource *res;
463 dev_err(dev, "Missing platform data\n");
467 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
469 dev_err(dev, "Memory allocation failed\n");
473 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh");
474 omap->uhh_base = devm_request_and_ioremap(dev, res);
475 if (!omap->uhh_base) {
476 dev_err(dev, "Resource request/ioremap failed\n");
477 return -EADDRNOTAVAIL;
480 spin_lock_init(&omap->lock);
484 pm_runtime_enable(dev);
486 platform_set_drvdata(pdev, omap);
487 pm_runtime_get_sync(dev);
489 omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
491 /* we need to call runtime suspend before we update omap->nports
492 * to prevent unbalanced clk_disable()
494 pm_runtime_put_sync(dev);
497 * If platform data contains nports then use that
498 * else make out number of ports from USBHS revision
501 omap->nports = pdata->nports;
503 switch (omap->usbhs_rev) {
504 case OMAP_USBHS_REV1:
507 case OMAP_USBHS_REV2:
511 omap->nports = OMAP3_HS_USB_PORTS;
513 "USB HOST Rev:0x%d not recognized, assuming %d ports\n",
514 omap->usbhs_rev, omap->nports);
519 for (i = 0; i < omap->nports; i++)
520 if (is_ehci_phy_mode(i) || is_ehci_tll_mode(i) ||
521 is_ehci_hsic_mode(i)) {
522 omap->ehci_logic_fck = clk_get(dev, "ehci_logic_fck");
523 if (IS_ERR(omap->ehci_logic_fck)) {
524 ret = PTR_ERR(omap->ehci_logic_fck);
525 dev_warn(dev, "ehci_logic_fck failed:%d\n",
531 omap->utmi_p1_fck = clk_get(dev, "utmi_p1_gfclk");
532 if (IS_ERR(omap->utmi_p1_fck)) {
533 ret = PTR_ERR(omap->utmi_p1_fck);
534 dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret);
538 omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
539 if (IS_ERR(omap->xclk60mhsp1_ck)) {
540 ret = PTR_ERR(omap->xclk60mhsp1_ck);
541 dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
542 goto err_utmi_p1_fck;
545 omap->utmi_p2_fck = clk_get(dev, "utmi_p2_gfclk");
546 if (IS_ERR(omap->utmi_p2_fck)) {
547 ret = PTR_ERR(omap->utmi_p2_fck);
548 dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
549 goto err_xclk60mhsp1_ck;
552 omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
553 if (IS_ERR(omap->xclk60mhsp2_ck)) {
554 ret = PTR_ERR(omap->xclk60mhsp2_ck);
555 dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
556 goto err_utmi_p2_fck;
559 omap->usbhost_p1_fck = clk_get(dev, "usb_host_hs_utmi_p1_clk");
560 if (IS_ERR(omap->usbhost_p1_fck)) {
561 ret = PTR_ERR(omap->usbhost_p1_fck);
562 dev_err(dev, "usbhost_p1_fck failed error:%d\n", ret);
563 goto err_xclk60mhsp2_ck;
566 omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk");
567 if (IS_ERR(omap->usbhost_p2_fck)) {
568 ret = PTR_ERR(omap->usbhost_p2_fck);
569 dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret);
570 goto err_usbhost_p1_fck;
573 omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
574 if (IS_ERR(omap->init_60m_fclk)) {
575 ret = PTR_ERR(omap->init_60m_fclk);
576 dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
577 goto err_usbhost_p2_fck;
580 if (is_ehci_phy_mode(pdata->port_mode[0])) {
581 /* for OMAP3 , the clk set paretn fails */
582 ret = clk_set_parent(omap->utmi_p1_fck,
583 omap->xclk60mhsp1_ck);
585 dev_err(dev, "xclk60mhsp1_ck set parent"
586 "failed error:%d\n", ret);
587 } else if (is_ehci_tll_mode(pdata->port_mode[0])) {
588 ret = clk_set_parent(omap->utmi_p1_fck,
589 omap->init_60m_fclk);
591 dev_err(dev, "init_60m_fclk set parent"
592 "failed error:%d\n", ret);
595 if (is_ehci_phy_mode(pdata->port_mode[1])) {
596 ret = clk_set_parent(omap->utmi_p2_fck,
597 omap->xclk60mhsp2_ck);
599 dev_err(dev, "xclk60mhsp2_ck set parent"
600 "failed error:%d\n", ret);
601 } else if (is_ehci_tll_mode(pdata->port_mode[1])) {
602 ret = clk_set_parent(omap->utmi_p2_fck,
603 omap->init_60m_fclk);
605 dev_err(dev, "init_60m_fclk set parent"
606 "failed error:%d\n", ret);
609 omap_usbhs_init(dev);
610 ret = omap_usbhs_alloc_children(pdev);
612 dev_err(dev, "omap_usbhs_alloc_children failed\n");
619 omap_usbhs_deinit(&pdev->dev);
620 clk_put(omap->init_60m_fclk);
623 clk_put(omap->usbhost_p2_fck);
626 clk_put(omap->usbhost_p1_fck);
629 clk_put(omap->xclk60mhsp2_ck);
632 clk_put(omap->utmi_p2_fck);
635 clk_put(omap->xclk60mhsp1_ck);
638 clk_put(omap->utmi_p1_fck);
641 clk_put(omap->ehci_logic_fck);
642 pm_runtime_disable(dev);
648 * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
649 * @pdev: USB Host Controller being removed
651 * Reverses the effect of usbhs_omap_probe().
653 static int usbhs_omap_remove(struct platform_device *pdev)
655 struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
657 omap_usbhs_deinit(&pdev->dev);
658 clk_put(omap->init_60m_fclk);
659 clk_put(omap->usbhost_p2_fck);
660 clk_put(omap->usbhost_p1_fck);
661 clk_put(omap->xclk60mhsp2_ck);
662 clk_put(omap->utmi_p2_fck);
663 clk_put(omap->xclk60mhsp1_ck);
664 clk_put(omap->utmi_p1_fck);
665 clk_put(omap->ehci_logic_fck);
666 pm_runtime_disable(&pdev->dev);
671 static const struct dev_pm_ops usbhsomap_dev_pm_ops = {
672 .runtime_suspend = usbhs_runtime_suspend,
673 .runtime_resume = usbhs_runtime_resume,
676 static struct platform_driver usbhs_omap_driver = {
678 .name = (char *)usbhs_driver_name,
679 .owner = THIS_MODULE,
680 .pm = &usbhsomap_dev_pm_ops,
682 .remove = __exit_p(usbhs_omap_remove),
685 MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
686 MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
687 MODULE_LICENSE("GPL v2");
688 MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI");
690 static int __init omap_usbhs_drvinit(void)
692 return platform_driver_probe(&usbhs_omap_driver, usbhs_omap_probe);
696 * init before ehci and ohci drivers;
697 * The usbhs core driver should be initialized much before
698 * the omap ehci and ohci probe functions are called.
699 * This usbhs core driver should be initialized after
702 fs_initcall_sync(omap_usbhs_drvinit);
704 static void __exit omap_usbhs_drvexit(void)
706 platform_driver_unregister(&usbhs_omap_driver);
708 module_exit(omap_usbhs_drvexit);