drivers/mfd/lpc_ich.c

   1 /*
   2  *  lpc_ich.c - LPC interface for Intel ICH
   3  *
   4  *  LPC bridge function of the Intel ICH contains many other
   5  *  functional units, such as Interrupt controllers, Timers,
   6  *  Power Management, System Management, GPIO, RTC, and LPC
   7  *  Configuration Registers.
   8  *
   9  *  This driver is derived from lpc_sch.
  10
  11  *  Copyright (c) 2011 Extreme Engineering Solution, Inc.
  12  *  Author: Aaron Sierra <asierra@xes-inc.com>
  13  *
  14  *  This program is free software; you can redistribute it and/or modify
  15  *  it under the terms of the GNU General Public License 2 as published
  16  *  by the Free Software Foundation.
  17  *
  18  *  This program is distributed in the hope that it will be useful,
  19  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *  GNU General Public License for more details.
  22  *
  23  *  You should have received a copy of the GNU General Public License
  24  *  along with this program; see the file COPYING.  If not, write to
  25  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  26  *
  27  *  This driver supports the following I/O Controller hubs:
  28  *      (See the intel documentation on http://developer.intel.com.)
  29  *      document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
  30  *      document number 290687-002, 298242-027: 82801BA (ICH2)
  31  *      document number 290733-003, 290739-013: 82801CA (ICH3-S)
  32  *      document number 290716-001, 290718-007: 82801CAM (ICH3-M)
  33  *      document number 290744-001, 290745-025: 82801DB (ICH4)
  34  *      document number 252337-001, 252663-008: 82801DBM (ICH4-M)
  35  *      document number 273599-001, 273645-002: 82801E (C-ICH)
  36  *      document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
  37  *      document number 300641-004, 300884-013: 6300ESB
  38  *      document number 301473-002, 301474-026: 82801F (ICH6)
  39  *      document number 313082-001, 313075-006: 631xESB, 632xESB
  40  *      document number 307013-003, 307014-024: 82801G (ICH7)
  41  *      document number 322896-001, 322897-001: NM10
  42  *      document number 313056-003, 313057-017: 82801H (ICH8)
  43  *      document number 316972-004, 316973-012: 82801I (ICH9)
  44  *      document number 319973-002, 319974-002: 82801J (ICH10)
  45  *      document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
  46  *      document number 320066-003, 320257-008: EP80597 (IICH)
  47  *      document number 324645-001, 324646-001: Cougar Point (CPT)
  48  *      document number TBD : Patsburg (PBG)
  49  *      document number TBD : DH89xxCC
  50  *      document number TBD : Panther Point
  51  *      document number TBD : Lynx Point
  52  *      document number TBD : Lynx Point-LP
  53  *      document number TBD : Wellsburg
  54  *      document number TBD : Avoton SoC
  55  */
  56
  57 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  58
  59 #include <linux/init.h>
  60 #include <linux/kernel.h>
  61 #include <linux/module.h>
  62 #include <linux/errno.h>
  63 #include <linux/acpi.h>
  64 #include <linux/pci.h>
  65 #include <linux/mfd/core.h>
  66 #include <linux/mfd/lpc_ich.h>
  67
  68 #define ACPIBASE                0x40
  69 #define ACPIBASE_GPE_OFF        0x28
  70 #define ACPIBASE_GPE_END        0x2f
  71 #define ACPIBASE_SMI_OFF        0x30
  72 #define ACPIBASE_SMI_END        0x33
  73 #define ACPIBASE_TCO_OFF        0x60
  74 #define ACPIBASE_TCO_END        0x7f
  75 #define ACPICTRL                0x44
  76
  77 #define ACPIBASE_GCS_OFF        0x3410
  78 #define ACPIBASE_GCS_END        0x3414
  79
  80 #define GPIOBASE_ICH0           0x58
  81 #define GPIOCTRL_ICH0           0x5C
  82 #define GPIOBASE_ICH6           0x48
  83 #define GPIOCTRL_ICH6           0x4C
  84
  85 #define RCBABASE                0xf0
  86
  87 #define wdt_io_res(i) wdt_res(0, i)
  88 #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)
  89 #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])
  90
  91 struct lpc_ich_cfg {
  92         int base;
  93         int ctrl;
  94         int save;
  95 };
  96
  97 struct lpc_ich_priv {
  98         int chipset;
  99         struct lpc_ich_cfg acpi;
 100         struct lpc_ich_cfg gpio;
 101 };
 102
 103 static struct resource wdt_ich_res[] = {
 104         /* ACPI - TCO */
 105         {
 106                 .flags = IORESOURCE_IO,
 107         },
 108         /* ACPI - SMI */
 109         {
 110                 .flags = IORESOURCE_IO,
 111         },
 112         /* GCS */
 113         {
 114                 .flags = IORESOURCE_MEM,
 115         },
 116 };
 117
 118 static struct resource gpio_ich_res[] = {
 119         /* GPIO */
 120         {
 121                 .flags = IORESOURCE_IO,
 122         },
 123         /* ACPI - GPE0 */
 124         {
 125                 .flags = IORESOURCE_IO,
 126         },
 127 };
 128
 129 enum lpc_cells {
 130         LPC_WDT = 0,
 131         LPC_GPIO,
 132 };
 133
 134 static struct mfd_cell lpc_ich_cells[] = {
 135         [LPC_WDT] = {
 136                 .name = "iTCO_wdt",
 137                 .num_resources = ARRAY_SIZE(wdt_ich_res),
 138                 .resources = wdt_ich_res,
 139                 .ignore_resource_conflicts = true,
 140         },
 141         [LPC_GPIO] = {
 142                 .name = "gpio_ich",
 143                 .num_resources = ARRAY_SIZE(gpio_ich_res),
 144                 .resources = gpio_ich_res,
 145                 .ignore_resource_conflicts = true,
 146         },
 147 };
 148
 149 /* chipset related info */
 150 enum lpc_chipsets {
 151         LPC_ICH = 0,    /* ICH */
 152         LPC_ICH0,       /* ICH0 */
 153         LPC_ICH2,       /* ICH2 */
 154         LPC_ICH2M,      /* ICH2-M */
 155         LPC_ICH3,       /* ICH3-S */
 156         LPC_ICH3M,      /* ICH3-M */
 157         LPC_ICH4,       /* ICH4 */
 158         LPC_ICH4M,      /* ICH4-M */
 159         LPC_CICH,       /* C-ICH */
 160         LPC_ICH5,       /* ICH5 & ICH5R */
 161         LPC_6300ESB,    /* 6300ESB */
 162         LPC_ICH6,       /* ICH6 & ICH6R */
 163         LPC_ICH6M,      /* ICH6-M */
 164         LPC_ICH6W,      /* ICH6W & ICH6RW */
 165         LPC_631XESB,    /* 631xESB/632xESB */
 166         LPC_ICH7,       /* ICH7 & ICH7R */
 167         LPC_ICH7DH,     /* ICH7DH */
 168         LPC_ICH7M,      /* ICH7-M & ICH7-U */
 169         LPC_ICH7MDH,    /* ICH7-M DH */
 170         LPC_NM10,       /* NM10 */
 171         LPC_ICH8,       /* ICH8 & ICH8R */
 172         LPC_ICH8DH,     /* ICH8DH */
 173         LPC_ICH8DO,     /* ICH8DO */
 174         LPC_ICH8M,      /* ICH8M */
 175         LPC_ICH8ME,     /* ICH8M-E */
 176         LPC_ICH9,       /* ICH9 */
 177         LPC_ICH9R,      /* ICH9R */
 178         LPC_ICH9DH,     /* ICH9DH */
 179         LPC_ICH9DO,     /* ICH9DO */
 180         LPC_ICH9M,      /* ICH9M */
 181         LPC_ICH9ME,     /* ICH9M-E */
 182         LPC_ICH10,      /* ICH10 */
 183         LPC_ICH10R,     /* ICH10R */
 184         LPC_ICH10D,     /* ICH10D */
 185         LPC_ICH10DO,    /* ICH10DO */
 186         LPC_PCH,        /* PCH Desktop Full Featured */
 187         LPC_PCHM,       /* PCH Mobile Full Featured */
 188         LPC_P55,        /* P55 */
 189         LPC_PM55,       /* PM55 */
 190         LPC_H55,        /* H55 */
 191         LPC_QM57,       /* QM57 */
 192         LPC_H57,        /* H57 */
 193         LPC_HM55,       /* HM55 */
 194         LPC_Q57,        /* Q57 */
 195         LPC_HM57,       /* HM57 */
 196         LPC_PCHMSFF,    /* PCH Mobile SFF Full Featured */
 197         LPC_QS57,       /* QS57 */
 198         LPC_3400,       /* 3400 */
 199         LPC_3420,       /* 3420 */
 200         LPC_3450,       /* 3450 */
 201         LPC_EP80579,    /* EP80579 */
 202         LPC_CPT,        /* Cougar Point */
 203         LPC_CPTD,       /* Cougar Point Desktop */
 204         LPC_CPTM,       /* Cougar Point Mobile */
 205         LPC_PBG,        /* Patsburg */
 206         LPC_DH89XXCC,   /* DH89xxCC */
 207         LPC_PPT,        /* Panther Point */
 208         LPC_LPT,        /* Lynx Point */
 209         LPC_LPT_LP,     /* Lynx Point-LP */
 210         LPC_WBG,        /* Wellsburg */
 211         LPC_AVN,        /* Avoton SoC */
 212 };
 213
 214 struct lpc_ich_info lpc_chipset_info[] = {
 215         [LPC_ICH] = {
 216                 .name = "ICH",
 217                 .iTCO_version = 1,
 218         },
 219         [LPC_ICH0] = {
 220                 .name = "ICH0",
 221                 .iTCO_version = 1,
 222         },
 223         [LPC_ICH2] = {
 224                 .name = "ICH2",
 225                 .iTCO_version = 1,
 226         },
 227         [LPC_ICH2M] = {
 228                 .name = "ICH2-M",
 229                 .iTCO_version = 1,
 230         },
 231         [LPC_ICH3] = {
 232                 .name = "ICH3-S",
 233                 .iTCO_version = 1,
 234         },
 235         [LPC_ICH3M] = {
 236                 .name = "ICH3-M",
 237                 .iTCO_version = 1,
 238         },
 239         [LPC_ICH4] = {
 240                 .name = "ICH4",
 241                 .iTCO_version = 1,
 242         },
 243         [LPC_ICH4M] = {
 244                 .name = "ICH4-M",
 245                 .iTCO_version = 1,
 246         },
 247         [LPC_CICH] = {
 248                 .name = "C-ICH",
 249                 .iTCO_version = 1,
 250         },
 251         [LPC_ICH5] = {
 252                 .name = "ICH5 or ICH5R",
 253                 .iTCO_version = 1,
 254         },
 255         [LPC_6300ESB] = {
 256                 .name = "6300ESB",
 257                 .iTCO_version = 1,
 258         },
 259         [LPC_ICH6] = {
 260                 .name = "ICH6 or ICH6R",
 261                 .iTCO_version = 2,
 262                 .gpio_version = ICH_V6_GPIO,
 263         },
 264         [LPC_ICH6M] = {
 265                 .name = "ICH6-M",
 266                 .iTCO_version = 2,
 267                 .gpio_version = ICH_V6_GPIO,
 268         },
 269         [LPC_ICH6W] = {
 270                 .name = "ICH6W or ICH6RW",
 271                 .iTCO_version = 2,
 272                 .gpio_version = ICH_V6_GPIO,
 273         },
 274         [LPC_631XESB] = {
 275                 .name = "631xESB/632xESB",
 276                 .iTCO_version = 2,
 277                 .gpio_version = ICH_V6_GPIO,
 278         },
 279         [LPC_ICH7] = {
 280                 .name = "ICH7 or ICH7R",
 281                 .iTCO_version = 2,
 282                 .gpio_version = ICH_V7_GPIO,
 283         },
 284         [LPC_ICH7DH] = {
 285                 .name = "ICH7DH",
 286                 .iTCO_version = 2,
 287                 .gpio_version = ICH_V7_GPIO,
 288         },
 289         [LPC_ICH7M] = {
 290                 .name = "ICH7-M or ICH7-U",
 291                 .iTCO_version = 2,
 292                 .gpio_version = ICH_V7_GPIO,
 293         },
 294         [LPC_ICH7MDH] = {
 295                 .name = "ICH7-M DH",
 296                 .iTCO_version = 2,
 297                 .gpio_version = ICH_V7_GPIO,
 298         },
 299         [LPC_NM10] = {
 300                 .name = "NM10",
 301                 .iTCO_version = 2,
 302         },
 303         [LPC_ICH8] = {
 304                 .name = "ICH8 or ICH8R",
 305                 .iTCO_version = 2,
 306                 .gpio_version = ICH_V7_GPIO,
 307         },
 308         [LPC_ICH8DH] = {
 309                 .name = "ICH8DH",
 310                 .iTCO_version = 2,
 311                 .gpio_version = ICH_V7_GPIO,
 312         },
 313         [LPC_ICH8DO] = {
 314                 .name = "ICH8DO",
 315                 .iTCO_version = 2,
 316                 .gpio_version = ICH_V7_GPIO,
 317         },
 318         [LPC_ICH8M] = {
 319                 .name = "ICH8M",
 320                 .iTCO_version = 2,
 321                 .gpio_version = ICH_V7_GPIO,
 322         },
 323         [LPC_ICH8ME] = {
 324                 .name = "ICH8M-E",
 325                 .iTCO_version = 2,
 326                 .gpio_version = ICH_V7_GPIO,
 327         },
 328         [LPC_ICH9] = {
 329                 .name = "ICH9",
 330                 .iTCO_version = 2,
 331                 .gpio_version = ICH_V9_GPIO,
 332         },
 333         [LPC_ICH9R] = {
 334                 .name = "ICH9R",
 335                 .iTCO_version = 2,
 336                 .gpio_version = ICH_V9_GPIO,
 337         },
 338         [LPC_ICH9DH] = {
 339                 .name = "ICH9DH",
 340                 .iTCO_version = 2,
 341                 .gpio_version = ICH_V9_GPIO,
 342         },
 343         [LPC_ICH9DO] = {
 344                 .name = "ICH9DO",
 345                 .iTCO_version = 2,
 346                 .gpio_version = ICH_V9_GPIO,
 347         },
 348         [LPC_ICH9M] = {
 349                 .name = "ICH9M",
 350                 .iTCO_version = 2,
 351                 .gpio_version = ICH_V9_GPIO,
 352         },
 353         [LPC_ICH9ME] = {
 354                 .name = "ICH9M-E",
 355                 .iTCO_version = 2,
 356                 .gpio_version = ICH_V9_GPIO,
 357         },
 358         [LPC_ICH10] = {
 359                 .name = "ICH10",
 360                 .iTCO_version = 2,
 361                 .gpio_version = ICH_V10CONS_GPIO,
 362         },
 363         [LPC_ICH10R] = {
 364                 .name = "ICH10R",
 365                 .iTCO_version = 2,
 366                 .gpio_version = ICH_V10CONS_GPIO,
 367         },
 368         [LPC_ICH10D] = {
 369                 .name = "ICH10D",
 370                 .iTCO_version = 2,
 371                 .gpio_version = ICH_V10CORP_GPIO,
 372         },
 373         [LPC_ICH10DO] = {
 374                 .name = "ICH10DO",
 375                 .iTCO_version = 2,
 376                 .gpio_version = ICH_V10CORP_GPIO,
 377         },
 378         [LPC_PCH] = {
 379                 .name = "PCH Desktop Full Featured",
 380                 .iTCO_version = 2,
 381                 .gpio_version = ICH_V5_GPIO,
 382         },
 383         [LPC_PCHM] = {
 384                 .name = "PCH Mobile Full Featured",
 385                 .iTCO_version = 2,
 386                 .gpio_version = ICH_V5_GPIO,
 387         },
 388         [LPC_P55] = {
 389                 .name = "P55",
 390                 .iTCO_version = 2,
 391                 .gpio_version = ICH_V5_GPIO,
 392         },
 393         [LPC_PM55] = {
 394                 .name = "PM55",
 395                 .iTCO_version = 2,
 396                 .gpio_version = ICH_V5_GPIO,
 397         },
 398         [LPC_H55] = {
 399                 .name = "H55",
 400                 .iTCO_version = 2,
 401                 .gpio_version = ICH_V5_GPIO,
 402         },
 403         [LPC_QM57] = {
 404                 .name = "QM57",
 405                 .iTCO_version = 2,
 406                 .gpio_version = ICH_V5_GPIO,
 407         },
 408         [LPC_H57] = {
 409                 .name = "H57",
 410                 .iTCO_version = 2,
 411                 .gpio_version = ICH_V5_GPIO,
 412         },
 413         [LPC_HM55] = {
 414                 .name = "HM55",
 415                 .iTCO_version = 2,
 416                 .gpio_version = ICH_V5_GPIO,
 417         },
 418         [LPC_Q57] = {
 419                 .name = "Q57",
 420                 .iTCO_version = 2,
 421                 .gpio_version = ICH_V5_GPIO,
 422         },
 423         [LPC_HM57] = {
 424                 .name = "HM57",
 425                 .iTCO_version = 2,
 426                 .gpio_version = ICH_V5_GPIO,
 427         },
 428         [LPC_PCHMSFF] = {
 429                 .name = "PCH Mobile SFF Full Featured",
 430                 .iTCO_version = 2,
 431                 .gpio_version = ICH_V5_GPIO,
 432         },
 433         [LPC_QS57] = {
 434                 .name = "QS57",
 435                 .iTCO_version = 2,
 436                 .gpio_version = ICH_V5_GPIO,
 437         },
 438         [LPC_3400] = {
 439                 .name = "3400",
 440                 .iTCO_version = 2,
 441                 .gpio_version = ICH_V5_GPIO,
 442         },
 443         [LPC_3420] = {
 444                 .name = "3420",
 445                 .iTCO_version = 2,
 446                 .gpio_version = ICH_V5_GPIO,
 447         },
 448         [LPC_3450] = {
 449                 .name = "3450",
 450                 .iTCO_version = 2,
 451                 .gpio_version = ICH_V5_GPIO,
 452         },
 453         [LPC_EP80579] = {
 454                 .name = "EP80579",
 455                 .iTCO_version = 2,
 456         },
 457         [LPC_CPT] = {
 458                 .name = "Cougar Point",
 459                 .iTCO_version = 2,
 460                 .gpio_version = ICH_V5_GPIO,
 461         },
 462         [LPC_CPTD] = {
 463                 .name = "Cougar Point Desktop",
 464                 .iTCO_version = 2,
 465                 .gpio_version = ICH_V5_GPIO,
 466         },
 467         [LPC_CPTM] = {
 468                 .name = "Cougar Point Mobile",
 469                 .iTCO_version = 2,
 470                 .gpio_version = ICH_V5_GPIO,
 471         },
 472         [LPC_PBG] = {
 473                 .name = "Patsburg",
 474                 .iTCO_version = 2,
 475         },
 476         [LPC_DH89XXCC] = {
 477                 .name = "DH89xxCC",
 478                 .iTCO_version = 2,
 479         },
 480         [LPC_PPT] = {
 481                 .name = "Panther Point",
 482                 .iTCO_version = 2,
 483         },
 484         [LPC_LPT] = {
 485                 .name = "Lynx Point",
 486                 .iTCO_version = 2,
 487         },
 488         [LPC_LPT_LP] = {
 489                 .name = "Lynx Point_LP",
 490                 .iTCO_version = 2,
 491         },
 492         [LPC_WBG] = {
 493                 .name = "Wellsburg",
 494                 .iTCO_version = 2,
 495         },
 496         [LPC_AVN] = {
 497                 .name = "Avoton SoC",
 498                 .iTCO_version = 1,
 499         },
 500 };
 501
 502 /*
 503  * This data only exists for exporting the supported PCI ids
 504  * via MODULE_DEVICE_TABLE.  We do not actually register a
 505  * pci_driver, because the I/O Controller Hub has also other
 506  * functions that probably will be registered by other drivers.
 507  */
 508 static DEFINE_PCI_DEVICE_TABLE(lpc_ich_ids) = {
 509         { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH},
 510         { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0},
 511         { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2},
 512         { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M},
 513         { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3},
 514         { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M},
 515         { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4},
 516         { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M},
 517         { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH},
 518         { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5},
 519         { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB},
 520         { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6},
 521         { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M},
 522         { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W},
 523         { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB},
 524         { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB},
 525         { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB},
 526         { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB},
 527         { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB},
 528         { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB},
 529         { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB},
 530         { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB},
 531         { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB},
 532         { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB},
 533         { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB},
 534         { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB},
 535         { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB},
 536         { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB},
 537         { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB},
 538         { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB},
 539         { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7},
 540         { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH},
 541         { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M},
 542         { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH},
 543         { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10},
 544         { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8},
 545         { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH},
 546         { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO},
 547         { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M},
 548         { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME},
 549         { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9},
 550         { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R},
 551         { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH},
 552         { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO},
 553         { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M},
 554         { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME},
 555         { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10},
 556         { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R},
 557         { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D},
 558         { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO},
 559         { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH},
 560         { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM},
 561         { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55},
 562         { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55},
 563         { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55},
 564         { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57},
 565         { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57},
 566         { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55},
 567         { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57},
 568         { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57},
 569         { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF},
 570         { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57},
 571         { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400},
 572         { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
 573         { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
 574         { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
 575         { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT},
 576         { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD},
 577         { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM},
 578         { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT},
 579         { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT},
 580         { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT},
 581         { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT},
 582         { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT},
 583         { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT},
 584         { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT},
 585         { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT},
 586         { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT},
 587         { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT},
 588         { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT},
 589         { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT},
 590         { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT},
 591         { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT},
 592         { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT},
 593         { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT},
 594         { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT},
 595         { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT},
 596         { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT},
 597         { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT},
 598         { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT},
 599         { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT},
 600         { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT},
 601         { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT},
 602         { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT},
 603         { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT},
 604         { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT},
 605         { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT},
 606         { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG},
 607         { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG},
 608         { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC},
 609         { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT},
 610         { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT},
 611         { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT},
 612         { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT},
 613         { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT},
 614         { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT},
 615         { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT},
 616         { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT},
 617         { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT},
 618         { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT},
 619         { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT},
 620         { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT},
 621         { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT},
 622         { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT},
 623         { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT},
 624         { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT},
 625         { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT},
 626         { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT},
 627         { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT},
 628         { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT},
 629         { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT},
 630         { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT},
 631         { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT},
 632         { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT},
 633         { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT},
 634         { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT},
 635         { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT},
 636         { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT},
 637         { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT},
 638         { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT},
 639         { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT},
 640         { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT},
 641         { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
 642         { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
 643         { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
 644         { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT},
 645         { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT},
 646         { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT},
 647         { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT},
 648         { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT},
 649         { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT},
 650         { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT},
 651         { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT},
 652         { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT},
 653         { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT},
 654         { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT},
 655         { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT},
 656         { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT},
 657         { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT},
 658         { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT},
 659         { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT},
 660         { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT},
 661         { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT},
 662         { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT},
 663         { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT},
 664         { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT},
 665         { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT},
 666         { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT},
 667         { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT},
 668         { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT},
 669         { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT},
 670         { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT},
 671         { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT},
 672         { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT},
 673         { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP},
 674         { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP},
 675         { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP},
 676         { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP},
 677         { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP},
 678         { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP},
 679         { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP},
 680         { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP},
 681         { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG},
 682         { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG},
 683         { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG},
 684         { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG},
 685         { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG},
 686         { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG},
 687         { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG},
 688         { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG},
 689         { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG},
 690         { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG},
 691         { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG},
 692         { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG},
 693         { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG},
 694         { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG},
 695         { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG},
 696         { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG},
 697         { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG},
 698         { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG},
 699         { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG},
 700         { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG},
 701         { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG},
 702         { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG},
 703         { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG},
 704         { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG},
 705         { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG},
 706         { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG},
 707         { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG},
 708         { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG},
 709         { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG},
 710         { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG},
 711         { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG},
 712         { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG},
 713         { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN},
 714         { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN},
 715         { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN},
 716         { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN},
 717         { 0, },                 /* End of list */
 718 };
 719 MODULE_DEVICE_TABLE(pci, lpc_ich_ids);
 720
 721 static void lpc_ich_restore_config_space(struct pci_dev *dev)
 722 {
 723         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
 724
 725         if (priv->acpi.save >= 0) {
 726                 pci_write_config_byte(dev, priv->acpi.ctrl, priv->acpi.save);
 727                 priv->acpi.save = -1;
 728         }
 729
 730         if (priv->gpio.save >= 0) {
 731                 pci_write_config_byte(dev, priv->gpio.ctrl, priv->gpio.save);
 732                 priv->gpio.save = -1;
 733         }
 734 }
 735
 736 static void lpc_ich_enable_acpi_space(struct pci_dev *dev)
 737 {
 738         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
 739         u8 reg_save;
 740
 741         pci_read_config_byte(dev, priv->acpi.ctrl, &reg_save);
 742         pci_write_config_byte(dev, priv->acpi.ctrl, reg_save | 0x10);
 743         priv->acpi.save = reg_save;
 744 }
 745
 746 static void lpc_ich_enable_gpio_space(struct pci_dev *dev)
 747 {
 748         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
 749         u8 reg_save;
 750
 751         pci_read_config_byte(dev, priv->gpio.ctrl, &reg_save);
 752         pci_write_config_byte(dev, priv->gpio.ctrl, reg_save | 0x10);
 753         priv->gpio.save = reg_save;
 754 }
 755
 756 static void lpc_ich_finalize_cell(struct pci_dev *dev, struct mfd_cell *cell)
 757 {
 758         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
 759
 760         cell->platform_data = &lpc_chipset_info[priv->chipset];
 761         cell->pdata_size = sizeof(struct lpc_ich_info);
 762 }
 763
 764 /*
 765  * We don't check for resource conflict globally. There are 2 or 3 independent
 766  * GPIO groups and it's enough to have access to one of these to instantiate
 767  * the device.
 768  */
 769 static int lpc_ich_check_conflict_gpio(struct resource *res)
 770 {
 771         int ret;
 772         u8 use_gpio = 0;
 773
 774         if (resource_size(res) >= 0x50 &&
 775             !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3"))
 776                 use_gpio |= 1 << 2;
 777
 778         if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2"))
 779                 use_gpio |= 1 << 1;
 780
 781         ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1");
 782         if (!ret)
 783                 use_gpio |= 1 << 0;
 784
 785         return use_gpio ? use_gpio : ret;
 786 }
 787
 788 static int lpc_ich_init_gpio(struct pci_dev *dev)
 789 {
 790         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
 791         u32 base_addr_cfg;
 792         u32 base_addr;
 793         int ret;
 794         bool acpi_conflict = false;
 795         struct resource *res;
 796
 797         /* Setup power management base register */
 798         pci_read_config_dword(dev, priv->acpi.base, &base_addr_cfg);
 799         base_addr = base_addr_cfg & 0x0000ff80;
 800         if (!base_addr) {
 801                 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
 802                 lpc_ich_cells[LPC_GPIO].num_resources--;
 803                 goto gpe0_done;
 804         }
 805
 806         res = &gpio_ich_res[ICH_RES_GPE0];
 807         res->start = base_addr + ACPIBASE_GPE_OFF;
 808         res->end = base_addr + ACPIBASE_GPE_END;
 809         ret = acpi_check_resource_conflict(res);
 810         if (ret) {
 811                 /*
 812                  * This isn't fatal for the GPIO, but we have to make sure that
 813                  * the platform_device subsystem doesn't see this resource
 814                  * or it will register an invalid region.
 815                  */
 816                 lpc_ich_cells[LPC_GPIO].num_resources--;
 817                 acpi_conflict = true;
 818         } else {
 819                 lpc_ich_enable_acpi_space(dev);
 820         }
 821
 822 gpe0_done:
 823         /* Setup GPIO base register */
 824         pci_read_config_dword(dev, priv->gpio.base, &base_addr_cfg);
 825         base_addr = base_addr_cfg & 0x0000ff80;
 826         if (!base_addr) {
 827                 dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n");
 828                 ret = -ENODEV;
 829                 goto gpio_done;
 830         }
 831
 832         /* Older devices provide fewer GPIO and have a smaller resource size. */
 833         res = &gpio_ich_res[ICH_RES_GPIO];
 834         res->start = base_addr;
 835         switch (lpc_chipset_info[priv->chipset].gpio_version) {
 836         case ICH_V5_GPIO:
 837         case ICH_V10CORP_GPIO:
 838                 res->end = res->start + 128 - 1;
 839                 break;
 840         default:
 841                 res->end = res->start + 64 - 1;
 842                 break;
 843         }
 844
 845         ret = lpc_ich_check_conflict_gpio(res);
 846         if (ret < 0) {
 847                 /* this isn't necessarily fatal for the GPIO */
 848                 acpi_conflict = true;
 849                 goto gpio_done;
 850         }
 851         lpc_chipset_info[priv->chipset].use_gpio = ret;
 852         lpc_ich_enable_gpio_space(dev);
 853
 854         lpc_ich_finalize_cell(dev, &lpc_ich_cells[LPC_GPIO]);
 855         ret = mfd_add_devices(&dev->dev, -1, &lpc_ich_cells[LPC_GPIO],
 856                               1, NULL, 0, NULL);
 857
 858 gpio_done:
 859         if (acpi_conflict)
 860                 pr_warn("Resource conflict(s) found affecting %s\n",
 861                                 lpc_ich_cells[LPC_GPIO].name);
 862         return ret;
 863 }
 864
 865 static int lpc_ich_init_wdt(struct pci_dev *dev)
 866 {
 867         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
 868         u32 base_addr_cfg;
 869         u32 base_addr;
 870         int ret;
 871         struct resource *res;
 872
 873         /* Setup power management base register */
 874         pci_read_config_dword(dev, priv->acpi.base, &base_addr_cfg);
 875         base_addr = base_addr_cfg & 0x0000ff80;
 876         if (!base_addr) {
 877                 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
 878                 ret = -ENODEV;
 879                 goto wdt_done;
 880         }
 881
 882         res = wdt_io_res(ICH_RES_IO_TCO);
 883         res->start = base_addr + ACPIBASE_TCO_OFF;
 884         res->end = base_addr + ACPIBASE_TCO_END;
 885
 886         res = wdt_io_res(ICH_RES_IO_SMI);
 887         res->start = base_addr + ACPIBASE_SMI_OFF;
 888         res->end = base_addr + ACPIBASE_SMI_END;
 889
 890         lpc_ich_enable_acpi_space(dev);
 891
 892         /*
 893          * Get the Memory-Mapped GCS register. To get access to it
 894          * we have to read RCBA from PCI Config space 0xf0 and use
 895          * it as base. GCS = RCBA + ICH6_GCS(0x3410).
 896          */
 897         if (lpc_chipset_info[priv->chipset].iTCO_version == 1) {
 898                 /* Don't register iomem for TCO ver 1 */
 899                 lpc_ich_cells[LPC_WDT].num_resources--;
 900         } else {
 901                 pci_read_config_dword(dev, RCBABASE, &base_addr_cfg);
 902                 base_addr = base_addr_cfg & 0xffffc000;
 903                 if (!(base_addr_cfg & 1)) {
 904                         dev_notice(&dev->dev, "RCBA is disabled by "
 905                                         "hardware/BIOS, device disabled\n");
 906                         ret = -ENODEV;
 907                         goto wdt_done;
 908                 }
 909                 res = wdt_mem_res(ICH_RES_MEM_GCS);
 910                 res->start = base_addr + ACPIBASE_GCS_OFF;
 911                 res->end = base_addr + ACPIBASE_GCS_END;
 912         }
 913
 914         lpc_ich_finalize_cell(dev, &lpc_ich_cells[LPC_WDT]);
 915         ret = mfd_add_devices(&dev->dev, -1, &lpc_ich_cells[LPC_WDT],
 916                               1, NULL, 0, NULL);
 917
 918 wdt_done:
 919         return ret;
 920 }
 921
 922 static int lpc_ich_probe(struct pci_dev *dev,
 923                                 const struct pci_device_id *id)
 924 {
 925         struct lpc_ich_priv *priv;
 926         int ret;
 927         bool cell_added = false;
 928
 929         priv = devm_kzalloc(&dev->dev,
 930                             sizeof(struct lpc_ich_priv), GFP_KERNEL);
 931         if (!priv)
 932                 return -ENOMEM;
 933
 934         priv->chipset = id->driver_data;
 935         priv->acpi.save = -1;
 936         priv->acpi.base = ACPIBASE;
 937         priv->acpi.ctrl = ACPICTRL;
 938
 939         priv->gpio.save = -1;
 940         if (priv->chipset <= LPC_ICH5) {
 941                 priv->gpio.base = GPIOBASE_ICH0;
 942                 priv->gpio.ctrl = GPIOCTRL_ICH0;
 943         } else {
 944                 priv->gpio.base = GPIOBASE_ICH6;
 945                 priv->gpio.ctrl = GPIOCTRL_ICH6;
 946         }
 947
 948         pci_set_drvdata(dev, priv);
 949
 950         ret = lpc_ich_init_wdt(dev);
 951         if (!ret)
 952                 cell_added = true;
 953
 954         ret = lpc_ich_init_gpio(dev);
 955         if (!ret)
 956                 cell_added = true;
 957
 958         /*
 959          * We only care if at least one or none of the cells registered
 960          * successfully.
 961          */
 962         if (!cell_added) {
 963                 dev_warn(&dev->dev, "No MFD cells added\n");
 964                 lpc_ich_restore_config_space(dev);
 965                 pci_set_drvdata(dev, NULL);
 966                 return -ENODEV;
 967         }
 968
 969         return 0;
 970 }
 971
 972 static void lpc_ich_remove(struct pci_dev *dev)
 973 {
 974         mfd_remove_devices(&dev->dev);
 975         lpc_ich_restore_config_space(dev);
 976         pci_set_drvdata(dev, NULL);
 977 }
 978
 979 static struct pci_driver lpc_ich_driver = {
 980         .name           = "lpc_ich",
 981         .id_table       = lpc_ich_ids,
 982         .probe          = lpc_ich_probe,
 983         .remove         = lpc_ich_remove,
 984 };
 985
 986 module_pci_driver(lpc_ich_driver);
 987
 988 MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");
 989 MODULE_DESCRIPTION("LPC interface for Intel ICH");
 990 MODULE_LICENSE("GPL");