drivers/mfd/db8500-prcmu.c

   1 /*
   2  * Copyright (C) STMicroelectronics 2009
   3  * Copyright (C) ST-Ericsson SA 2010
   4  *
   5  * License Terms: GNU General Public License v2
   6  * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
   7  * Author: Sundar Iyer <sundar.iyer@stericsson.com>
   8  * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
   9  *
  10  * U8500 PRCM Unit interface driver
  11  *
  12  */
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/delay.h>
  16 #include <linux/errno.h>
  17 #include <linux/err.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/io.h>
  20 #include <linux/slab.h>
  21 #include <linux/mutex.h>
  22 #include <linux/completion.h>
  23 #include <linux/irq.h>
  24 #include <linux/jiffies.h>
  25 #include <linux/bitops.h>
  26 #include <linux/fs.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/uaccess.h>
  29 #include <linux/mfd/core.h>
  30 #include <linux/mfd/dbx500-prcmu.h>
  31 #include <linux/mfd/abx500/ab8500.h>
  32 #include <linux/regulator/db8500-prcmu.h>
  33 #include <linux/regulator/machine.h>
  34 #include <asm/hardware/gic.h>
  35 #include <mach/hardware.h>
  36 #include <mach/irqs.h>
  37 #include <mach/db8500-regs.h>
  38 #include <mach/id.h>
  39 #include "dbx500-prcmu-regs.h"
  40
  41 /* Offset for the firmware version within the TCPM */
  42 #define PRCMU_FW_VERSION_OFFSET 0xA4
  43
  44 /* Index of different voltages to be used when accessing AVSData */
  45 #define PRCM_AVS_BASE           0x2FC
  46 #define PRCM_AVS_VBB_RET        (PRCM_AVS_BASE + 0x0)
  47 #define PRCM_AVS_VBB_MAX_OPP    (PRCM_AVS_BASE + 0x1)
  48 #define PRCM_AVS_VBB_100_OPP    (PRCM_AVS_BASE + 0x2)
  49 #define PRCM_AVS_VBB_50_OPP     (PRCM_AVS_BASE + 0x3)
  50 #define PRCM_AVS_VARM_MAX_OPP   (PRCM_AVS_BASE + 0x4)
  51 #define PRCM_AVS_VARM_100_OPP   (PRCM_AVS_BASE + 0x5)
  52 #define PRCM_AVS_VARM_50_OPP    (PRCM_AVS_BASE + 0x6)
  53 #define PRCM_AVS_VARM_RET       (PRCM_AVS_BASE + 0x7)
  54 #define PRCM_AVS_VAPE_100_OPP   (PRCM_AVS_BASE + 0x8)
  55 #define PRCM_AVS_VAPE_50_OPP    (PRCM_AVS_BASE + 0x9)
  56 #define PRCM_AVS_VMOD_100_OPP   (PRCM_AVS_BASE + 0xA)
  57 #define PRCM_AVS_VMOD_50_OPP    (PRCM_AVS_BASE + 0xB)
  58 #define PRCM_AVS_VSAFE          (PRCM_AVS_BASE + 0xC)
  59
  60 #define PRCM_AVS_VOLTAGE                0
  61 #define PRCM_AVS_VOLTAGE_MASK           0x3f
  62 #define PRCM_AVS_ISSLOWSTARTUP          6
  63 #define PRCM_AVS_ISSLOWSTARTUP_MASK     (1 << PRCM_AVS_ISSLOWSTARTUP)
  64 #define PRCM_AVS_ISMODEENABLE           7
  65 #define PRCM_AVS_ISMODEENABLE_MASK      (1 << PRCM_AVS_ISMODEENABLE)
  66
  67 #define PRCM_BOOT_STATUS        0xFFF
  68 #define PRCM_ROMCODE_A2P        0xFFE
  69 #define PRCM_ROMCODE_P2A        0xFFD
  70 #define PRCM_XP70_CUR_PWR_STATE 0xFFC      /* 4 BYTES */
  71
  72 #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
  73
  74 #define _PRCM_MBOX_HEADER               0xFE8 /* 16 bytes */
  75 #define PRCM_MBOX_HEADER_REQ_MB0        (_PRCM_MBOX_HEADER + 0x0)
  76 #define PRCM_MBOX_HEADER_REQ_MB1        (_PRCM_MBOX_HEADER + 0x1)
  77 #define PRCM_MBOX_HEADER_REQ_MB2        (_PRCM_MBOX_HEADER + 0x2)
  78 #define PRCM_MBOX_HEADER_REQ_MB3        (_PRCM_MBOX_HEADER + 0x3)
  79 #define PRCM_MBOX_HEADER_REQ_MB4        (_PRCM_MBOX_HEADER + 0x4)
  80 #define PRCM_MBOX_HEADER_REQ_MB5        (_PRCM_MBOX_HEADER + 0x5)
  81 #define PRCM_MBOX_HEADER_ACK_MB0        (_PRCM_MBOX_HEADER + 0x8)
  82
  83 /* Req Mailboxes */
  84 #define PRCM_REQ_MB0 0xFDC /* 12 bytes  */
  85 #define PRCM_REQ_MB1 0xFD0 /* 12 bytes  */
  86 #define PRCM_REQ_MB2 0xFC0 /* 16 bytes  */
  87 #define PRCM_REQ_MB3 0xE4C /* 372 bytes  */
  88 #define PRCM_REQ_MB4 0xE48 /* 4 bytes  */
  89 #define PRCM_REQ_MB5 0xE44 /* 4 bytes  */
  90
  91 /* Ack Mailboxes */
  92 #define PRCM_ACK_MB0 0xE08 /* 52 bytes  */
  93 #define PRCM_ACK_MB1 0xE04 /* 4 bytes */
  94 #define PRCM_ACK_MB2 0xE00 /* 4 bytes */
  95 #define PRCM_ACK_MB3 0xDFC /* 4 bytes */
  96 #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
  97 #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
  98
  99 /* Mailbox 0 headers */
 100 #define MB0H_POWER_STATE_TRANS          0
 101 #define MB0H_CONFIG_WAKEUPS_EXE         1
 102 #define MB0H_READ_WAKEUP_ACK            3
 103 #define MB0H_CONFIG_WAKEUPS_SLEEP       4
 104
 105 #define MB0H_WAKEUP_EXE 2
 106 #define MB0H_WAKEUP_SLEEP 5
 107
 108 /* Mailbox 0 REQs */
 109 #define PRCM_REQ_MB0_AP_POWER_STATE     (PRCM_REQ_MB0 + 0x0)
 110 #define PRCM_REQ_MB0_AP_PLL_STATE       (PRCM_REQ_MB0 + 0x1)
 111 #define PRCM_REQ_MB0_ULP_CLOCK_STATE    (PRCM_REQ_MB0 + 0x2)
 112 #define PRCM_REQ_MB0_DO_NOT_WFI         (PRCM_REQ_MB0 + 0x3)
 113 #define PRCM_REQ_MB0_WAKEUP_8500        (PRCM_REQ_MB0 + 0x4)
 114 #define PRCM_REQ_MB0_WAKEUP_4500        (PRCM_REQ_MB0 + 0x8)
 115
 116 /* Mailbox 0 ACKs */
 117 #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS  (PRCM_ACK_MB0 + 0x0)
 118 #define PRCM_ACK_MB0_READ_POINTER       (PRCM_ACK_MB0 + 0x1)
 119 #define PRCM_ACK_MB0_WAKEUP_0_8500      (PRCM_ACK_MB0 + 0x4)
 120 #define PRCM_ACK_MB0_WAKEUP_0_4500      (PRCM_ACK_MB0 + 0x8)
 121 #define PRCM_ACK_MB0_WAKEUP_1_8500      (PRCM_ACK_MB0 + 0x1C)
 122 #define PRCM_ACK_MB0_WAKEUP_1_4500      (PRCM_ACK_MB0 + 0x20)
 123 #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
 124
 125 /* Mailbox 1 headers */
 126 #define MB1H_ARM_APE_OPP 0x0
 127 #define MB1H_RESET_MODEM 0x2
 128 #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
 129 #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
 130 #define MB1H_RELEASE_USB_WAKEUP 0x5
 131 #define MB1H_PLL_ON_OFF 0x6
 132
 133 /* Mailbox 1 Requests */
 134 #define PRCM_REQ_MB1_ARM_OPP                    (PRCM_REQ_MB1 + 0x0)
 135 #define PRCM_REQ_MB1_APE_OPP                    (PRCM_REQ_MB1 + 0x1)
 136 #define PRCM_REQ_MB1_PLL_ON_OFF                 (PRCM_REQ_MB1 + 0x4)
 137 #define PLL_SOC0_OFF    0x1
 138 #define PLL_SOC0_ON     0x2
 139 #define PLL_SOC1_OFF    0x4
 140 #define PLL_SOC1_ON     0x8
 141
 142 /* Mailbox 1 ACKs */
 143 #define PRCM_ACK_MB1_CURRENT_ARM_OPP    (PRCM_ACK_MB1 + 0x0)
 144 #define PRCM_ACK_MB1_CURRENT_APE_OPP    (PRCM_ACK_MB1 + 0x1)
 145 #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
 146 #define PRCM_ACK_MB1_DVFS_STATUS        (PRCM_ACK_MB1 + 0x3)
 147
 148 /* Mailbox 2 headers */
 149 #define MB2H_DPS        0x0
 150 #define MB2H_AUTO_PWR   0x1
 151
 152 /* Mailbox 2 REQs */
 153 #define PRCM_REQ_MB2_SVA_MMDSP          (PRCM_REQ_MB2 + 0x0)
 154 #define PRCM_REQ_MB2_SVA_PIPE           (PRCM_REQ_MB2 + 0x1)
 155 #define PRCM_REQ_MB2_SIA_MMDSP          (PRCM_REQ_MB2 + 0x2)
 156 #define PRCM_REQ_MB2_SIA_PIPE           (PRCM_REQ_MB2 + 0x3)
 157 #define PRCM_REQ_MB2_SGA                (PRCM_REQ_MB2 + 0x4)
 158 #define PRCM_REQ_MB2_B2R2_MCDE          (PRCM_REQ_MB2 + 0x5)
 159 #define PRCM_REQ_MB2_ESRAM12            (PRCM_REQ_MB2 + 0x6)
 160 #define PRCM_REQ_MB2_ESRAM34            (PRCM_REQ_MB2 + 0x7)
 161 #define PRCM_REQ_MB2_AUTO_PM_SLEEP      (PRCM_REQ_MB2 + 0x8)
 162 #define PRCM_REQ_MB2_AUTO_PM_IDLE       (PRCM_REQ_MB2 + 0xC)
 163
 164 /* Mailbox 2 ACKs */
 165 #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
 166 #define HWACC_PWR_ST_OK 0xFE
 167
 168 /* Mailbox 3 headers */
 169 #define MB3H_ANC        0x0
 170 #define MB3H_SIDETONE   0x1
 171 #define MB3H_SYSCLK     0xE
 172
 173 /* Mailbox 3 Requests */
 174 #define PRCM_REQ_MB3_ANC_FIR_COEFF      (PRCM_REQ_MB3 + 0x0)
 175 #define PRCM_REQ_MB3_ANC_IIR_COEFF      (PRCM_REQ_MB3 + 0x20)
 176 #define PRCM_REQ_MB3_ANC_SHIFTER        (PRCM_REQ_MB3 + 0x60)
 177 #define PRCM_REQ_MB3_ANC_WARP           (PRCM_REQ_MB3 + 0x64)
 178 #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN  (PRCM_REQ_MB3 + 0x68)
 179 #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
 180 #define PRCM_REQ_MB3_SYSCLK_MGT         (PRCM_REQ_MB3 + 0x16C)
 181
 182 /* Mailbox 4 headers */
 183 #define MB4H_DDR_INIT   0x0
 184 #define MB4H_MEM_ST     0x1
 185 #define MB4H_HOTDOG     0x12
 186 #define MB4H_HOTMON     0x13
 187 #define MB4H_HOT_PERIOD 0x14
 188 #define MB4H_A9WDOG_CONF 0x16
 189 #define MB4H_A9WDOG_EN   0x17
 190 #define MB4H_A9WDOG_DIS  0x18
 191 #define MB4H_A9WDOG_LOAD 0x19
 192 #define MB4H_A9WDOG_KICK 0x20
 193
 194 /* Mailbox 4 Requests */
 195 #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE       (PRCM_REQ_MB4 + 0x0)
 196 #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE        (PRCM_REQ_MB4 + 0x1)
 197 #define PRCM_REQ_MB4_ESRAM0_ST                  (PRCM_REQ_MB4 + 0x3)
 198 #define PRCM_REQ_MB4_HOTDOG_THRESHOLD           (PRCM_REQ_MB4 + 0x0)
 199 #define PRCM_REQ_MB4_HOTMON_LOW                 (PRCM_REQ_MB4 + 0x0)
 200 #define PRCM_REQ_MB4_HOTMON_HIGH                (PRCM_REQ_MB4 + 0x1)
 201 #define PRCM_REQ_MB4_HOTMON_CONFIG              (PRCM_REQ_MB4 + 0x2)
 202 #define PRCM_REQ_MB4_HOT_PERIOD                 (PRCM_REQ_MB4 + 0x0)
 203 #define HOTMON_CONFIG_LOW                       BIT(0)
 204 #define HOTMON_CONFIG_HIGH                      BIT(1)
 205 #define PRCM_REQ_MB4_A9WDOG_0                   (PRCM_REQ_MB4 + 0x0)
 206 #define PRCM_REQ_MB4_A9WDOG_1                   (PRCM_REQ_MB4 + 0x1)
 207 #define PRCM_REQ_MB4_A9WDOG_2                   (PRCM_REQ_MB4 + 0x2)
 208 #define PRCM_REQ_MB4_A9WDOG_3                   (PRCM_REQ_MB4 + 0x3)
 209 #define A9WDOG_AUTO_OFF_EN                      BIT(7)
 210 #define A9WDOG_AUTO_OFF_DIS                     0
 211 #define A9WDOG_ID_MASK                          0xf
 212
 213 /* Mailbox 5 Requests */
 214 #define PRCM_REQ_MB5_I2C_SLAVE_OP       (PRCM_REQ_MB5 + 0x0)
 215 #define PRCM_REQ_MB5_I2C_HW_BITS        (PRCM_REQ_MB5 + 0x1)
 216 #define PRCM_REQ_MB5_I2C_REG            (PRCM_REQ_MB5 + 0x2)
 217 #define PRCM_REQ_MB5_I2C_VAL            (PRCM_REQ_MB5 + 0x3)
 218 #define PRCMU_I2C_WRITE(slave) \
 219         (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0))
 220 #define PRCMU_I2C_READ(slave) \
 221         (((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0))
 222 #define PRCMU_I2C_STOP_EN               BIT(3)
 223
 224 /* Mailbox 5 ACKs */
 225 #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
 226 #define PRCM_ACK_MB5_I2C_VAL    (PRCM_ACK_MB5 + 0x3)
 227 #define I2C_WR_OK 0x1
 228 #define I2C_RD_OK 0x2
 229
 230 #define NUM_MB 8
 231 #define MBOX_BIT BIT
 232 #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
 233
 234 /*
 235  * Wakeups/IRQs
 236  */
 237
 238 #define WAKEUP_BIT_RTC BIT(0)
 239 #define WAKEUP_BIT_RTT0 BIT(1)
 240 #define WAKEUP_BIT_RTT1 BIT(2)
 241 #define WAKEUP_BIT_HSI0 BIT(3)
 242 #define WAKEUP_BIT_HSI1 BIT(4)
 243 #define WAKEUP_BIT_CA_WAKE BIT(5)
 244 #define WAKEUP_BIT_USB BIT(6)
 245 #define WAKEUP_BIT_ABB BIT(7)
 246 #define WAKEUP_BIT_ABB_FIFO BIT(8)
 247 #define WAKEUP_BIT_SYSCLK_OK BIT(9)
 248 #define WAKEUP_BIT_CA_SLEEP BIT(10)
 249 #define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
 250 #define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
 251 #define WAKEUP_BIT_ANC_OK BIT(13)
 252 #define WAKEUP_BIT_SW_ERROR BIT(14)
 253 #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
 254 #define WAKEUP_BIT_ARM BIT(17)
 255 #define WAKEUP_BIT_HOTMON_LOW BIT(18)
 256 #define WAKEUP_BIT_HOTMON_HIGH BIT(19)
 257 #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
 258 #define WAKEUP_BIT_GPIO0 BIT(23)
 259 #define WAKEUP_BIT_GPIO1 BIT(24)
 260 #define WAKEUP_BIT_GPIO2 BIT(25)
 261 #define WAKEUP_BIT_GPIO3 BIT(26)
 262 #define WAKEUP_BIT_GPIO4 BIT(27)
 263 #define WAKEUP_BIT_GPIO5 BIT(28)
 264 #define WAKEUP_BIT_GPIO6 BIT(29)
 265 #define WAKEUP_BIT_GPIO7 BIT(30)
 266 #define WAKEUP_BIT_GPIO8 BIT(31)
 267
 268 static struct {
 269         bool valid;
 270         struct prcmu_fw_version version;
 271 } fw_info;
 272
 273 /*
 274  * This vector maps irq numbers to the bits in the bit field used in
 275  * communication with the PRCMU firmware.
 276  *
 277  * The reason for having this is to keep the irq numbers contiguous even though
 278  * the bits in the bit field are not. (The bits also have a tendency to move
 279  * around, to further complicate matters.)
 280  */
 281 #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE)
 282 #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
 283 static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
 284         IRQ_ENTRY(RTC),
 285         IRQ_ENTRY(RTT0),
 286         IRQ_ENTRY(RTT1),
 287         IRQ_ENTRY(HSI0),
 288         IRQ_ENTRY(HSI1),
 289         IRQ_ENTRY(CA_WAKE),
 290         IRQ_ENTRY(USB),
 291         IRQ_ENTRY(ABB),
 292         IRQ_ENTRY(ABB_FIFO),
 293         IRQ_ENTRY(CA_SLEEP),
 294         IRQ_ENTRY(ARM),
 295         IRQ_ENTRY(HOTMON_LOW),
 296         IRQ_ENTRY(HOTMON_HIGH),
 297         IRQ_ENTRY(MODEM_SW_RESET_REQ),
 298         IRQ_ENTRY(GPIO0),
 299         IRQ_ENTRY(GPIO1),
 300         IRQ_ENTRY(GPIO2),
 301         IRQ_ENTRY(GPIO3),
 302         IRQ_ENTRY(GPIO4),
 303         IRQ_ENTRY(GPIO5),
 304         IRQ_ENTRY(GPIO6),
 305         IRQ_ENTRY(GPIO7),
 306         IRQ_ENTRY(GPIO8)
 307 };
 308
 309 #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
 310 #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
 311 static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
 312         WAKEUP_ENTRY(RTC),
 313         WAKEUP_ENTRY(RTT0),
 314         WAKEUP_ENTRY(RTT1),
 315         WAKEUP_ENTRY(HSI0),
 316         WAKEUP_ENTRY(HSI1),
 317         WAKEUP_ENTRY(USB),
 318         WAKEUP_ENTRY(ABB),
 319         WAKEUP_ENTRY(ABB_FIFO),
 320         WAKEUP_ENTRY(ARM)
 321 };
 322
 323 /*
 324  * mb0_transfer - state needed for mailbox 0 communication.
 325  * @lock:               The transaction lock.
 326  * @dbb_events_lock:    A lock used to handle concurrent access to (parts of)
 327  *                      the request data.
 328  * @mask_work:          Work structure used for (un)masking wakeup interrupts.
 329  * @req:                Request data that need to persist between requests.
 330  */
 331 static struct {
 332         spinlock_t lock;
 333         spinlock_t dbb_irqs_lock;
 334         struct work_struct mask_work;
 335         struct mutex ac_wake_lock;
 336         struct completion ac_wake_work;
 337         struct {
 338                 u32 dbb_irqs;
 339                 u32 dbb_wakeups;
 340                 u32 abb_events;
 341         } req;
 342 } mb0_transfer;
 343
 344 /*
 345  * mb1_transfer - state needed for mailbox 1 communication.
 346  * @lock:       The transaction lock.
 347  * @work:       The transaction completion structure.
 348  * @ape_opp:    The current APE OPP.
 349  * @ack:        Reply ("acknowledge") data.
 350  */
 351 static struct {
 352         struct mutex lock;
 353         struct completion work;
 354         u8 ape_opp;
 355         struct {
 356                 u8 header;
 357                 u8 arm_opp;
 358                 u8 ape_opp;
 359                 u8 ape_voltage_status;
 360         } ack;
 361 } mb1_transfer;
 362
 363 /*
 364  * mb2_transfer - state needed for mailbox 2 communication.
 365  * @lock:            The transaction lock.
 366  * @work:            The transaction completion structure.
 367  * @auto_pm_lock:    The autonomous power management configuration lock.
 368  * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
 369  * @req:             Request data that need to persist between requests.
 370  * @ack:             Reply ("acknowledge") data.
 371  */
 372 static struct {
 373         struct mutex lock;
 374         struct completion work;
 375         spinlock_t auto_pm_lock;
 376         bool auto_pm_enabled;
 377         struct {
 378                 u8 status;
 379         } ack;
 380 } mb2_transfer;
 381
 382 /*
 383  * mb3_transfer - state needed for mailbox 3 communication.
 384  * @lock:               The request lock.
 385  * @sysclk_lock:        A lock used to handle concurrent sysclk requests.
 386  * @sysclk_work:        Work structure used for sysclk requests.
 387  */
 388 static struct {
 389         spinlock_t lock;
 390         struct mutex sysclk_lock;
 391         struct completion sysclk_work;
 392 } mb3_transfer;
 393
 394 /*
 395  * mb4_transfer - state needed for mailbox 4 communication.
 396  * @lock:       The transaction lock.
 397  * @work:       The transaction completion structure.
 398  */
 399 static struct {
 400         struct mutex lock;
 401         struct completion work;
 402 } mb4_transfer;
 403
 404 /*
 405  * mb5_transfer - state needed for mailbox 5 communication.
 406  * @lock:       The transaction lock.
 407  * @work:       The transaction completion structure.
 408  * @ack:        Reply ("acknowledge") data.
 409  */
 410 static struct {
 411         struct mutex lock;
 412         struct completion work;
 413         struct {
 414                 u8 status;
 415                 u8 value;
 416         } ack;
 417 } mb5_transfer;
 418
 419 static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
 420
 421 /* Spinlocks */
 422 static DEFINE_SPINLOCK(prcmu_lock);
 423 static DEFINE_SPINLOCK(clkout_lock);
 424
 425 /* Global var to runtime determine TCDM base for v2 or v1 */
 426 static __iomem void *tcdm_base;
 427
 428 struct clk_mgt {
 429         void __iomem *reg;
 430         u32 pllsw;
 431         int branch;
 432         bool clk38div;
 433 };
 434
 435 enum {
 436         PLL_RAW,
 437         PLL_FIX,
 438         PLL_DIV
 439 };
 440
 441 static DEFINE_SPINLOCK(clk_mgt_lock);
 442
 443 #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
 444         { (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
 445 struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
 446         CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
 447         CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true),
 448         CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true),
 449         CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true),
 450         CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true),
 451         CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
 452         CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true),
 453         CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
 454         CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
 455         CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
 456         CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
 457         CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
 458         CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
 459         CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
 460         CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
 461         CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
 462         CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
 463         CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false),
 464         CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true),
 465         CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true),
 466         CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
 467         CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true),
 468         CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false),
 469         CLK_MGT_ENTRY(DMACLK, PLL_DIV, true),
 470         CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true),
 471         CLK_MGT_ENTRY(TVCLK, PLL_FIX, true),
 472         CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true),
 473         CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true),
 474         CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false),
 475 };
 476
 477 struct dsiclk {
 478         u32 divsel_mask;
 479         u32 divsel_shift;
 480         u32 divsel;
 481 };
 482
 483 static struct dsiclk dsiclk[2] = {
 484         {
 485                 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK,
 486                 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT,
 487                 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
 488         },
 489         {
 490                 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK,
 491                 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT,
 492                 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
 493         }
 494 };
 495
 496 struct dsiescclk {
 497         u32 en;
 498         u32 div_mask;
 499         u32 div_shift;
 500 };
 501
 502 static struct dsiescclk dsiescclk[3] = {
 503         {
 504                 .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN,
 505                 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
 506                 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
 507         },
 508         {
 509                 .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN,
 510                 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
 511                 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
 512         },
 513         {
 514                 .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN,
 515                 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
 516                 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
 517         }
 518 };
 519
 520 /*
 521 * Used by MCDE to setup all necessary PRCMU registers
 522 */
 523 #define PRCMU_RESET_DSIPLL              0x00004000
 524 #define PRCMU_UNCLAMP_DSIPLL            0x00400800
 525
 526 #define PRCMU_CLK_PLL_DIV_SHIFT         0
 527 #define PRCMU_CLK_PLL_SW_SHIFT          5
 528 #define PRCMU_CLK_38                    (1 << 9)
 529 #define PRCMU_CLK_38_SRC                (1 << 10)
 530 #define PRCMU_CLK_38_DIV                (1 << 11)
 531
 532 /* PLLDIV=12, PLLSW=4 (PLLDDR) */
 533 #define PRCMU_DSI_CLOCK_SETTING         0x0000008C
 534
 535 /* DPI 50000000 Hz */
 536 #define PRCMU_DPI_CLOCK_SETTING         ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
 537                                           (16 << PRCMU_CLK_PLL_DIV_SHIFT))
 538 #define PRCMU_DSI_LP_CLOCK_SETTING      0x00000E00
 539
 540 /* D=101, N=1, R=4, SELDIV2=0 */
 541 #define PRCMU_PLLDSI_FREQ_SETTING       0x00040165
 542
 543 #define PRCMU_ENABLE_PLLDSI             0x00000001
 544 #define PRCMU_DISABLE_PLLDSI            0x00000000
 545 #define PRCMU_RELEASE_RESET_DSS         0x0000400C
 546 #define PRCMU_DSI_PLLOUT_SEL_SETTING    0x00000202
 547 /* ESC clk, div0=1, div1=1, div2=3 */
 548 #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV   0x07030101
 549 #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV  0x00030101
 550 #define PRCMU_DSI_RESET_SW              0x00000007
 551
 552 #define PRCMU_PLLDSI_LOCKP_LOCKED       0x3
 553
 554 int db8500_prcmu_enable_dsipll(void)
 555 {
 556         int i;
 557
 558         /* Clear DSIPLL_RESETN */
 559         writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
 560         /* Unclamp DSIPLL in/out */
 561         writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
 562
 563         /* Set DSI PLL FREQ */
 564         writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
 565         writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL);
 566         /* Enable Escape clocks */
 567         writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
 568
 569         /* Start DSI PLL */
 570         writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
 571         /* Reset DSI PLL */
 572         writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
 573         for (i = 0; i < 10; i++) {
 574                 if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED)
 575                                         == PRCMU_PLLDSI_LOCKP_LOCKED)
 576                         break;
 577                 udelay(100);
 578         }
 579         /* Set DSIPLL_RESETN */
 580         writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
 581         return 0;
 582 }
 583
 584 int db8500_prcmu_disable_dsipll(void)
 585 {
 586         /* Disable dsi pll */
 587         writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
 588         /* Disable  escapeclock */
 589         writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
 590         return 0;
 591 }
 592
 593 int db8500_prcmu_set_display_clocks(void)
 594 {
 595         unsigned long flags;
 596
 597         spin_lock_irqsave(&clk_mgt_lock, flags);
 598
 599         /* Grab the HW semaphore. */
 600         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
 601                 cpu_relax();
 602
 603         writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT);
 604         writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT);
 605         writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT);
 606
 607         /* Release the HW semaphore. */
 608         writel(0, PRCM_SEM);
 609
 610         spin_unlock_irqrestore(&clk_mgt_lock, flags);
 611
 612         return 0;
 613 }
 614
 615 u32 db8500_prcmu_read(unsigned int reg)
 616 {
 617         return readl(_PRCMU_BASE + reg);
 618 }
 619
 620 void db8500_prcmu_write(unsigned int reg, u32 value)
 621 {
 622         unsigned long flags;
 623
 624         spin_lock_irqsave(&prcmu_lock, flags);
 625         writel(value, (_PRCMU_BASE + reg));
 626         spin_unlock_irqrestore(&prcmu_lock, flags);
 627 }
 628
 629 void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
 630 {
 631         u32 val;
 632         unsigned long flags;
 633
 634         spin_lock_irqsave(&prcmu_lock, flags);
 635         val = readl(_PRCMU_BASE + reg);
 636         val = ((val & ~mask) | (value & mask));
 637         writel(val, (_PRCMU_BASE + reg));
 638         spin_unlock_irqrestore(&prcmu_lock, flags);
 639 }
 640
 641 struct prcmu_fw_version *prcmu_get_fw_version(void)
 642 {
 643         return fw_info.valid ? &fw_info.version : NULL;
 644 }
 645
 646 bool prcmu_has_arm_maxopp(void)
 647 {
 648         return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
 649                 PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
 650 }
 651
 652 /**
 653  * prcmu_get_boot_status - PRCMU boot status checking
 654  * Returns: the current PRCMU boot status
 655  */
 656 int prcmu_get_boot_status(void)
 657 {
 658         return readb(tcdm_base + PRCM_BOOT_STATUS);
 659 }
 660
 661 /**
 662  * prcmu_set_rc_a2p - This function is used to run few power state sequences
 663  * @val: Value to be set, i.e. transition requested
 664  * Returns: 0 on success, -EINVAL on invalid argument
 665  *
 666  * This function is used to run the following power state sequences -
 667  * any state to ApReset,  ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
 668  */
 669 int prcmu_set_rc_a2p(enum romcode_write val)
 670 {
 671         if (val < RDY_2_DS || val > RDY_2_XP70_RST)
 672                 return -EINVAL;
 673         writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
 674         return 0;
 675 }
 676
 677 /**
 678  * prcmu_get_rc_p2a - This function is used to get power state sequences
 679  * Returns: the power transition that has last happened
 680  *
 681  * This function can return the following transitions-
 682  * any state to ApReset,  ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
 683  */
 684 enum romcode_read prcmu_get_rc_p2a(void)
 685 {
 686         return readb(tcdm_base + PRCM_ROMCODE_P2A);
 687 }
 688
 689 /**
 690  * prcmu_get_current_mode - Return the current XP70 power mode
 691  * Returns: Returns the current AP(ARM) power mode: init,
 692  * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
 693  */
 694 enum ap_pwrst prcmu_get_xp70_current_state(void)
 695 {
 696         return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
 697 }
 698
 699 /**
 700  * prcmu_config_clkout - Configure one of the programmable clock outputs.
 701  * @clkout:     The CLKOUT number (0 or 1).
 702  * @source:     The clock to be used (one of the PRCMU_CLKSRC_*).
 703  * @div:        The divider to be applied.
 704  *
 705  * Configures one of the programmable clock outputs (CLKOUTs).
 706  * @div should be in the range [1,63] to request a configuration, or 0 to
 707  * inform that the configuration is no longer requested.
 708  */
 709 int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
 710 {
 711         static int requests[2];
 712         int r = 0;
 713         unsigned long flags;
 714         u32 val;
 715         u32 bits;
 716         u32 mask;
 717         u32 div_mask;
 718
 719         BUG_ON(clkout > 1);
 720         BUG_ON(div > 63);
 721         BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
 722
 723         if (!div && !requests[clkout])
 724                 return -EINVAL;
 725
 726         switch (clkout) {
 727         case 0:
 728                 div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
 729                 mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
 730                 bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
 731                         (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
 732                 break;
 733         case 1:
 734                 div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
 735                 mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
 736                         PRCM_CLKOCR_CLK1TYPE);
 737                 bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
 738                         (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
 739                 break;
 740         }
 741         bits &= mask;
 742
 743         spin_lock_irqsave(&clkout_lock, flags);
 744
 745         val = readl(PRCM_CLKOCR);
 746         if (val & div_mask) {
 747                 if (div) {
 748                         if ((val & mask) != bits) {
 749                                 r = -EBUSY;
 750                                 goto unlock_and_return;
 751                         }
 752                 } else {
 753                         if ((val & mask & ~div_mask) != bits) {
 754                                 r = -EINVAL;
 755                                 goto unlock_and_return;
 756                         }
 757                 }
 758         }
 759         writel((bits | (val & ~mask)), PRCM_CLKOCR);
 760         requests[clkout] += (div ? 1 : -1);
 761
 762 unlock_and_return:
 763         spin_unlock_irqrestore(&clkout_lock, flags);
 764
 765         return r;
 766 }
 767
 768 int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
 769 {
 770         unsigned long flags;
 771
 772         BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
 773
 774         spin_lock_irqsave(&mb0_transfer.lock, flags);
 775
 776         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
 777                 cpu_relax();
 778
 779         writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
 780         writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
 781         writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
 782         writeb((keep_ulp_clk ? 1 : 0),
 783                 (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
 784         writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
 785         writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
 786
 787         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
 788
 789         return 0;
 790 }
 791
 792 u8 db8500_prcmu_get_power_state_result(void)
 793 {
 794         return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
 795 }
 796
 797 /* This function decouple the gic from the prcmu */
 798 int db8500_prcmu_gic_decouple(void)
 799 {
 800         u32 val = readl(PRCM_A9_MASK_REQ);
 801
 802         /* Set bit 0 register value to 1 */
 803         writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ,
 804                PRCM_A9_MASK_REQ);
 805
 806         /* Make sure the register is updated */
 807         readl(PRCM_A9_MASK_REQ);
 808
 809         /* Wait a few cycles for the gic mask completion */
 810         udelay(1);
 811
 812         return 0;
 813 }
 814
 815 /* This function recouple the gic with the prcmu */
 816 int db8500_prcmu_gic_recouple(void)
 817 {
 818         u32 val = readl(PRCM_A9_MASK_REQ);
 819
 820         /* Set bit 0 register value to 0 */
 821         writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ);
 822
 823         return 0;
 824 }
 825
 826 #define PRCMU_GIC_NUMBER_REGS 5
 827
 828 /*
 829  * This function checks if there are pending irq on the gic. It only
 830  * makes sense if the gic has been decoupled before with the
 831  * db8500_prcmu_gic_decouple function. Disabling an interrupt only
 832  * disables the forwarding of the interrupt to any CPU interface. It
 833  * does not prevent the interrupt from changing state, for example
 834  * becoming pending, or active and pending if it is already
 835  * active. Hence, we have to check the interrupt is pending *and* is
 836  * active.
 837  */
 838 bool db8500_prcmu_gic_pending_irq(void)
 839 {
 840         u32 pr; /* Pending register */
 841         u32 er; /* Enable register */
 842         void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
 843         int i;
 844
 845         /* 5 registers. STI & PPI not skipped */
 846         for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) {
 847
 848                 pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4);
 849                 er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
 850
 851                 if (pr & er)
 852                         return true; /* There is a pending interrupt */
 853         }
 854
 855         return false;
 856 }
 857
 858 /*
 859  * This function checks if there are pending interrupt on the
 860  * prcmu which has been delegated to monitor the irqs with the
 861  * db8500_prcmu_copy_gic_settings function.
 862  */
 863 bool db8500_prcmu_pending_irq(void)
 864 {
 865         u32 it, im;
 866         int i;
 867
 868         for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
 869                 it = readl(PRCM_ARMITVAL31TO0 + i * 4);
 870                 im = readl(PRCM_ARMITMSK31TO0 + i * 4);
 871                 if (it & im)
 872                         return true; /* There is a pending interrupt */
 873         }
 874
 875         return false;
 876 }
 877
 878 /*
 879  * This function checks if the specified cpu is in in WFI. It's usage
 880  * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
 881  * function. Of course passing smp_processor_id() to this function will
 882  * always return false...
 883  */
 884 bool db8500_prcmu_is_cpu_in_wfi(int cpu)
 885 {
 886         return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 :
 887                      PRCM_ARM_WFI_STANDBY_WFI0;
 888 }
 889
 890 /*
 891  * This function copies the gic SPI settings to the prcmu in order to
 892  * monitor them and abort/finish the retention/off sequence or state.
 893  */
 894 int db8500_prcmu_copy_gic_settings(void)
 895 {
 896         u32 er; /* Enable register */
 897         void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
 898         int i;
 899
 900         /* We skip the STI and PPI */
 901         for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
 902                 er = readl_relaxed(dist_base +
 903                                    GIC_DIST_ENABLE_SET + (i + 1) * 4);
 904                 writel(er, PRCM_ARMITMSK31TO0 + i * 4);
 905         }
 906
 907         return 0;
 908 }
 909
 910 /* This function should only be called while mb0_transfer.lock is held. */
 911 static void config_wakeups(void)
 912 {
 913         const u8 header[2] = {
 914                 MB0H_CONFIG_WAKEUPS_EXE,
 915                 MB0H_CONFIG_WAKEUPS_SLEEP
 916         };
 917         static u32 last_dbb_events;
 918         static u32 last_abb_events;
 919         u32 dbb_events;
 920         u32 abb_events;
 921         unsigned int i;
 922
 923         dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
 924         dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
 925
 926         abb_events = mb0_transfer.req.abb_events;
 927
 928         if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
 929                 return;
 930
 931         for (i = 0; i < 2; i++) {
 932                 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
 933                         cpu_relax();
 934                 writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
 935                 writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
 936                 writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
 937                 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
 938         }
 939         last_dbb_events = dbb_events;
 940         last_abb_events = abb_events;
 941 }
 942
 943 void db8500_prcmu_enable_wakeups(u32 wakeups)
 944 {
 945         unsigned long flags;
 946         u32 bits;
 947         int i;
 948
 949         BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
 950
 951         for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
 952                 if (wakeups & BIT(i))
 953                         bits |= prcmu_wakeup_bit[i];
 954         }
 955
 956         spin_lock_irqsave(&mb0_transfer.lock, flags);
 957
 958         mb0_transfer.req.dbb_wakeups = bits;
 959         config_wakeups();
 960
 961         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
 962 }
 963
 964 void db8500_prcmu_config_abb_event_readout(u32 abb_events)
 965 {
 966         unsigned long flags;
 967
 968         spin_lock_irqsave(&mb0_transfer.lock, flags);
 969
 970         mb0_transfer.req.abb_events = abb_events;
 971         config_wakeups();
 972
 973         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
 974 }
 975
 976 void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
 977 {
 978         if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
 979                 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
 980         else
 981                 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
 982 }
 983
 984 /**
 985  * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
 986  * @opp: The new ARM operating point to which transition is to be made
 987  * Returns: 0 on success, non-zero on failure
 988  *
 989  * This function sets the the operating point of the ARM.
 990  */
 991 int db8500_prcmu_set_arm_opp(u8 opp)
 992 {
 993         int r;
 994
 995         if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
 996                 return -EINVAL;
 997
 998         r = 0;
 999
1000         mutex_lock(&mb1_transfer.lock);
1001
1002         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1003                 cpu_relax();
1004
1005         writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1006         writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
1007         writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
1008
1009         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1010         wait_for_completion(&mb1_transfer.work);
1011
1012         if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1013                 (mb1_transfer.ack.arm_opp != opp))
1014                 r = -EIO;
1015
1016         mutex_unlock(&mb1_transfer.lock);
1017
1018         return r;
1019 }
1020
1021 /**
1022  * db8500_prcmu_get_arm_opp - get the current ARM OPP
1023  *
1024  * Returns: the current ARM OPP
1025  */
1026 int db8500_prcmu_get_arm_opp(void)
1027 {
1028         return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
1029 }
1030
1031 /**
1032  * db8500_prcmu_get_ddr_opp - get the current DDR OPP
1033  *
1034  * Returns: the current DDR OPP
1035  */
1036 int db8500_prcmu_get_ddr_opp(void)
1037 {
1038         return readb(PRCM_DDR_SUBSYS_APE_MINBW);
1039 }
1040
1041 /**
1042  * db8500_set_ddr_opp - set the appropriate DDR OPP
1043  * @opp: The new DDR operating point to which transition is to be made
1044  * Returns: 0 on success, non-zero on failure
1045  *
1046  * This function sets the operating point of the DDR.
1047  */
1048 int db8500_prcmu_set_ddr_opp(u8 opp)
1049 {
1050         if (opp < DDR_100_OPP || opp > DDR_25_OPP)
1051                 return -EINVAL;
1052         /* Changing the DDR OPP can hang the hardware pre-v21 */
1053         if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20())
1054                 writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW);
1055
1056         return 0;
1057 }
1058
1059 /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
1060 static void request_even_slower_clocks(bool enable)
1061 {
1062         void __iomem *clock_reg[] = {
1063                 PRCM_ACLK_MGT,
1064                 PRCM_DMACLK_MGT
1065         };
1066         unsigned long flags;
1067         unsigned int i;
1068
1069         spin_lock_irqsave(&clk_mgt_lock, flags);
1070
1071         /* Grab the HW semaphore. */
1072         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1073                 cpu_relax();
1074
1075         for (i = 0; i < ARRAY_SIZE(clock_reg); i++) {
1076                 u32 val;
1077                 u32 div;
1078
1079                 val = readl(clock_reg[i]);
1080                 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
1081                 if (enable) {
1082                         if ((div <= 1) || (div > 15)) {
1083                                 pr_err("prcmu: Bad clock divider %d in %s\n",
1084                                         div, __func__);
1085                                 goto unlock_and_return;
1086                         }
1087                         div <<= 1;
1088                 } else {
1089                         if (div <= 2)
1090                                 goto unlock_and_return;
1091                         div >>= 1;
1092                 }
1093                 val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
1094                         (div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
1095                 writel(val, clock_reg[i]);
1096         }
1097
1098 unlock_and_return:
1099         /* Release the HW semaphore. */
1100         writel(0, PRCM_SEM);
1101
1102         spin_unlock_irqrestore(&clk_mgt_lock, flags);
1103 }
1104
1105 /**
1106  * db8500_set_ape_opp - set the appropriate APE OPP
1107  * @opp: The new APE operating point to which transition is to be made
1108  * Returns: 0 on success, non-zero on failure
1109  *
1110  * This function sets the operating point of the APE.
1111  */
1112 int db8500_prcmu_set_ape_opp(u8 opp)
1113 {
1114         int r = 0;
1115
1116         if (opp == mb1_transfer.ape_opp)
1117                 return 0;
1118
1119         mutex_lock(&mb1_transfer.lock);
1120
1121         if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)
1122                 request_even_slower_clocks(false);
1123
1124         if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP))
1125                 goto skip_message;
1126
1127         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1128                 cpu_relax();
1129
1130         writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1131         writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
1132         writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),
1133                 (tcdm_base + PRCM_REQ_MB1_APE_OPP));
1134
1135         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1136         wait_for_completion(&mb1_transfer.work);
1137
1138         if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1139                 (mb1_transfer.ack.ape_opp != opp))
1140                 r = -EIO;
1141
1142 skip_message:
1143         if ((!r && (opp == APE_50_PARTLY_25_OPP)) ||
1144                 (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)))
1145                 request_even_slower_clocks(true);
1146         if (!r)
1147                 mb1_transfer.ape_opp = opp;
1148
1149         mutex_unlock(&mb1_transfer.lock);
1150
1151         return r;
1152 }
1153
1154 /**
1155  * db8500_prcmu_get_ape_opp - get the current APE OPP
1156  *
1157  * Returns: the current APE OPP
1158  */
1159 int db8500_prcmu_get_ape_opp(void)
1160 {
1161         return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
1162 }
1163
1164 /**
1165  * prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
1166  * @enable: true to request the higher voltage, false to drop a request.
1167  *
1168  * Calls to this function to enable and disable requests must be balanced.
1169  */
1170 int prcmu_request_ape_opp_100_voltage(bool enable)
1171 {
1172         int r = 0;
1173         u8 header;
1174         static unsigned int requests;
1175
1176         mutex_lock(&mb1_transfer.lock);
1177
1178         if (enable) {
1179                 if (0 != requests++)
1180                         goto unlock_and_return;
1181                 header = MB1H_REQUEST_APE_OPP_100_VOLT;
1182         } else {
1183                 if (requests == 0) {
1184                         r = -EIO;
1185                         goto unlock_and_return;
1186                 } else if (1 != requests--) {
1187                         goto unlock_and_return;
1188                 }
1189                 header = MB1H_RELEASE_APE_OPP_100_VOLT;
1190         }
1191
1192         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1193                 cpu_relax();
1194
1195         writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1196
1197         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1198         wait_for_completion(&mb1_transfer.work);
1199
1200         if ((mb1_transfer.ack.header != header) ||
1201                 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1202                 r = -EIO;
1203
1204 unlock_and_return:
1205         mutex_unlock(&mb1_transfer.lock);
1206
1207         return r;
1208 }
1209
1210 /**
1211  * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
1212  *
1213  * This function releases the power state requirements of a USB wakeup.
1214  */
1215 int prcmu_release_usb_wakeup_state(void)
1216 {
1217         int r = 0;
1218
1219         mutex_lock(&mb1_transfer.lock);
1220
1221         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1222                 cpu_relax();
1223
1224         writeb(MB1H_RELEASE_USB_WAKEUP,
1225                 (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1226
1227         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1228         wait_for_completion(&mb1_transfer.work);
1229
1230         if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
1231                 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1232                 r = -EIO;
1233
1234         mutex_unlock(&mb1_transfer.lock);
1235
1236         return r;
1237 }
1238
1239 static int request_pll(u8 clock, bool enable)
1240 {
1241         int r = 0;
1242
1243         if (clock == PRCMU_PLLSOC0)
1244                 clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
1245         else if (clock == PRCMU_PLLSOC1)
1246                 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
1247         else
1248                 return -EINVAL;
1249
1250         mutex_lock(&mb1_transfer.lock);
1251
1252         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1253                 cpu_relax();
1254
1255         writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1256         writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
1257
1258         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1259         wait_for_completion(&mb1_transfer.work);
1260
1261         if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF)
1262                 r = -EIO;
1263
1264         mutex_unlock(&mb1_transfer.lock);
1265
1266         return r;
1267 }
1268
1269 /**
1270  * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
1271  * @epod_id: The EPOD to set
1272  * @epod_state: The new EPOD state
1273  *
1274  * This function sets the state of a EPOD (power domain). It may not be called
1275  * from interrupt context.
1276  */
1277 int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
1278 {
1279         int r = 0;
1280         bool ram_retention = false;
1281         int i;
1282
1283         /* check argument */
1284         BUG_ON(epod_id >= NUM_EPOD_ID);
1285
1286         /* set flag if retention is possible */
1287         switch (epod_id) {
1288         case EPOD_ID_SVAMMDSP:
1289         case EPOD_ID_SIAMMDSP:
1290         case EPOD_ID_ESRAM12:
1291         case EPOD_ID_ESRAM34:
1292                 ram_retention = true;
1293                 break;
1294         }
1295
1296         /* check argument */
1297         BUG_ON(epod_state > EPOD_STATE_ON);
1298         BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
1299
1300         /* get lock */
1301         mutex_lock(&mb2_transfer.lock);
1302
1303         /* wait for mailbox */
1304         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
1305                 cpu_relax();
1306
1307         /* fill in mailbox */
1308         for (i = 0; i < NUM_EPOD_ID; i++)
1309                 writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
1310         writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
1311
1312         writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
1313
1314         writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
1315
1316         /*
1317          * The current firmware version does not handle errors correctly,
1318          * and we cannot recover if there is an error.
1319          * This is expected to change when the firmware is updated.
1320          */
1321         if (!wait_for_completion_timeout(&mb2_transfer.work,
1322                         msecs_to_jiffies(20000))) {
1323                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1324                         __func__);
1325                 r = -EIO;
1326                 goto unlock_and_return;
1327         }
1328
1329         if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
1330                 r = -EIO;
1331
1332 unlock_and_return:
1333         mutex_unlock(&mb2_transfer.lock);
1334         return r;
1335 }
1336
1337 /**
1338  * prcmu_configure_auto_pm - Configure autonomous power management.
1339  * @sleep: Configuration for ApSleep.
1340  * @idle:  Configuration for ApIdle.
1341  */
1342 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
1343         struct prcmu_auto_pm_config *idle)
1344 {
1345         u32 sleep_cfg;
1346         u32 idle_cfg;
1347         unsigned long flags;
1348
1349         BUG_ON((sleep == NULL) || (idle == NULL));
1350
1351         sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
1352         sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
1353         sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
1354         sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
1355         sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
1356         sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
1357
1358         idle_cfg = (idle->sva_auto_pm_enable & 0xF);
1359         idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
1360         idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
1361         idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
1362         idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
1363         idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
1364
1365         spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
1366
1367         /*
1368          * The autonomous power management configuration is done through
1369          * fields in mailbox 2, but these fields are only used as shared
1370          * variables - i.e. there is no need to send a message.
1371          */
1372         writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
1373         writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
1374
1375         mb2_transfer.auto_pm_enabled =
1376                 ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1377                  (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1378                  (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1379                  (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
1380
1381         spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
1382 }
1383 EXPORT_SYMBOL(prcmu_configure_auto_pm);
1384
1385 bool prcmu_is_auto_pm_enabled(void)
1386 {
1387         return mb2_transfer.auto_pm_enabled;
1388 }
1389
1390 static int request_sysclk(bool enable)
1391 {
1392         int r;
1393         unsigned long flags;
1394
1395         r = 0;
1396
1397         mutex_lock(&mb3_transfer.sysclk_lock);
1398
1399         spin_lock_irqsave(&mb3_transfer.lock, flags);
1400
1401         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
1402                 cpu_relax();
1403
1404         writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
1405
1406         writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
1407         writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
1408
1409         spin_unlock_irqrestore(&mb3_transfer.lock, flags);
1410
1411         /*
1412          * The firmware only sends an ACK if we want to enable the
1413          * SysClk, and it succeeds.
1414          */
1415         if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
1416                         msecs_to_jiffies(20000))) {
1417                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1418                         __func__);
1419                 r = -EIO;
1420         }
1421
1422         mutex_unlock(&mb3_transfer.sysclk_lock);
1423
1424         return r;
1425 }
1426
1427 static int request_timclk(bool enable)
1428 {
1429         u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
1430
1431         if (!enable)
1432                 val |= PRCM_TCR_STOP_TIMERS;
1433         writel(val, PRCM_TCR);
1434
1435         return 0;
1436 }
1437
1438 static int request_clock(u8 clock, bool enable)
1439 {
1440         u32 val;
1441         unsigned long flags;
1442
1443         spin_lock_irqsave(&clk_mgt_lock, flags);
1444
1445         /* Grab the HW semaphore. */
1446         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1447                 cpu_relax();
1448
1449         val = readl(clk_mgt[clock].reg);
1450         if (enable) {
1451                 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1452         } else {
1453                 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1454                 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1455         }
1456         writel(val, clk_mgt[clock].reg);
1457
1458         /* Release the HW semaphore. */
1459         writel(0, PRCM_SEM);
1460
1461         spin_unlock_irqrestore(&clk_mgt_lock, flags);
1462
1463         return 0;
1464 }
1465
1466 static int request_sga_clock(u8 clock, bool enable)
1467 {
1468         u32 val;
1469         int ret;
1470
1471         if (enable) {
1472                 val = readl(PRCM_CGATING_BYPASS);
1473                 writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1474         }
1475
1476         ret = request_clock(clock, enable);
1477
1478         if (!ret && !enable) {
1479                 val = readl(PRCM_CGATING_BYPASS);
1480                 writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1481         }
1482
1483         return ret;
1484 }
1485
1486 static inline bool plldsi_locked(void)
1487 {
1488         return (readl(PRCM_PLLDSI_LOCKP) &
1489                 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1490                  PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) ==
1491                 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1492                  PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3);
1493 }
1494
1495 static int request_plldsi(bool enable)
1496 {
1497         int r = 0;
1498         u32 val;
1499
1500         writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1501                 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ?
1502                 PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET));
1503
1504         val = readl(PRCM_PLLDSI_ENABLE);
1505         if (enable)
1506                 val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1507         else
1508                 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1509         writel(val, PRCM_PLLDSI_ENABLE);
1510
1511         if (enable) {
1512                 unsigned int i;
1513                 bool locked = plldsi_locked();
1514
1515                 for (i = 10; !locked && (i > 0); --i) {
1516                         udelay(100);
1517                         locked = plldsi_locked();
1518                 }
1519                 if (locked) {
1520                         writel(PRCM_APE_RESETN_DSIPLL_RESETN,
1521                                 PRCM_APE_RESETN_SET);
1522                 } else {
1523                         writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1524                                 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI),
1525                                 PRCM_MMIP_LS_CLAMP_SET);
1526                         val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1527                         writel(val, PRCM_PLLDSI_ENABLE);
1528                         r = -EAGAIN;
1529                 }
1530         } else {
1531                 writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);
1532         }
1533         return r;
1534 }
1535
1536 static int request_dsiclk(u8 n, bool enable)
1537 {
1538         u32 val;
1539
1540         val = readl(PRCM_DSI_PLLOUT_SEL);
1541         val &= ~dsiclk[n].divsel_mask;
1542         val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
1543                 dsiclk[n].divsel_shift);
1544         writel(val, PRCM_DSI_PLLOUT_SEL);
1545         return 0;
1546 }
1547
1548 static int request_dsiescclk(u8 n, bool enable)
1549 {
1550         u32 val;
1551
1552         val = readl(PRCM_DSITVCLK_DIV);
1553         enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
1554         writel(val, PRCM_DSITVCLK_DIV);
1555         return 0;
1556 }
1557
1558 /**
1559  * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
1560  * @clock:      The clock for which the request is made.
1561  * @enable:     Whether the clock should be enabled (true) or disabled (false).
1562  *
1563  * This function should only be used by the clock implementation.
1564  * Do not use it from any other place!
1565  */
1566 int db8500_prcmu_request_clock(u8 clock, bool enable)
1567 {
1568         if (clock == PRCMU_SGACLK)
1569                 return request_sga_clock(clock, enable);
1570         else if (clock < PRCMU_NUM_REG_CLOCKS)
1571                 return request_clock(clock, enable);
1572         else if (clock == PRCMU_TIMCLK)
1573                 return request_timclk(enable);
1574         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1575                 return request_dsiclk((clock - PRCMU_DSI0CLK), enable);
1576         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1577                 return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable);
1578         else if (clock == PRCMU_PLLDSI)
1579                 return request_plldsi(enable);
1580         else if (clock == PRCMU_SYSCLK)
1581                 return request_sysclk(enable);
1582         else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1))
1583                 return request_pll(clock, enable);
1584         else
1585                 return -EINVAL;
1586 }
1587
1588 static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
1589         int branch)
1590 {
1591         u64 rate;
1592         u32 val;
1593         u32 d;
1594         u32 div = 1;
1595
1596         val = readl(reg);
1597
1598         rate = src_rate;
1599         rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
1600
1601         d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
1602         if (d > 1)
1603                 div *= d;
1604
1605         d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
1606         if (d > 1)
1607                 div *= d;
1608
1609         if (val & PRCM_PLL_FREQ_SELDIV2)
1610                 div *= 2;
1611
1612         if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
1613                 (val & PRCM_PLL_FREQ_DIV2EN) &&
1614                 ((reg == PRCM_PLLSOC0_FREQ) ||
1615                  (reg == PRCM_PLLDDR_FREQ))))
1616                 div *= 2;
1617
1618         (void)do_div(rate, div);
1619
1620         return (unsigned long)rate;
1621 }
1622
1623 #define ROOT_CLOCK_RATE 38400000
1624
1625 static unsigned long clock_rate(u8 clock)
1626 {
1627         u32 val;
1628         u32 pllsw;
1629         unsigned long rate = ROOT_CLOCK_RATE;
1630
1631         val = readl(clk_mgt[clock].reg);
1632
1633         if (val & PRCM_CLK_MGT_CLK38) {
1634                 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
1635                         rate /= 2;
1636                 return rate;
1637         }
1638
1639         val |= clk_mgt[clock].pllsw;
1640         pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1641
1642         if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1643                 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1644         else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1645                 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1646         else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR)
1647                 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1648         else
1649                 return 0;
1650
1651         if ((clock == PRCMU_SGACLK) &&
1652                 (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
1653                 u64 r = (rate * 10);
1654
1655                 (void)do_div(r, 25);
1656                 return (unsigned long)r;
1657         }
1658         val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1659         if (val)
1660                 return rate / val;
1661         else
1662                 return 0;
1663 }
1664
1665 static unsigned long dsiclk_rate(u8 n)
1666 {
1667         u32 divsel;
1668         u32 div = 1;
1669
1670         divsel = readl(PRCM_DSI_PLLOUT_SEL);
1671         divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);
1672
1673         if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
1674                 divsel = dsiclk[n].divsel;
1675
1676         switch (divsel) {
1677         case PRCM_DSI_PLLOUT_SEL_PHI_4:
1678                 div *= 2;
1679         case PRCM_DSI_PLLOUT_SEL_PHI_2:
1680                 div *= 2;
1681         case PRCM_DSI_PLLOUT_SEL_PHI:
1682                 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1683                         PLL_RAW) / div;
1684         default:
1685                 return 0;
1686         }
1687 }
1688
1689 static unsigned long dsiescclk_rate(u8 n)
1690 {
1691         u32 div;
1692
1693         div = readl(PRCM_DSITVCLK_DIV);
1694         div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
1695         return clock_rate(PRCMU_TVCLK) / max((u32)1, div);
1696 }
1697
1698 unsigned long prcmu_clock_rate(u8 clock)
1699 {
1700         if (clock < PRCMU_NUM_REG_CLOCKS)
1701                 return clock_rate(clock);
1702         else if (clock == PRCMU_TIMCLK)
1703                 return ROOT_CLOCK_RATE / 16;
1704         else if (clock == PRCMU_SYSCLK)
1705                 return ROOT_CLOCK_RATE;
1706         else if (clock == PRCMU_PLLSOC0)
1707                 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1708         else if (clock == PRCMU_PLLSOC1)
1709                 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1710         else if (clock == PRCMU_PLLDDR)
1711                 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1712         else if (clock == PRCMU_PLLDSI)
1713                 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1714                         PLL_RAW);
1715         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1716                 return dsiclk_rate(clock - PRCMU_DSI0CLK);
1717         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1718                 return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK);
1719         else
1720                 return 0;
1721 }
1722
1723 static unsigned long clock_source_rate(u32 clk_mgt_val, int branch)
1724 {
1725         if (clk_mgt_val & PRCM_CLK_MGT_CLK38)
1726                 return ROOT_CLOCK_RATE;
1727         clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK;
1728         if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1729                 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch);
1730         else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1731                 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch);
1732         else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR)
1733                 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch);
1734         else
1735                 return 0;
1736 }
1737
1738 static u32 clock_divider(unsigned long src_rate, unsigned long rate)
1739 {
1740         u32 div;
1741
1742         div = (src_rate / rate);
1743         if (div == 0)
1744                 return 1;
1745         if (rate < (src_rate / div))
1746                 div++;
1747         return div;
1748 }
1749
1750 static long round_clock_rate(u8 clock, unsigned long rate)
1751 {
1752         u32 val;
1753         u32 div;
1754         unsigned long src_rate;
1755         long rounded_rate;
1756
1757         val = readl(clk_mgt[clock].reg);
1758         src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1759                 clk_mgt[clock].branch);
1760         div = clock_divider(src_rate, rate);
1761         if (val & PRCM_CLK_MGT_CLK38) {
1762                 if (clk_mgt[clock].clk38div) {
1763                         if (div > 2)
1764                                 div = 2;
1765                 } else {
1766                         div = 1;
1767                 }
1768         } else if ((clock == PRCMU_SGACLK) && (div == 3)) {
1769                 u64 r = (src_rate * 10);
1770
1771                 (void)do_div(r, 25);
1772                 if (r <= rate)
1773                         return (unsigned long)r;
1774         }
1775         rounded_rate = (src_rate / min(div, (u32)31));
1776
1777         return rounded_rate;
1778 }
1779
1780 #define MIN_PLL_VCO_RATE 600000000ULL
1781 #define MAX_PLL_VCO_RATE 1680640000ULL
1782
1783 static long round_plldsi_rate(unsigned long rate)
1784 {
1785         long rounded_rate = 0;
1786         unsigned long src_rate;
1787         unsigned long rem;
1788         u32 r;
1789
1790         src_rate = clock_rate(PRCMU_HDMICLK);
1791         rem = rate;
1792
1793         for (r = 7; (rem > 0) && (r > 0); r--) {
1794                 u64 d;
1795
1796                 d = (r * rate);
1797                 (void)do_div(d, src_rate);
1798                 if (d < 6)
1799                         d = 6;
1800                 else if (d > 255)
1801                         d = 255;
1802                 d *= src_rate;
1803                 if (((2 * d) < (r * MIN_PLL_VCO_RATE)) ||
1804                         ((r * MAX_PLL_VCO_RATE) < (2 * d)))
1805                         continue;
1806                 (void)do_div(d, r);
1807                 if (rate < d) {
1808                         if (rounded_rate == 0)
1809                                 rounded_rate = (long)d;
1810                         break;
1811                 }
1812                 if ((rate - d) < rem) {
1813                         rem = (rate - d);
1814                         rounded_rate = (long)d;
1815                 }
1816         }
1817         return rounded_rate;
1818 }
1819
1820 static long round_dsiclk_rate(unsigned long rate)
1821 {
1822         u32 div;
1823         unsigned long src_rate;
1824         long rounded_rate;
1825
1826         src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1827                 PLL_RAW);
1828         div = clock_divider(src_rate, rate);
1829         rounded_rate = (src_rate / ((div > 2) ? 4 : div));
1830
1831         return rounded_rate;
1832 }
1833
1834 static long round_dsiescclk_rate(unsigned long rate)
1835 {
1836         u32 div;
1837         unsigned long src_rate;
1838         long rounded_rate;
1839
1840         src_rate = clock_rate(PRCMU_TVCLK);
1841         div = clock_divider(src_rate, rate);
1842         rounded_rate = (src_rate / min(div, (u32)255));
1843
1844         return rounded_rate;
1845 }
1846
1847 long prcmu_round_clock_rate(u8 clock, unsigned long rate)
1848 {
1849         if (clock < PRCMU_NUM_REG_CLOCKS)
1850                 return round_clock_rate(clock, rate);
1851         else if (clock == PRCMU_PLLDSI)
1852                 return round_plldsi_rate(rate);
1853         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1854                 return round_dsiclk_rate(rate);
1855         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1856                 return round_dsiescclk_rate(rate);
1857         else
1858                 return (long)prcmu_clock_rate(clock);
1859 }
1860
1861 static void set_clock_rate(u8 clock, unsigned long rate)
1862 {
1863         u32 val;
1864         u32 div;
1865         unsigned long src_rate;
1866         unsigned long flags;
1867
1868         spin_lock_irqsave(&clk_mgt_lock, flags);
1869
1870         /* Grab the HW semaphore. */
1871         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1872                 cpu_relax();
1873
1874         val = readl(clk_mgt[clock].reg);
1875         src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1876                 clk_mgt[clock].branch);
1877         div = clock_divider(src_rate, rate);
1878         if (val & PRCM_CLK_MGT_CLK38) {
1879                 if (clk_mgt[clock].clk38div) {
1880                         if (div > 1)
1881                                 val |= PRCM_CLK_MGT_CLK38DIV;
1882                         else
1883                                 val &= ~PRCM_CLK_MGT_CLK38DIV;
1884                 }
1885         } else if (clock == PRCMU_SGACLK) {
1886                 val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
1887                         PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN);
1888                 if (div == 3) {
1889                         u64 r = (src_rate * 10);
1890
1891                         (void)do_div(r, 25);
1892                         if (r <= rate) {
1893                                 val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
1894                                 div = 0;
1895                         }
1896                 }
1897                 val |= min(div, (u32)31);
1898         } else {
1899                 val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
1900                 val |= min(div, (u32)31);
1901         }
1902         writel(val, clk_mgt[clock].reg);
1903
1904         /* Release the HW semaphore. */
1905         writel(0, PRCM_SEM);
1906
1907         spin_unlock_irqrestore(&clk_mgt_lock, flags);
1908 }
1909
1910 static int set_plldsi_rate(unsigned long rate)
1911 {
1912         unsigned long src_rate;
1913         unsigned long rem;
1914         u32 pll_freq = 0;
1915         u32 r;
1916
1917         src_rate = clock_rate(PRCMU_HDMICLK);
1918         rem = rate;
1919
1920         for (r = 7; (rem > 0) && (r > 0); r--) {
1921                 u64 d;
1922                 u64 hwrate;
1923
1924                 d = (r * rate);
1925                 (void)do_div(d, src_rate);
1926                 if (d < 6)
1927                         d = 6;
1928                 else if (d > 255)
1929                         d = 255;
1930                 hwrate = (d * src_rate);
1931                 if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) ||
1932                         ((r * MAX_PLL_VCO_RATE) < (2 * hwrate)))
1933                         continue;
1934                 (void)do_div(hwrate, r);
1935                 if (rate < hwrate) {
1936                         if (pll_freq == 0)
1937                                 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1938                                         (r << PRCM_PLL_FREQ_R_SHIFT));
1939                         break;
1940                 }
1941                 if ((rate - hwrate) < rem) {
1942                         rem = (rate - hwrate);
1943                         pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1944                                 (r << PRCM_PLL_FREQ_R_SHIFT));
1945                 }
1946         }
1947         if (pll_freq == 0)
1948                 return -EINVAL;
1949
1950         pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT);
1951         writel(pll_freq, PRCM_PLLDSI_FREQ);
1952
1953         return 0;
1954 }
1955
1956 static void set_dsiclk_rate(u8 n, unsigned long rate)
1957 {
1958         u32 val;
1959         u32 div;
1960
1961         div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,
1962                         clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
1963
1964         dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
1965                            (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 :
1966                            /* else */   PRCM_DSI_PLLOUT_SEL_PHI_4;
1967
1968         val = readl(PRCM_DSI_PLLOUT_SEL);
1969         val &= ~dsiclk[n].divsel_mask;
1970         val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
1971         writel(val, PRCM_DSI_PLLOUT_SEL);
1972 }
1973
1974 static void set_dsiescclk_rate(u8 n, unsigned long rate)
1975 {
1976         u32 val;
1977         u32 div;
1978
1979         div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
1980         val = readl(PRCM_DSITVCLK_DIV);
1981         val &= ~dsiescclk[n].div_mask;
1982         val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
1983         writel(val, PRCM_DSITVCLK_DIV);
1984 }
1985
1986 int prcmu_set_clock_rate(u8 clock, unsigned long rate)
1987 {
1988         if (clock < PRCMU_NUM_REG_CLOCKS)
1989                 set_clock_rate(clock, rate);
1990         else if (clock == PRCMU_PLLDSI)
1991                 return set_plldsi_rate(rate);
1992         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1993                 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
1994         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1995                 set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);
1996         return 0;
1997 }
1998
1999 int db8500_prcmu_config_esram0_deep_sleep(u8 state)
2000 {
2001         if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
2002             (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
2003                 return -EINVAL;
2004
2005         mutex_lock(&mb4_transfer.lock);
2006
2007         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2008                 cpu_relax();
2009
2010         writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2011         writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
2012                (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
2013         writeb(DDR_PWR_STATE_ON,
2014                (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
2015         writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
2016
2017         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2018         wait_for_completion(&mb4_transfer.work);
2019
2020         mutex_unlock(&mb4_transfer.lock);
2021
2022         return 0;
2023 }
2024
2025 int db8500_prcmu_config_hotdog(u8 threshold)
2026 {
2027         mutex_lock(&mb4_transfer.lock);
2028
2029         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2030                 cpu_relax();
2031
2032         writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
2033         writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2034
2035         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2036         wait_for_completion(&mb4_transfer.work);
2037
2038         mutex_unlock(&mb4_transfer.lock);
2039
2040         return 0;
2041 }
2042
2043 int db8500_prcmu_config_hotmon(u8 low, u8 high)
2044 {
2045         mutex_lock(&mb4_transfer.lock);
2046
2047         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2048                 cpu_relax();
2049
2050         writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
2051         writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
2052         writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
2053                 (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
2054         writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2055
2056         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2057         wait_for_completion(&mb4_transfer.work);
2058
2059         mutex_unlock(&mb4_transfer.lock);
2060
2061         return 0;
2062 }
2063
2064 static int config_hot_period(u16 val)
2065 {
2066         mutex_lock(&mb4_transfer.lock);
2067
2068         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2069                 cpu_relax();
2070
2071         writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
2072         writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2073
2074         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2075         wait_for_completion(&mb4_transfer.work);
2076
2077         mutex_unlock(&mb4_transfer.lock);
2078
2079         return 0;
2080 }
2081
2082 int db8500_prcmu_start_temp_sense(u16 cycles32k)
2083 {
2084         if (cycles32k == 0xFFFF)
2085                 return -EINVAL;
2086
2087         return config_hot_period(cycles32k);
2088 }
2089
2090 int db8500_prcmu_stop_temp_sense(void)
2091 {
2092         return config_hot_period(0xFFFF);
2093 }
2094
2095 static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3)
2096 {
2097
2098         mutex_lock(&mb4_transfer.lock);
2099
2100         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2101                 cpu_relax();
2102
2103         writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));
2104         writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));
2105         writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));
2106         writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));
2107
2108         writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2109
2110         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2111         wait_for_completion(&mb4_transfer.work);
2112
2113         mutex_unlock(&mb4_transfer.lock);
2114
2115         return 0;
2116
2117 }
2118
2119 int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
2120 {
2121         BUG_ON(num == 0 || num > 0xf);
2122         return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0,
2123                             sleep_auto_off ? A9WDOG_AUTO_OFF_EN :
2124                             A9WDOG_AUTO_OFF_DIS);
2125 }
2126
2127 int db8500_prcmu_enable_a9wdog(u8 id)
2128 {
2129         return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0);
2130 }
2131
2132 int db8500_prcmu_disable_a9wdog(u8 id)
2133 {
2134         return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0);
2135 }
2136
2137 int db8500_prcmu_kick_a9wdog(u8 id)
2138 {
2139         return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0);
2140 }
2141
2142 /*
2143  * timeout is 28 bit, in ms.
2144  */
2145 int db8500_prcmu_load_a9wdog(u8 id, u32 timeout)
2146 {
2147         return prcmu_a9wdog(MB4H_A9WDOG_LOAD,
2148                             (id & A9WDOG_ID_MASK) |
2149                             /*
2150                              * Put the lowest 28 bits of timeout at
2151                              * offset 4. Four first bits are used for id.
2152                              */
2153                             (u8)((timeout << 4) & 0xf0),
2154                             (u8)((timeout >> 4) & 0xff),
2155                             (u8)((timeout >> 12) & 0xff),
2156                             (u8)((timeout >> 20) & 0xff));
2157 }
2158
2159 /**
2160  * prcmu_abb_read() - Read register value(s) from the ABB.
2161  * @slave:      The I2C slave address.
2162  * @reg:        The (start) register address.
2163  * @value:      The read out value(s).
2164  * @size:       The number of registers to read.
2165  *
2166  * Reads register value(s) from the ABB.
2167  * @size has to be 1 for the current firmware version.
2168  */
2169 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
2170 {
2171         int r;
2172
2173         if (size != 1)
2174                 return -EINVAL;
2175
2176         mutex_lock(&mb5_transfer.lock);
2177
2178         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2179                 cpu_relax();
2180
2181         writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2182         writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2183         writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2184         writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2185         writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2186
2187         writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2188
2189         if (!wait_for_completion_timeout(&mb5_transfer.work,
2190                                 msecs_to_jiffies(20000))) {
2191                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2192                         __func__);
2193                 r = -EIO;
2194         } else {
2195                 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
2196         }
2197
2198         if (!r)
2199                 *value = mb5_transfer.ack.value;
2200
2201         mutex_unlock(&mb5_transfer.lock);
2202
2203         return r;
2204 }
2205
2206 /**
2207  * prcmu_abb_write_masked() - Write masked register value(s) to the ABB.
2208  * @slave:      The I2C slave address.
2209  * @reg:        The (start) register address.
2210  * @value:      The value(s) to write.
2211  * @mask:       The mask(s) to use.
2212  * @size:       The number of registers to write.
2213  *
2214  * Writes masked register value(s) to the ABB.
2215  * For each @value, only the bits set to 1 in the corresponding @mask
2216  * will be written. The other bits are not changed.
2217  * @size has to be 1 for the current firmware version.
2218  */
2219 int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size)
2220 {
2221         int r;
2222
2223         if (size != 1)
2224                 return -EINVAL;
2225
2226         mutex_lock(&mb5_transfer.lock);
2227
2228         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2229                 cpu_relax();
2230
2231         writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2232         writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2233         writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2234         writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2235         writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2236
2237         writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2238
2239         if (!wait_for_completion_timeout(&mb5_transfer.work,
2240                                 msecs_to_jiffies(20000))) {
2241                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2242                         __func__);
2243                 r = -EIO;
2244         } else {
2245                 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
2246         }
2247
2248         mutex_unlock(&mb5_transfer.lock);
2249
2250         return r;
2251 }
2252
2253 /**
2254  * prcmu_abb_write() - Write register value(s) to the ABB.
2255  * @slave:      The I2C slave address.
2256  * @reg:        The (start) register address.
2257  * @value:      The value(s) to write.
2258  * @size:       The number of registers to write.
2259  *
2260  * Writes register value(s) to the ABB.
2261  * @size has to be 1 for the current firmware version.
2262  */
2263 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
2264 {
2265         u8 mask = ~0;
2266
2267         return prcmu_abb_write_masked(slave, reg, value, &mask, size);
2268 }
2269
2270 /**
2271  * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
2272  */
2273 int prcmu_ac_wake_req(void)
2274 {
2275         u32 val;
2276         int ret = 0;
2277
2278         mutex_lock(&mb0_transfer.ac_wake_lock);
2279
2280         val = readl(PRCM_HOSTACCESS_REQ);
2281         if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
2282                 goto unlock_and_return;
2283
2284         atomic_set(&ac_wake_req_state, 1);
2285
2286         /*
2287          * Force Modem Wake-up before hostaccess_req ping-pong.
2288          * It prevents Modem to enter in Sleep while acking the hostaccess
2289          * request. The 31us delay has been calculated by HWI.
2290          */
2291         val |= PRCM_HOSTACCESS_REQ_WAKE_REQ;
2292         writel(val, PRCM_HOSTACCESS_REQ);
2293
2294         udelay(31);
2295
2296         val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ;
2297         writel(val, PRCM_HOSTACCESS_REQ);
2298
2299         if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2300                         msecs_to_jiffies(5000))) {
2301 #if defined(CONFIG_DBX500_PRCMU_DEBUG)
2302                 db8500_prcmu_debug_dump(__func__, true, true);
2303 #endif
2304                 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2305                         __func__);
2306                 ret = -EFAULT;
2307         }
2308
2309 unlock_and_return:
2310         mutex_unlock(&mb0_transfer.ac_wake_lock);
2311         return ret;
2312 }
2313
2314 /**
2315  * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
2316  */
2317 void prcmu_ac_sleep_req()
2318 {
2319         u32 val;
2320
2321         mutex_lock(&mb0_transfer.ac_wake_lock);
2322
2323         val = readl(PRCM_HOSTACCESS_REQ);
2324         if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
2325                 goto unlock_and_return;
2326
2327         writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
2328                 PRCM_HOSTACCESS_REQ);
2329
2330         if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2331                         msecs_to_jiffies(5000))) {
2332                 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2333                         __func__);
2334         }
2335
2336         atomic_set(&ac_wake_req_state, 0);
2337
2338 unlock_and_return:
2339         mutex_unlock(&mb0_transfer.ac_wake_lock);
2340 }
2341
2342 bool db8500_prcmu_is_ac_wake_requested(void)
2343 {
2344         return (atomic_read(&ac_wake_req_state) != 0);
2345 }
2346
2347 /**
2348  * db8500_prcmu_system_reset - System reset
2349  *
2350  * Saves the reset reason code and then sets the APE_SOFTRST register which
2351  * fires interrupt to fw
2352  */
2353 void db8500_prcmu_system_reset(u16 reset_code)
2354 {
2355         writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
2356         writel(1, PRCM_APE_SOFTRST);
2357 }
2358
2359 /**
2360  * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
2361  *
2362  * Retrieves the reset reason code stored by prcmu_system_reset() before
2363  * last restart.
2364  */
2365 u16 db8500_prcmu_get_reset_code(void)
2366 {
2367         return readw(tcdm_base + PRCM_SW_RST_REASON);
2368 }
2369
2370 /**
2371  * db8500_prcmu_reset_modem - ask the PRCMU to reset modem
2372  */
2373 void db8500_prcmu_modem_reset(void)
2374 {
2375         mutex_lock(&mb1_transfer.lock);
2376
2377         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
2378                 cpu_relax();
2379
2380         writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
2381         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
2382         wait_for_completion(&mb1_transfer.work);
2383
2384         /*
2385          * No need to check return from PRCMU as modem should go in reset state
2386          * This state is already managed by upper layer
2387          */
2388
2389         mutex_unlock(&mb1_transfer.lock);
2390 }
2391
2392 static void ack_dbb_wakeup(void)
2393 {
2394         unsigned long flags;
2395
2396         spin_lock_irqsave(&mb0_transfer.lock, flags);
2397
2398         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
2399                 cpu_relax();
2400
2401         writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
2402         writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
2403
2404         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2405 }
2406
2407 static inline void print_unknown_header_warning(u8 n, u8 header)
2408 {
2409         pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
2410                 header, n);
2411 }
2412
2413 static bool read_mailbox_0(void)
2414 {
2415         bool r;
2416         u32 ev;
2417         unsigned int n;
2418         u8 header;
2419
2420         header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
2421         switch (header) {
2422         case MB0H_WAKEUP_EXE:
2423         case MB0H_WAKEUP_SLEEP:
2424                 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
2425                         ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
2426                 else
2427                         ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
2428
2429                 if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
2430                         complete(&mb0_transfer.ac_wake_work);
2431                 if (ev & WAKEUP_BIT_SYSCLK_OK)
2432                         complete(&mb3_transfer.sysclk_work);
2433
2434                 ev &= mb0_transfer.req.dbb_irqs;
2435
2436                 for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
2437                         if (ev & prcmu_irq_bit[n])
2438                                 generic_handle_irq(IRQ_PRCMU_BASE + n);
2439                 }
2440                 r = true;
2441                 break;
2442         default:
2443                 print_unknown_header_warning(0, header);
2444                 r = false;
2445                 break;
2446         }
2447         writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
2448         return r;
2449 }
2450
2451 static bool read_mailbox_1(void)
2452 {
2453         mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
2454         mb1_transfer.ack.arm_opp = readb(tcdm_base +
2455                 PRCM_ACK_MB1_CURRENT_ARM_OPP);
2456         mb1_transfer.ack.ape_opp = readb(tcdm_base +
2457                 PRCM_ACK_MB1_CURRENT_APE_OPP);
2458         mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
2459                 PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
2460         writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
2461         complete(&mb1_transfer.work);
2462         return false;
2463 }
2464
2465 static bool read_mailbox_2(void)
2466 {
2467         mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
2468         writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
2469         complete(&mb2_transfer.work);
2470         return false;
2471 }
2472
2473 static bool read_mailbox_3(void)
2474 {
2475         writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
2476         return false;
2477 }
2478
2479 static bool read_mailbox_4(void)
2480 {
2481         u8 header;
2482         bool do_complete = true;
2483
2484         header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
2485         switch (header) {
2486         case MB4H_MEM_ST:
2487         case MB4H_HOTDOG:
2488         case MB4H_HOTMON:
2489         case MB4H_HOT_PERIOD:
2490         case MB4H_A9WDOG_CONF:
2491         case MB4H_A9WDOG_EN:
2492         case MB4H_A9WDOG_DIS:
2493         case MB4H_A9WDOG_LOAD:
2494         case MB4H_A9WDOG_KICK:
2495                 break;
2496         default:
2497                 print_unknown_header_warning(4, header);
2498                 do_complete = false;
2499                 break;
2500         }
2501
2502         writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
2503
2504         if (do_complete)
2505                 complete(&mb4_transfer.work);
2506
2507         return false;
2508 }
2509
2510 static bool read_mailbox_5(void)
2511 {
2512         mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
2513         mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
2514         writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
2515         complete(&mb5_transfer.work);
2516         return false;
2517 }
2518
2519 static bool read_mailbox_6(void)
2520 {
2521         writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
2522         return false;
2523 }
2524
2525 static bool read_mailbox_7(void)
2526 {
2527         writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
2528         return false;
2529 }
2530
2531 static bool (* const read_mailbox[NUM_MB])(void) = {
2532         read_mailbox_0,
2533         read_mailbox_1,
2534         read_mailbox_2,
2535         read_mailbox_3,
2536         read_mailbox_4,
2537         read_mailbox_5,
2538         read_mailbox_6,
2539         read_mailbox_7
2540 };
2541
2542 static irqreturn_t prcmu_irq_handler(int irq, void *data)
2543 {
2544         u32 bits;
2545         u8 n;
2546         irqreturn_t r;
2547
2548         bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
2549         if (unlikely(!bits))
2550                 return IRQ_NONE;
2551
2552         r = IRQ_HANDLED;
2553         for (n = 0; bits; n++) {
2554                 if (bits & MBOX_BIT(n)) {
2555                         bits -= MBOX_BIT(n);
2556                         if (read_mailbox[n]())
2557                                 r = IRQ_WAKE_THREAD;
2558                 }
2559         }
2560         return r;
2561 }
2562
2563 static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
2564 {
2565         ack_dbb_wakeup();
2566         return IRQ_HANDLED;
2567 }
2568
2569 static void prcmu_mask_work(struct work_struct *work)
2570 {
2571         unsigned long flags;
2572
2573         spin_lock_irqsave(&mb0_transfer.lock, flags);
2574
2575         config_wakeups();
2576
2577         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2578 }
2579
2580 static void prcmu_irq_mask(struct irq_data *d)
2581 {
2582         unsigned long flags;
2583
2584         spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2585
2586         mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE];
2587
2588         spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2589
2590         if (d->irq != IRQ_PRCMU_CA_SLEEP)
2591                 schedule_work(&mb0_transfer.mask_work);
2592 }
2593
2594 static void prcmu_irq_unmask(struct irq_data *d)
2595 {
2596         unsigned long flags;
2597
2598         spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2599
2600         mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE];
2601
2602         spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2603
2604         if (d->irq != IRQ_PRCMU_CA_SLEEP)
2605                 schedule_work(&mb0_transfer.mask_work);
2606 }
2607
2608 static void noop(struct irq_data *d)
2609 {
2610 }
2611
2612 static struct irq_chip prcmu_irq_chip = {
2613         .name           = "prcmu",
2614         .irq_disable    = prcmu_irq_mask,
2615         .irq_ack        = noop,
2616         .irq_mask       = prcmu_irq_mask,
2617         .irq_unmask     = prcmu_irq_unmask,
2618 };
2619
2620 static char *fw_project_name(u8 project)
2621 {
2622         switch (project) {
2623         case PRCMU_FW_PROJECT_U8500:
2624                 return "U8500";
2625         case PRCMU_FW_PROJECT_U8500_C2:
2626                 return "U8500 C2";
2627         case PRCMU_FW_PROJECT_U9500:
2628                 return "U9500";
2629         case PRCMU_FW_PROJECT_U9500_C2:
2630                 return "U9500 C2";
2631         case PRCMU_FW_PROJECT_U8520:
2632                 return "U8520";
2633         case PRCMU_FW_PROJECT_U8420:
2634                 return "U8420";
2635         default:
2636                 return "Unknown";
2637         }
2638 }
2639
2640 void __init db8500_prcmu_early_init(void)
2641 {
2642         unsigned int i;
2643         if (cpu_is_u8500v2()) {
2644                 void *tcpm_base = ioremap_nocache(U8500_PRCMU_TCPM_BASE, SZ_4K);
2645
2646                 if (tcpm_base != NULL) {
2647                         u32 version;
2648                         version = readl(tcpm_base + PRCMU_FW_VERSION_OFFSET);
2649                         fw_info.version.project = version & 0xFF;
2650                         fw_info.version.api_version = (version >> 8) & 0xFF;
2651                         fw_info.version.func_version = (version >> 16) & 0xFF;
2652                         fw_info.version.errata = (version >> 24) & 0xFF;
2653                         fw_info.valid = true;
2654                         pr_info("PRCMU firmware: %s, version %d.%d.%d\n",
2655                                 fw_project_name(fw_info.version.project),
2656                                 (version >> 8) & 0xFF, (version >> 16) & 0xFF,
2657                                 (version >> 24) & 0xFF);
2658                         iounmap(tcpm_base);
2659                 }
2660
2661                 tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE);
2662         } else {
2663                 pr_err("prcmu: Unsupported chip version\n");
2664                 BUG();
2665         }
2666
2667         spin_lock_init(&mb0_transfer.lock);
2668         spin_lock_init(&mb0_transfer.dbb_irqs_lock);
2669         mutex_init(&mb0_transfer.ac_wake_lock);
2670         init_completion(&mb0_transfer.ac_wake_work);
2671         mutex_init(&mb1_transfer.lock);
2672         init_completion(&mb1_transfer.work);
2673         mb1_transfer.ape_opp = APE_NO_CHANGE;
2674         mutex_init(&mb2_transfer.lock);
2675         init_completion(&mb2_transfer.work);
2676         spin_lock_init(&mb2_transfer.auto_pm_lock);
2677         spin_lock_init(&mb3_transfer.lock);
2678         mutex_init(&mb3_transfer.sysclk_lock);
2679         init_completion(&mb3_transfer.sysclk_work);
2680         mutex_init(&mb4_transfer.lock);
2681         init_completion(&mb4_transfer.work);
2682         mutex_init(&mb5_transfer.lock);
2683         init_completion(&mb5_transfer.work);
2684
2685         INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
2686
2687         /* Initalize irqs. */
2688         for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) {
2689                 unsigned int irq;
2690
2691                 irq = IRQ_PRCMU_BASE + i;
2692                 irq_set_chip_and_handler(irq, &prcmu_irq_chip,
2693                                          handle_simple_irq);
2694                 set_irq_flags(irq, IRQF_VALID);
2695         }
2696 }
2697
2698 static void __init init_prcm_registers(void)
2699 {
2700         u32 val;
2701
2702         val = readl(PRCM_A9PL_FORCE_CLKEN);
2703         val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
2704                 PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
2705         writel(val, (PRCM_A9PL_FORCE_CLKEN));
2706 }
2707
2708 /*
2709  * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
2710  */
2711 static struct regulator_consumer_supply db8500_vape_consumers[] = {
2712         REGULATOR_SUPPLY("v-ape", NULL),
2713         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
2714         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
2715         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
2716         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
2717         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"),
2718         /* "v-mmc" changed to "vcore" in the mainline kernel */
2719         REGULATOR_SUPPLY("vcore", "sdi0"),
2720         REGULATOR_SUPPLY("vcore", "sdi1"),
2721         REGULATOR_SUPPLY("vcore", "sdi2"),
2722         REGULATOR_SUPPLY("vcore", "sdi3"),
2723         REGULATOR_SUPPLY("vcore", "sdi4"),
2724         REGULATOR_SUPPLY("v-dma", "dma40.0"),
2725         REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
2726         /* "v-uart" changed to "vcore" in the mainline kernel */
2727         REGULATOR_SUPPLY("vcore", "uart0"),
2728         REGULATOR_SUPPLY("vcore", "uart1"),
2729         REGULATOR_SUPPLY("vcore", "uart2"),
2730         REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
2731         REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
2732         REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
2733 };
2734
2735 static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
2736         REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
2737         /* AV8100 regulator */
2738         REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
2739 };
2740
2741 static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
2742         REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
2743         REGULATOR_SUPPLY("vsupply", "mcde"),
2744 };
2745
2746 /* SVA MMDSP regulator switch */
2747 static struct regulator_consumer_supply db8500_svammdsp_consumers[] = {
2748         REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
2749 };
2750
2751 /* SVA pipe regulator switch */
2752 static struct regulator_consumer_supply db8500_svapipe_consumers[] = {
2753         REGULATOR_SUPPLY("sva-pipe", "cm_control"),
2754 };
2755
2756 /* SIA MMDSP regulator switch */
2757 static struct regulator_consumer_supply db8500_siammdsp_consumers[] = {
2758         REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
2759 };
2760
2761 /* SIA pipe regulator switch */
2762 static struct regulator_consumer_supply db8500_siapipe_consumers[] = {
2763         REGULATOR_SUPPLY("sia-pipe", "cm_control"),
2764 };
2765
2766 static struct regulator_consumer_supply db8500_sga_consumers[] = {
2767         REGULATOR_SUPPLY("v-mali", NULL),
2768 };
2769
2770 /* ESRAM1 and 2 regulator switch */
2771 static struct regulator_consumer_supply db8500_esram12_consumers[] = {
2772         REGULATOR_SUPPLY("esram12", "cm_control"),
2773 };
2774
2775 /* ESRAM3 and 4 regulator switch */
2776 static struct regulator_consumer_supply db8500_esram34_consumers[] = {
2777         REGULATOR_SUPPLY("v-esram34", "mcde"),
2778         REGULATOR_SUPPLY("esram34", "cm_control"),
2779         REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
2780 };
2781
2782 static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
2783         [DB8500_REGULATOR_VAPE] = {
2784                 .constraints = {
2785                         .name = "db8500-vape",
2786                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2787                         .always_on = true,
2788                 },
2789                 .consumer_supplies = db8500_vape_consumers,
2790                 .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
2791         },
2792         [DB8500_REGULATOR_VARM] = {
2793                 .constraints = {
2794                         .name = "db8500-varm",
2795                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2796                 },
2797         },
2798         [DB8500_REGULATOR_VMODEM] = {
2799                 .constraints = {
2800                         .name = "db8500-vmodem",
2801                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2802                 },
2803         },
2804         [DB8500_REGULATOR_VPLL] = {
2805                 .constraints = {
2806                         .name = "db8500-vpll",
2807                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2808                 },
2809         },
2810         [DB8500_REGULATOR_VSMPS1] = {
2811                 .constraints = {
2812                         .name = "db8500-vsmps1",
2813                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2814                 },
2815         },
2816         [DB8500_REGULATOR_VSMPS2] = {
2817                 .constraints = {
2818                         .name = "db8500-vsmps2",
2819                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2820                 },
2821                 .consumer_supplies = db8500_vsmps2_consumers,
2822                 .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
2823         },
2824         [DB8500_REGULATOR_VSMPS3] = {
2825                 .constraints = {
2826                         .name = "db8500-vsmps3",
2827                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2828                 },
2829         },
2830         [DB8500_REGULATOR_VRF1] = {
2831                 .constraints = {
2832                         .name = "db8500-vrf1",
2833                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2834                 },
2835         },
2836         [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
2837                 /* dependency to u8500-vape is handled outside regulator framework */
2838                 .constraints = {
2839                         .name = "db8500-sva-mmdsp",
2840                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2841                 },
2842                 .consumer_supplies = db8500_svammdsp_consumers,
2843                 .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers),
2844         },
2845         [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
2846                 .constraints = {
2847                         /* "ret" means "retention" */
2848                         .name = "db8500-sva-mmdsp-ret",
2849                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2850                 },
2851         },
2852         [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
2853                 /* dependency to u8500-vape is handled outside regulator framework */
2854                 .constraints = {
2855                         .name = "db8500-sva-pipe",
2856                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2857                 },
2858                 .consumer_supplies = db8500_svapipe_consumers,
2859                 .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers),
2860         },
2861         [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
2862                 /* dependency to u8500-vape is handled outside regulator framework */
2863                 .constraints = {
2864                         .name = "db8500-sia-mmdsp",
2865                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2866                 },
2867                 .consumer_supplies = db8500_siammdsp_consumers,
2868                 .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers),
2869         },
2870         [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
2871                 .constraints = {
2872                         .name = "db8500-sia-mmdsp-ret",
2873                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2874                 },
2875         },
2876         [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
2877                 /* dependency to u8500-vape is handled outside regulator framework */
2878                 .constraints = {
2879                         .name = "db8500-sia-pipe",
2880                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2881                 },
2882                 .consumer_supplies = db8500_siapipe_consumers,
2883                 .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers),
2884         },
2885         [DB8500_REGULATOR_SWITCH_SGA] = {
2886                 .supply_regulator = "db8500-vape",
2887                 .constraints = {
2888                         .name = "db8500-sga",
2889                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2890                 },
2891                 .consumer_supplies = db8500_sga_consumers,
2892                 .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers),
2893
2894         },
2895         [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
2896                 .supply_regulator = "db8500-vape",
2897                 .constraints = {
2898                         .name = "db8500-b2r2-mcde",
2899                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2900                 },
2901                 .consumer_supplies = db8500_b2r2_mcde_consumers,
2902                 .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
2903         },
2904         [DB8500_REGULATOR_SWITCH_ESRAM12] = {
2905                 /*
2906                  * esram12 is set in retention and supplied by Vsafe when Vape is off,
2907                  * no need to hold Vape
2908                  */
2909                 .constraints = {
2910                         .name = "db8500-esram12",
2911                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2912                 },
2913                 .consumer_supplies = db8500_esram12_consumers,
2914                 .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers),
2915         },
2916         [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
2917                 .constraints = {
2918                         .name = "db8500-esram12-ret",
2919                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2920                 },
2921         },
2922         [DB8500_REGULATOR_SWITCH_ESRAM34] = {
2923                 /*
2924                  * esram34 is set in retention and supplied by Vsafe when Vape is off,
2925                  * no need to hold Vape
2926                  */
2927                 .constraints = {
2928                         .name = "db8500-esram34",
2929                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2930                 },
2931                 .consumer_supplies = db8500_esram34_consumers,
2932                 .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers),
2933         },
2934         [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
2935                 .constraints = {
2936                         .name = "db8500-esram34-ret",
2937                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2938                 },
2939         },
2940 };
2941
2942 static struct resource ab8500_resources[] = {
2943         [0] = {
2944                 .start  = IRQ_DB8500_AB8500,
2945                 .end    = IRQ_DB8500_AB8500,
2946                 .flags  = IORESOURCE_IRQ
2947         }
2948 };
2949
2950 static struct mfd_cell db8500_prcmu_devs[] = {
2951         {
2952                 .name = "db8500-prcmu-regulators",
2953                 .of_compatible = "stericsson,db8500-prcmu-regulator",
2954                 .platform_data = &db8500_regulators,
2955                 .pdata_size = sizeof(db8500_regulators),
2956         },
2957         {
2958                 .name = "cpufreq-u8500",
2959                 .of_compatible = "stericsson,cpufreq-u8500",
2960         },
2961         {
2962                 .name = "ab8500-core",
2963                 .of_compatible = "stericsson,ab8500",
2964                 .num_resources = ARRAY_SIZE(ab8500_resources),
2965                 .resources = ab8500_resources,
2966                 .id = AB8500_VERSION_AB8500,
2967         },
2968 };
2969
2970 /**
2971  * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
2972  *
2973  */
2974 static int __devinit db8500_prcmu_probe(struct platform_device *pdev)
2975 {
2976         struct ab8500_platform_data *ab8500_platdata = pdev->dev.platform_data;
2977         struct device_node *np = pdev->dev.of_node;
2978         int irq = 0, err = 0, i;
2979
2980         if (ux500_is_svp())
2981                 return -ENODEV;
2982
2983         init_prcm_registers();
2984
2985         /* Clean up the mailbox interrupts after pre-kernel code. */
2986         writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
2987
2988         if (np)
2989                 irq = platform_get_irq(pdev, 0);
2990
2991         if (!np || irq <= 0)
2992                 irq = IRQ_DB8500_PRCMU1;
2993
2994         err = request_threaded_irq(irq, prcmu_irq_handler,
2995                 prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
2996         if (err < 0) {
2997                 pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
2998                 err = -EBUSY;
2999                 goto no_irq_return;
3000         }
3001
3002         for (i = 0; i < ARRAY_SIZE(db8500_prcmu_devs); i++) {
3003                 if (!strcmp(db8500_prcmu_devs[i].name, "ab8500-core")) {
3004                         db8500_prcmu_devs[i].platform_data = ab8500_platdata;
3005                         db8500_prcmu_devs[i].pdata_size = sizeof(struct ab8500_platform_data);
3006                 }
3007         }
3008
3009         if (cpu_is_u8500v20_or_later())
3010                 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
3011
3012         err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
3013                         ARRAY_SIZE(db8500_prcmu_devs), NULL, 0);
3014         if (err) {
3015                 pr_err("prcmu: Failed to add subdevices\n");
3016                 return err;
3017         }
3018
3019         pr_info("DB8500 PRCMU initialized\n");
3020
3021 no_irq_return:
3022         return err;
3023 }
3024 static const struct of_device_id db8500_prcmu_match[] = {
3025         { .compatible = "stericsson,db8500-prcmu"},
3026         { },
3027 };
3028
3029 static struct platform_driver db8500_prcmu_driver = {
3030         .driver = {
3031                 .name = "db8500-prcmu",
3032                 .owner = THIS_MODULE,
3033                 .of_match_table = db8500_prcmu_match,
3034         },
3035         .probe = db8500_prcmu_probe,
3036 };
3037
3038 static int __init db8500_prcmu_init(void)
3039 {
3040         return platform_driver_register(&db8500_prcmu_driver);
3041 }
3042
3043 core_initcall(db8500_prcmu_init);
3044
3045 MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>");
3046 MODULE_DESCRIPTION("DB8500 PRCM Unit driver");
3047 MODULE_LICENSE("GPL v2");