drivers/mfd/cs42l43.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * CS42L43 core driver
   4  *
   5  * Copyright (C) 2022-2023 Cirrus Logic, Inc. and
   6  *                         Cirrus Logic International Semiconductor Ltd.
   7  */
   8
   9 #include <linux/bitops.h>
  10 #include <linux/build_bug.h>
  11 #include <linux/delay.h>
  12 #include <linux/err.h>
  13 #include <linux/errno.h>
  14 #include <linux/firmware.h>
  15 #include <linux/jiffies.h>
  16 #include <linux/mfd/core.h>
  17 #include <linux/mfd/cs42l43-regs.h>
  18 #include <linux/module.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/soundwire/sdw.h>
  21
  22 #include "cs42l43.h"
  23
  24 #define CS42L43_RESET_DELAY                     20
  25
  26 #define CS42L43_SDW_ATTACH_TIMEOUT              500
  27 #define CS42L43_SDW_DETACH_TIMEOUT              100
  28
  29 #define CS42L43_MCU_BOOT_STAGE1                 1
  30 #define CS42L43_MCU_BOOT_STAGE2                 2
  31 #define CS42L43_MCU_BOOT_STAGE3                 3
  32 #define CS42L43_MCU_BOOT_STAGE4                 4
  33 #define CS42L43_MCU_POLL                        5000
  34 #define CS42L43_MCU_CMD_TIMEOUT                 20000
  35 #define CS42L43_MCU_UPDATE_FORMAT               3
  36 #define CS42L43_MCU_UPDATE_OFFSET               0x100000
  37 #define CS42L43_MCU_UPDATE_TIMEOUT              500000
  38 #define CS42L43_MCU_UPDATE_RETRIES              5
  39
  40 #define CS42L43_MCU_SUPPORTED_REV               0x2105
  41 #define CS42L43_MCU_SHADOW_REGS_REQUIRED_REV    0x2200
  42 #define CS42L43_MCU_SUPPORTED_BIOS_REV          0x0001
  43
  44 #define CS42L43_VDDP_DELAY                      50
  45 #define CS42L43_VDDD_DELAY                      1000
  46
  47 #define CS42L43_AUTOSUSPEND_TIME                250
  48
  49 struct cs42l43_patch_header {
  50         __le16 version;
  51         __le16 size;
  52         u8 reserved;
  53         u8 secure;
  54         __le16 bss_size;
  55         __le32 apply_addr;
  56         __le32 checksum;
  57         __le32 sha;
  58         __le16 swrev;
  59         __le16 patchid;
  60         __le16 ipxid;
  61         __le16 romver;
  62         __le32 load_addr;
  63 } __packed;
  64
  65 static const struct reg_sequence cs42l43_reva_patch[] = {
  66         { 0x4000,                                       0x00000055 },
  67         { 0x4000,                                       0x000000AA },
  68         { 0x10084,                                      0x00000000 },
  69         { 0x1741C,                                      0x00CD2000 },
  70         { 0x1718C,                                      0x00000003 },
  71         { 0x4000,                                       0x00000000 },
  72         { CS42L43_CCM_BLK_CLK_CONTROL,                  0x00000002 },
  73         { CS42L43_HPPATHVOL,                            0x011B011B },
  74         { CS42L43_OSC_DIV_SEL,                          0x00000001 },
  75         { CS42L43_DACCNFG2,                             0x00000005 },
  76         { CS42L43_MIC_DETECT_CONTROL_ANDROID,           0x80790079 },
  77         { CS42L43_RELID,                                0x0000000F },
  78 };
  79
  80 const struct reg_default cs42l43_reg_default[CS42L43_N_DEFAULTS] = {
  81         { CS42L43_DRV_CTRL1,                            0x000186C0 },
  82         { CS42L43_DRV_CTRL3,                            0x286DB018 },
  83         { CS42L43_DRV_CTRL4,                            0x000006D8 },
  84         { CS42L43_DRV_CTRL_5,                           0x136C00C0 },
  85         { CS42L43_GPIO_CTRL1,                           0x00000707 },
  86         { CS42L43_GPIO_CTRL2,                           0x00000000 },
  87         { CS42L43_GPIO_FN_SEL,                          0x00000000 },
  88         { CS42L43_MCLK_SRC_SEL,                         0x00000000 },
  89         { CS42L43_SAMPLE_RATE1,                         0x00000003 },
  90         { CS42L43_SAMPLE_RATE2,                         0x00000003 },
  91         { CS42L43_SAMPLE_RATE3,                         0x00000003 },
  92         { CS42L43_SAMPLE_RATE4,                         0x00000003 },
  93         { CS42L43_PLL_CONTROL,                          0x00000000 },
  94         { CS42L43_FS_SELECT1,                           0x00000000 },
  95         { CS42L43_FS_SELECT2,                           0x00000000 },
  96         { CS42L43_FS_SELECT3,                           0x00000000 },
  97         { CS42L43_FS_SELECT4,                           0x00000000 },
  98         { CS42L43_PDM_CONTROL,                          0x00000000 },
  99         { CS42L43_ASP_CLK_CONFIG1,                      0x00010001 },
 100         { CS42L43_ASP_CLK_CONFIG2,                      0x00000000 },
 101         { CS42L43_OSC_DIV_SEL,                          0x00000001 },
 102         { CS42L43_ADC_B_CTRL1,                          0x00000000 },
 103         { CS42L43_ADC_B_CTRL2,                          0x00000000 },
 104         { CS42L43_DECIM_HPF_WNF_CTRL1,                  0x00000001 },
 105         { CS42L43_DECIM_HPF_WNF_CTRL2,                  0x00000001 },
 106         { CS42L43_DECIM_HPF_WNF_CTRL3,                  0x00000001 },
 107         { CS42L43_DECIM_HPF_WNF_CTRL4,                  0x00000001 },
 108         { CS42L43_DMIC_PDM_CTRL,                        0x00000000 },
 109         { CS42L43_DECIM_VOL_CTRL_CH1_CH2,               0x20122012 },
 110         { CS42L43_DECIM_VOL_CTRL_CH3_CH4,               0x20122012 },
 111         { CS42L43_INTP_VOLUME_CTRL1,                    0x00000180 },
 112         { CS42L43_INTP_VOLUME_CTRL2,                    0x00000180 },
 113         { CS42L43_AMP1_2_VOL_RAMP,                      0x00000022 },
 114         { CS42L43_ASP_CTRL,                             0x00000004 },
 115         { CS42L43_ASP_FSYNC_CTRL1,                      0x000000FA },
 116         { CS42L43_ASP_FSYNC_CTRL2,                      0x00000001 },
 117         { CS42L43_ASP_FSYNC_CTRL3,                      0x00000000 },
 118         { CS42L43_ASP_FSYNC_CTRL4,                      0x000001F4 },
 119         { CS42L43_ASP_DATA_CTRL,                        0x0000003A },
 120         { CS42L43_ASP_RX_EN,                            0x00000000 },
 121         { CS42L43_ASP_TX_EN,                            0x00000000 },
 122         { CS42L43_ASP_RX_CH1_CTRL,                      0x00170001 },
 123         { CS42L43_ASP_RX_CH2_CTRL,                      0x00170031 },
 124         { CS42L43_ASP_RX_CH3_CTRL,                      0x00170061 },
 125         { CS42L43_ASP_RX_CH4_CTRL,                      0x00170091 },
 126         { CS42L43_ASP_RX_CH5_CTRL,                      0x001700C1 },
 127         { CS42L43_ASP_RX_CH6_CTRL,                      0x001700F1 },
 128         { CS42L43_ASP_TX_CH1_CTRL,                      0x00170001 },
 129         { CS42L43_ASP_TX_CH2_CTRL,                      0x00170031 },
 130         { CS42L43_ASP_TX_CH3_CTRL,                      0x00170061 },
 131         { CS42L43_ASP_TX_CH4_CTRL,                      0x00170091 },
 132         { CS42L43_ASP_TX_CH5_CTRL,                      0x001700C1 },
 133         { CS42L43_ASP_TX_CH6_CTRL,                      0x001700F1 },
 134         { CS42L43_ASPTX1_INPUT,                         0x00800000 },
 135         { CS42L43_ASPTX2_INPUT,                         0x00800000 },
 136         { CS42L43_ASPTX3_INPUT,                         0x00800000 },
 137         { CS42L43_ASPTX4_INPUT,                         0x00800000 },
 138         { CS42L43_ASPTX5_INPUT,                         0x00800000 },
 139         { CS42L43_ASPTX6_INPUT,                         0x00800000 },
 140         { CS42L43_SWIRE_DP1_CH1_INPUT,                  0x00800000 },
 141         { CS42L43_SWIRE_DP1_CH2_INPUT,                  0x00800000 },
 142         { CS42L43_SWIRE_DP1_CH3_INPUT,                  0x00800000 },
 143         { CS42L43_SWIRE_DP1_CH4_INPUT,                  0x00800000 },
 144         { CS42L43_SWIRE_DP2_CH1_INPUT,                  0x00800000 },
 145         { CS42L43_SWIRE_DP2_CH2_INPUT,                  0x00800000 },
 146         { CS42L43_SWIRE_DP3_CH1_INPUT,                  0x00800000 },
 147         { CS42L43_SWIRE_DP3_CH2_INPUT,                  0x00800000 },
 148         { CS42L43_SWIRE_DP4_CH1_INPUT,                  0x00800000 },
 149         { CS42L43_SWIRE_DP4_CH2_INPUT,                  0x00800000 },
 150         { CS42L43_ASRC_INT1_INPUT1,                     0x00800000 },
 151         { CS42L43_ASRC_INT2_INPUT1,                     0x00800000 },
 152         { CS42L43_ASRC_INT3_INPUT1,                     0x00800000 },
 153         { CS42L43_ASRC_INT4_INPUT1,                     0x00800000 },
 154         { CS42L43_ASRC_DEC1_INPUT1,                     0x00800000 },
 155         { CS42L43_ASRC_DEC2_INPUT1,                     0x00800000 },
 156         { CS42L43_ASRC_DEC3_INPUT1,                     0x00800000 },
 157         { CS42L43_ASRC_DEC4_INPUT1,                     0x00800000 },
 158         { CS42L43_ISRC1INT1_INPUT1,                     0x00800000 },
 159         { CS42L43_ISRC1INT2_INPUT1,                     0x00800000 },
 160         { CS42L43_ISRC1DEC1_INPUT1,                     0x00800000 },
 161         { CS42L43_ISRC1DEC2_INPUT1,                     0x00800000 },
 162         { CS42L43_ISRC2INT1_INPUT1,                     0x00800000 },
 163         { CS42L43_ISRC2INT2_INPUT1,                     0x00800000 },
 164         { CS42L43_ISRC2DEC1_INPUT1,                     0x00800000 },
 165         { CS42L43_ISRC2DEC2_INPUT1,                     0x00800000 },
 166         { CS42L43_EQ1MIX_INPUT1,                        0x00800000 },
 167         { CS42L43_EQ1MIX_INPUT2,                        0x00800000 },
 168         { CS42L43_EQ1MIX_INPUT3,                        0x00800000 },
 169         { CS42L43_EQ1MIX_INPUT4,                        0x00800000 },
 170         { CS42L43_EQ2MIX_INPUT1,                        0x00800000 },
 171         { CS42L43_EQ2MIX_INPUT2,                        0x00800000 },
 172         { CS42L43_EQ2MIX_INPUT3,                        0x00800000 },
 173         { CS42L43_EQ2MIX_INPUT4,                        0x00800000 },
 174         { CS42L43_SPDIF1_INPUT1,                        0x00800000 },
 175         { CS42L43_SPDIF2_INPUT1,                        0x00800000 },
 176         { CS42L43_AMP1MIX_INPUT1,                       0x00800000 },
 177         { CS42L43_AMP1MIX_INPUT2,                       0x00800000 },
 178         { CS42L43_AMP1MIX_INPUT3,                       0x00800000 },
 179         { CS42L43_AMP1MIX_INPUT4,                       0x00800000 },
 180         { CS42L43_AMP2MIX_INPUT1,                       0x00800000 },
 181         { CS42L43_AMP2MIX_INPUT2,                       0x00800000 },
 182         { CS42L43_AMP2MIX_INPUT3,                       0x00800000 },
 183         { CS42L43_AMP2MIX_INPUT4,                       0x00800000 },
 184         { CS42L43_AMP3MIX_INPUT1,                       0x00800000 },
 185         { CS42L43_AMP3MIX_INPUT2,                       0x00800000 },
 186         { CS42L43_AMP3MIX_INPUT3,                       0x00800000 },
 187         { CS42L43_AMP3MIX_INPUT4,                       0x00800000 },
 188         { CS42L43_AMP4MIX_INPUT1,                       0x00800000 },
 189         { CS42L43_AMP4MIX_INPUT2,                       0x00800000 },
 190         { CS42L43_AMP4MIX_INPUT3,                       0x00800000 },
 191         { CS42L43_AMP4MIX_INPUT4,                       0x00800000 },
 192         { CS42L43_ASRC_INT_ENABLES,                     0x00000100 },
 193         { CS42L43_ASRC_DEC_ENABLES,                     0x00000100 },
 194         { CS42L43_PDNCNTL,                              0x00000000 },
 195         { CS42L43_RINGSENSE_DEB_CTRL,                   0x0000001B },
 196         { CS42L43_TIPSENSE_DEB_CTRL,                    0x0000001B },
 197         { CS42L43_HS2,                                  0x050106F3 },
 198         { CS42L43_STEREO_MIC_CTRL,                      0x00000000 },
 199         { CS42L43_STEREO_MIC_CLAMP_CTRL,                0x00000001 },
 200         { CS42L43_BLOCK_EN2,                            0x00000000 },
 201         { CS42L43_BLOCK_EN3,                            0x00000000 },
 202         { CS42L43_BLOCK_EN4,                            0x00000000 },
 203         { CS42L43_BLOCK_EN5,                            0x00000000 },
 204         { CS42L43_BLOCK_EN6,                            0x00000000 },
 205         { CS42L43_BLOCK_EN7,                            0x00000000 },
 206         { CS42L43_BLOCK_EN8,                            0x00000000 },
 207         { CS42L43_BLOCK_EN9,                            0x00000000 },
 208         { CS42L43_BLOCK_EN10,                           0x00000000 },
 209         { CS42L43_BLOCK_EN11,                           0x00000000 },
 210         { CS42L43_TONE_CH1_CTRL,                        0x00000000 },
 211         { CS42L43_TONE_CH2_CTRL,                        0x00000000 },
 212         { CS42L43_MIC_DETECT_CONTROL_1,                 0x00000003 },
 213         { CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL,  0x02000003 },
 214         { CS42L43_MIC_DETECT_CONTROL_ANDROID,           0x80790079 },
 215         { CS42L43_ISRC1_CTRL,                           0x00000000 },
 216         { CS42L43_ISRC2_CTRL,                           0x00000000 },
 217         { CS42L43_CTRL_REG,                             0x00000006 },
 218         { CS42L43_FDIV_FRAC,                            0x40000000 },
 219         { CS42L43_CAL_RATIO,                            0x00000080 },
 220         { CS42L43_SPI_CLK_CONFIG1,                      0x00000000 },
 221         { CS42L43_SPI_CONFIG1,                          0x00000000 },
 222         { CS42L43_SPI_CONFIG2,                          0x00000000 },
 223         { CS42L43_SPI_CONFIG3,                          0x00000001 },
 224         { CS42L43_SPI_CONFIG4,                          0x00000000 },
 225         { CS42L43_TRAN_CONFIG3,                         0x00000000 },
 226         { CS42L43_TRAN_CONFIG4,                         0x00000000 },
 227         { CS42L43_TRAN_CONFIG5,                         0x00000000 },
 228         { CS42L43_TRAN_CONFIG6,                         0x00000000 },
 229         { CS42L43_TRAN_CONFIG7,                         0x00000000 },
 230         { CS42L43_TRAN_CONFIG8,                         0x00000000 },
 231         { CS42L43_DACCNFG1,                             0x00000008 },
 232         { CS42L43_DACCNFG2,                             0x00000005 },
 233         { CS42L43_HPPATHVOL,                            0x011B011B },
 234         { CS42L43_PGAVOL,                               0x00003470 },
 235         { CS42L43_LOADDETENA,                           0x00000000 },
 236         { CS42L43_CTRL,                                 0x00000037 },
 237         { CS42L43_COEFF_DATA_IN0,                       0x00000000 },
 238         { CS42L43_COEFF_RD_WR0,                         0x00000000 },
 239         { CS42L43_START_EQZ0,                           0x00000000 },
 240         { CS42L43_MUTE_EQ_IN0,                          0x00000000 },
 241         { CS42L43_DECIM_MASK,                           0x0000000F },
 242         { CS42L43_EQ_MIX_MASK,                          0x0000000F },
 243         { CS42L43_ASP_MASK,                             0x000000FF },
 244         { CS42L43_PLL_MASK,                             0x00000003 },
 245         { CS42L43_SOFT_MASK,                            0x0000FFFF },
 246         { CS42L43_SWIRE_MASK,                           0x00007FFF },
 247         { CS42L43_MSM_MASK,                             0x00000FFF },
 248         { CS42L43_ACC_DET_MASK,                         0x00000FFF },
 249         { CS42L43_I2C_TGT_MASK,                         0x00000003 },
 250         { CS42L43_SPI_MSTR_MASK,                        0x00000007 },
 251         { CS42L43_SW_TO_SPI_BRIDGE_MASK,                0x00000001 },
 252         { CS42L43_OTP_MASK,                             0x00000007 },
 253         { CS42L43_CLASS_D_AMP_MASK,                     0x00003FFF },
 254         { CS42L43_GPIO_INT_MASK,                        0x0000003F },
 255         { CS42L43_ASRC_MASK,                            0x0000000F },
 256         { CS42L43_HPOUT_MASK,                           0x00000003 },
 257 };
 258 EXPORT_SYMBOL_NS_GPL(cs42l43_reg_default, MFD_CS42L43);
 259
 260 bool cs42l43_readable_register(struct device *dev, unsigned int reg)
 261 {
 262         switch (reg) {
 263         case CS42L43_DEVID:
 264         case CS42L43_REVID:
 265         case CS42L43_RELID:
 266         case CS42L43_SFT_RESET:
 267         case CS42L43_DRV_CTRL1:
 268         case CS42L43_DRV_CTRL3:
 269         case CS42L43_DRV_CTRL4:
 270         case CS42L43_DRV_CTRL_5:
 271         case CS42L43_GPIO_CTRL1:
 272         case CS42L43_GPIO_CTRL2:
 273         case CS42L43_GPIO_STS:
 274         case CS42L43_GPIO_FN_SEL:
 275         case CS42L43_MCLK_SRC_SEL:
 276         case CS42L43_SAMPLE_RATE1 ... CS42L43_SAMPLE_RATE4:
 277         case CS42L43_PLL_CONTROL:
 278         case CS42L43_FS_SELECT1 ... CS42L43_FS_SELECT4:
 279         case CS42L43_PDM_CONTROL:
 280         case CS42L43_ASP_CLK_CONFIG1 ... CS42L43_ASP_CLK_CONFIG2:
 281         case CS42L43_OSC_DIV_SEL:
 282         case CS42L43_ADC_B_CTRL1 ...  CS42L43_ADC_B_CTRL2:
 283         case CS42L43_DECIM_HPF_WNF_CTRL1 ... CS42L43_DECIM_HPF_WNF_CTRL4:
 284         case CS42L43_DMIC_PDM_CTRL:
 285         case CS42L43_DECIM_VOL_CTRL_CH1_CH2 ... CS42L43_DECIM_VOL_CTRL_CH3_CH4:
 286         case CS42L43_INTP_VOLUME_CTRL1 ... CS42L43_INTP_VOLUME_CTRL2:
 287         case CS42L43_AMP1_2_VOL_RAMP:
 288         case CS42L43_ASP_CTRL:
 289         case CS42L43_ASP_FSYNC_CTRL1 ... CS42L43_ASP_FSYNC_CTRL4:
 290         case CS42L43_ASP_DATA_CTRL:
 291         case CS42L43_ASP_RX_EN ... CS42L43_ASP_TX_EN:
 292         case CS42L43_ASP_RX_CH1_CTRL ... CS42L43_ASP_RX_CH6_CTRL:
 293         case CS42L43_ASP_TX_CH1_CTRL ... CS42L43_ASP_TX_CH6_CTRL:
 294         case CS42L43_OTP_REVISION_ID:
 295         case CS42L43_ASPTX1_INPUT:
 296         case CS42L43_ASPTX2_INPUT:
 297         case CS42L43_ASPTX3_INPUT:
 298         case CS42L43_ASPTX4_INPUT:
 299         case CS42L43_ASPTX5_INPUT:
 300         case CS42L43_ASPTX6_INPUT:
 301         case CS42L43_SWIRE_DP1_CH1_INPUT:
 302         case CS42L43_SWIRE_DP1_CH2_INPUT:
 303         case CS42L43_SWIRE_DP1_CH3_INPUT:
 304         case CS42L43_SWIRE_DP1_CH4_INPUT:
 305         case CS42L43_SWIRE_DP2_CH1_INPUT:
 306         case CS42L43_SWIRE_DP2_CH2_INPUT:
 307         case CS42L43_SWIRE_DP3_CH1_INPUT:
 308         case CS42L43_SWIRE_DP3_CH2_INPUT:
 309         case CS42L43_SWIRE_DP4_CH1_INPUT:
 310         case CS42L43_SWIRE_DP4_CH2_INPUT:
 311         case CS42L43_ASRC_INT1_INPUT1:
 312         case CS42L43_ASRC_INT2_INPUT1:
 313         case CS42L43_ASRC_INT3_INPUT1:
 314         case CS42L43_ASRC_INT4_INPUT1:
 315         case CS42L43_ASRC_DEC1_INPUT1:
 316         case CS42L43_ASRC_DEC2_INPUT1:
 317         case CS42L43_ASRC_DEC3_INPUT1:
 318         case CS42L43_ASRC_DEC4_INPUT1:
 319         case CS42L43_ISRC1INT1_INPUT1:
 320         case CS42L43_ISRC1INT2_INPUT1:
 321         case CS42L43_ISRC1DEC1_INPUT1:
 322         case CS42L43_ISRC1DEC2_INPUT1:
 323         case CS42L43_ISRC2INT1_INPUT1:
 324         case CS42L43_ISRC2INT2_INPUT1:
 325         case CS42L43_ISRC2DEC1_INPUT1:
 326         case CS42L43_ISRC2DEC2_INPUT1:
 327         case CS42L43_EQ1MIX_INPUT1 ... CS42L43_EQ1MIX_INPUT4:
 328         case CS42L43_EQ2MIX_INPUT1 ... CS42L43_EQ2MIX_INPUT4:
 329         case CS42L43_SPDIF1_INPUT1:
 330         case CS42L43_SPDIF2_INPUT1:
 331         case CS42L43_AMP1MIX_INPUT1 ... CS42L43_AMP1MIX_INPUT4:
 332         case CS42L43_AMP2MIX_INPUT1 ... CS42L43_AMP2MIX_INPUT4:
 333         case CS42L43_AMP3MIX_INPUT1 ... CS42L43_AMP3MIX_INPUT4:
 334         case CS42L43_AMP4MIX_INPUT1 ... CS42L43_AMP4MIX_INPUT4:
 335         case CS42L43_ASRC_INT_ENABLES ... CS42L43_ASRC_DEC_ENABLES:
 336         case CS42L43_PDNCNTL:
 337         case CS42L43_RINGSENSE_DEB_CTRL:
 338         case CS42L43_TIPSENSE_DEB_CTRL:
 339         case CS42L43_TIP_RING_SENSE_INTERRUPT_STATUS:
 340         case CS42L43_HS2:
 341         case CS42L43_HS_STAT:
 342         case CS42L43_MCU_SW_INTERRUPT:
 343         case CS42L43_STEREO_MIC_CTRL:
 344         case CS42L43_STEREO_MIC_CLAMP_CTRL:
 345         case CS42L43_BLOCK_EN2 ... CS42L43_BLOCK_EN11:
 346         case CS42L43_TONE_CH1_CTRL ... CS42L43_TONE_CH2_CTRL:
 347         case CS42L43_MIC_DETECT_CONTROL_1:
 348         case CS42L43_DETECT_STATUS_1:
 349         case CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL:
 350         case CS42L43_MIC_DETECT_CONTROL_ANDROID:
 351         case CS42L43_ISRC1_CTRL:
 352         case CS42L43_ISRC2_CTRL:
 353         case CS42L43_CTRL_REG:
 354         case CS42L43_FDIV_FRAC:
 355         case CS42L43_CAL_RATIO:
 356         case CS42L43_SPI_CLK_CONFIG1:
 357         case CS42L43_SPI_CONFIG1 ... CS42L43_SPI_CONFIG4:
 358         case CS42L43_SPI_STATUS1 ... CS42L43_SPI_STATUS2:
 359         case CS42L43_TRAN_CONFIG1 ... CS42L43_TRAN_CONFIG8:
 360         case CS42L43_TRAN_STATUS1 ... CS42L43_TRAN_STATUS3:
 361         case CS42L43_TX_DATA:
 362         case CS42L43_RX_DATA:
 363         case CS42L43_DACCNFG1 ... CS42L43_DACCNFG2:
 364         case CS42L43_HPPATHVOL:
 365         case CS42L43_PGAVOL:
 366         case CS42L43_LOADDETRESULTS:
 367         case CS42L43_LOADDETENA:
 368         case CS42L43_CTRL:
 369         case CS42L43_COEFF_DATA_IN0:
 370         case CS42L43_COEFF_RD_WR0:
 371         case CS42L43_INIT_DONE0:
 372         case CS42L43_START_EQZ0:
 373         case CS42L43_MUTE_EQ_IN0:
 374         case CS42L43_DECIM_INT ... CS42L43_HPOUT_INT:
 375         case CS42L43_DECIM_MASK ... CS42L43_HPOUT_MASK:
 376         case CS42L43_DECIM_INT_SHADOW ... CS42L43_HP_OUT_SHADOW:
 377         case CS42L43_BOOT_CONTROL:
 378         case CS42L43_BLOCK_EN:
 379         case CS42L43_SHUTTER_CONTROL:
 380         case CS42L43_MCU_SW_REV ... CS42L43_MCU_RAM_MAX:
 381                 return true;
 382         default:
 383                 return false;
 384         }
 385 }
 386 EXPORT_SYMBOL_NS_GPL(cs42l43_readable_register, MFD_CS42L43);
 387
 388 bool cs42l43_precious_register(struct device *dev, unsigned int reg)
 389 {
 390         switch (reg) {
 391         case CS42L43_SFT_RESET:
 392         case CS42L43_TX_DATA:
 393         case CS42L43_RX_DATA:
 394         case CS42L43_DECIM_INT ... CS42L43_HPOUT_INT:
 395         case CS42L43_MCU_SW_REV ... CS42L43_MCU_RAM_MAX:
 396                 return true;
 397         default:
 398                 return false;
 399         }
 400 }
 401 EXPORT_SYMBOL_NS_GPL(cs42l43_precious_register, MFD_CS42L43);
 402
 403 bool cs42l43_volatile_register(struct device *dev, unsigned int reg)
 404 {
 405         switch (reg) {
 406         case CS42L43_DEVID:
 407         case CS42L43_REVID:
 408         case CS42L43_RELID:
 409         case CS42L43_GPIO_STS:
 410         case CS42L43_OTP_REVISION_ID:
 411         case CS42L43_TIP_RING_SENSE_INTERRUPT_STATUS:
 412         case CS42L43_HS_STAT:
 413         case CS42L43_MCU_SW_INTERRUPT:
 414         case CS42L43_DETECT_STATUS_1:
 415         case CS42L43_SPI_STATUS1 ... CS42L43_SPI_STATUS2:
 416         case CS42L43_TRAN_CONFIG1 ... CS42L43_TRAN_CONFIG2:
 417         case CS42L43_TRAN_CONFIG8:
 418         case CS42L43_TRAN_STATUS1 ... CS42L43_TRAN_STATUS3:
 419         case CS42L43_LOADDETRESULTS:
 420         case CS42L43_INIT_DONE0:
 421         case CS42L43_DECIM_INT_SHADOW ... CS42L43_HP_OUT_SHADOW:
 422         case CS42L43_BOOT_CONTROL:
 423         case CS42L43_BLOCK_EN:
 424                 return true;
 425         default:
 426                 return cs42l43_precious_register(dev, reg);
 427         }
 428 }
 429 EXPORT_SYMBOL_NS_GPL(cs42l43_volatile_register, MFD_CS42L43);
 430
 431 #define CS42L43_IRQ_OFFSET(reg) ((CS42L43_##reg##_INT) - CS42L43_DECIM_INT)
 432
 433 #define CS42L43_IRQ_REG(name, reg) REGMAP_IRQ_REG(CS42L43_##name, \
 434                                                   CS42L43_IRQ_OFFSET(reg), \
 435                                                   CS42L43_##name##_INT_MASK)
 436
 437 static const struct regmap_irq cs42l43_regmap_irqs[] = {
 438         CS42L43_IRQ_REG(PLL_LOST_LOCK,                          PLL),
 439         CS42L43_IRQ_REG(PLL_READY,                              PLL),
 440
 441         CS42L43_IRQ_REG(HP_STARTUP_DONE,                        MSM),
 442         CS42L43_IRQ_REG(HP_SHUTDOWN_DONE,                       MSM),
 443         CS42L43_IRQ_REG(HSDET_DONE,                             MSM),
 444         CS42L43_IRQ_REG(TIPSENSE_UNPLUG_DB,                     MSM),
 445         CS42L43_IRQ_REG(TIPSENSE_PLUG_DB,                       MSM),
 446         CS42L43_IRQ_REG(RINGSENSE_UNPLUG_DB,                    MSM),
 447         CS42L43_IRQ_REG(RINGSENSE_PLUG_DB,                      MSM),
 448         CS42L43_IRQ_REG(TIPSENSE_UNPLUG_PDET,                   MSM),
 449         CS42L43_IRQ_REG(TIPSENSE_PLUG_PDET,                     MSM),
 450         CS42L43_IRQ_REG(RINGSENSE_UNPLUG_PDET,                  MSM),
 451         CS42L43_IRQ_REG(RINGSENSE_PLUG_PDET,                    MSM),
 452
 453         CS42L43_IRQ_REG(HS2_BIAS_SENSE,                         ACC_DET),
 454         CS42L43_IRQ_REG(HS1_BIAS_SENSE,                         ACC_DET),
 455         CS42L43_IRQ_REG(DC_DETECT1_FALSE,                       ACC_DET),
 456         CS42L43_IRQ_REG(DC_DETECT1_TRUE,                        ACC_DET),
 457         CS42L43_IRQ_REG(HSBIAS_CLAMPED,                         ACC_DET),
 458         CS42L43_IRQ_REG(HS3_4_BIAS_SENSE,                       ACC_DET),
 459
 460         CS42L43_IRQ_REG(AMP2_CLK_STOP_FAULT,                    CLASS_D_AMP),
 461         CS42L43_IRQ_REG(AMP1_CLK_STOP_FAULT,                    CLASS_D_AMP),
 462         CS42L43_IRQ_REG(AMP2_VDDSPK_FAULT,                      CLASS_D_AMP),
 463         CS42L43_IRQ_REG(AMP1_VDDSPK_FAULT,                      CLASS_D_AMP),
 464         CS42L43_IRQ_REG(AMP2_SHUTDOWN_DONE,                     CLASS_D_AMP),
 465         CS42L43_IRQ_REG(AMP1_SHUTDOWN_DONE,                     CLASS_D_AMP),
 466         CS42L43_IRQ_REG(AMP2_STARTUP_DONE,                      CLASS_D_AMP),
 467         CS42L43_IRQ_REG(AMP1_STARTUP_DONE,                      CLASS_D_AMP),
 468         CS42L43_IRQ_REG(AMP2_THERM_SHDN,                        CLASS_D_AMP),
 469         CS42L43_IRQ_REG(AMP1_THERM_SHDN,                        CLASS_D_AMP),
 470         CS42L43_IRQ_REG(AMP2_THERM_WARN,                        CLASS_D_AMP),
 471         CS42L43_IRQ_REG(AMP1_THERM_WARN,                        CLASS_D_AMP),
 472         CS42L43_IRQ_REG(AMP2_SCDET,                             CLASS_D_AMP),
 473         CS42L43_IRQ_REG(AMP1_SCDET,                             CLASS_D_AMP),
 474
 475         CS42L43_IRQ_REG(GPIO3_FALL,                             GPIO),
 476         CS42L43_IRQ_REG(GPIO3_RISE,                             GPIO),
 477         CS42L43_IRQ_REG(GPIO2_FALL,                             GPIO),
 478         CS42L43_IRQ_REG(GPIO2_RISE,                             GPIO),
 479         CS42L43_IRQ_REG(GPIO1_FALL,                             GPIO),
 480         CS42L43_IRQ_REG(GPIO1_RISE,                             GPIO),
 481
 482         CS42L43_IRQ_REG(HP_ILIMIT,                              HPOUT),
 483         CS42L43_IRQ_REG(HP_LOADDET_DONE,                        HPOUT),
 484 };
 485
 486 static const struct regmap_irq_chip cs42l43_irq_chip = {
 487         .name = "cs42l43",
 488
 489         .status_base = CS42L43_DECIM_INT,
 490         .mask_base = CS42L43_DECIM_MASK,
 491         .num_regs = 16,
 492
 493         .irqs = cs42l43_regmap_irqs,
 494         .num_irqs = ARRAY_SIZE(cs42l43_regmap_irqs),
 495
 496         .runtime_pm = true,
 497 };
 498
 499 static const char * const cs42l43_core_supplies[] = {
 500         "vdd-a", "vdd-io", "vdd-cp",
 501 };
 502
 503 static const char * const cs42l43_parent_supplies[] = { "vdd-amp" };
 504
 505 static const struct mfd_cell cs42l43_devs[] = {
 506         { .name = "cs42l43-pinctrl", },
 507         { .name = "cs42l43-spi", },
 508         {
 509                 .name = "cs42l43-codec",
 510                 .parent_supplies = cs42l43_parent_supplies,
 511                 .num_parent_supplies = ARRAY_SIZE(cs42l43_parent_supplies),
 512         },
 513 };
 514
 515 /*
 516  * If the device is connected over Soundwire, as well as soft resetting the
 517  * device, this function will also way for the device to detach from the bus
 518  * before returning.
 519  */
 520 static int cs42l43_soft_reset(struct cs42l43 *cs42l43)
 521 {
 522         static const struct reg_sequence reset[] = {
 523                 { CS42L43_SFT_RESET, CS42L43_SFT_RESET_VAL },
 524         };
 525
 526         reinit_completion(&cs42l43->device_detach);
 527
 528         /*
 529          * Apply cache only because the soft reset will cause the device to
 530          * detach from the soundwire bus.
 531          */
 532         regcache_cache_only(cs42l43->regmap, true);
 533         regmap_multi_reg_write_bypassed(cs42l43->regmap, reset, ARRAY_SIZE(reset));
 534
 535         msleep(CS42L43_RESET_DELAY);
 536
 537         if (cs42l43->sdw) {
 538                 unsigned long timeout = msecs_to_jiffies(CS42L43_SDW_DETACH_TIMEOUT);
 539                 unsigned long time;
 540
 541                 time = wait_for_completion_timeout(&cs42l43->device_detach, timeout);
 542                 if (!time) {
 543                         dev_err(cs42l43->dev, "Timed out waiting for device detach\n");
 544                         return -ETIMEDOUT;
 545                 }
 546         }
 547
 548         return -EAGAIN;
 549 }
 550
 551 /*
 552  * This function is essentially a no-op on I2C, but will wait for the device to
 553  * attach when the device is used on a SoundWire bus.
 554  */
 555 static int cs42l43_wait_for_attach(struct cs42l43 *cs42l43)
 556 {
 557         if (!cs42l43->attached) {
 558                 unsigned long timeout = msecs_to_jiffies(CS42L43_SDW_ATTACH_TIMEOUT);
 559                 unsigned long time;
 560
 561                 time = wait_for_completion_timeout(&cs42l43->device_attach, timeout);
 562                 if (!time) {
 563                         dev_err(cs42l43->dev, "Timed out waiting for device re-attach\n");
 564                         return -ETIMEDOUT;
 565                 }
 566         }
 567
 568         regcache_cache_only(cs42l43->regmap, false);
 569
 570         /* The hardware requires enabling OSC_DIV before doing any SoundWire reads. */
 571         if (cs42l43->sdw)
 572                 regmap_write(cs42l43->regmap, CS42L43_OSC_DIV_SEL,
 573                              CS42L43_OSC_DIV2_EN_MASK);
 574
 575         return 0;
 576 }
 577
 578 /*
 579  * This function will advance the firmware into boot stage 3 from boot stage 2.
 580  * Boot stage 3 is required to send commands to the firmware. This is achieved
 581  * by setting the firmware NEED configuration register to zero, this indicates
 582  * no configuration is required forcing the firmware to advance to boot stage 3.
 583  *
 584  * Later revisions of the firmware require the use of an alternative register
 585  * for this purpose, which is indicated through the shadow flag.
 586  */
 587 static int cs42l43_mcu_stage_2_3(struct cs42l43 *cs42l43, bool shadow)
 588 {
 589         unsigned int need_reg = CS42L43_NEED_CONFIGS;
 590         unsigned int val;
 591         int ret;
 592
 593         if (shadow)
 594                 need_reg = CS42L43_FW_SH_BOOT_CFG_NEED_CONFIGS;
 595
 596         regmap_write(cs42l43->regmap, need_reg, 0);
 597
 598         ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_BOOT_STATUS,
 599                                        val, (val == CS42L43_MCU_BOOT_STAGE3),
 600                                        CS42L43_MCU_POLL, CS42L43_MCU_CMD_TIMEOUT);
 601         if (ret) {
 602                 dev_err(cs42l43->dev, "Failed to move to stage 3: %d, 0x%x\n", ret, val);
 603                 return ret;
 604         }
 605
 606         return -EAGAIN;
 607 }
 608
 609 /*
 610  * This function will return the firmware to boot stage 2 from boot stage 3.
 611  * Boot stage 2 is required to apply updates to the firmware. This is achieved
 612  * by setting the firmware NEED configuration register to FW_PATCH_NEED_CFG,
 613  * setting the HAVE configuration register to 0, and soft resetting. The
 614  * firmware will see it is missing a patch configuration and will pause in boot
 615  * stage 2.
 616  *
 617  * Note: Unlike cs42l43_mcu_stage_2_3 there is no need to consider the shadow
 618  * register here as the driver will only return to boot stage 2 if the firmware
 619  * requires update which means the revision does not include shadow register
 620  * support.
 621  */
 622 static int cs42l43_mcu_stage_3_2(struct cs42l43 *cs42l43)
 623 {
 624         regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_NEED_CONFIGS,
 625                      CS42L43_FW_PATCH_NEED_CFG_MASK);
 626         regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_HAVE_CONFIGS, 0);
 627
 628         return cs42l43_soft_reset(cs42l43);
 629 }
 630
 631 /*
 632  * Disable the firmware running on the device such that the driver can access
 633  * the registers without fear of the MCU changing them under it.
 634  */
 635 static int cs42l43_mcu_disable(struct cs42l43 *cs42l43)
 636 {
 637         unsigned int val;
 638         int ret;
 639
 640         regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_REG,
 641                      CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_DISABLE_VAL);
 642         regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_MM_CTRL_SELECTION,
 643                      CS42L43_FW_MM_CTRL_MCU_SEL_MASK);
 644         regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, CS42L43_CONTROL_IND_MASK);
 645         regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, 0);
 646
 647         ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_SOFT_INT_SHADOW, val,
 648                                        (val & CS42L43_CONTROL_APPLIED_INT_MASK),
 649                                        CS42L43_MCU_POLL, CS42L43_MCU_CMD_TIMEOUT);
 650         if (ret) {
 651                 dev_err(cs42l43->dev, "Failed to disable firmware: %d, 0x%x\n", ret, val);
 652                 return ret;
 653         }
 654
 655         /* Soft reset to clear any register state the firmware left behind. */
 656         return cs42l43_soft_reset(cs42l43);
 657 }
 658
 659 /*
 660  * Callback to load firmware updates.
 661  */
 662 static void cs42l43_mcu_load_firmware(const struct firmware *firmware, void *context)
 663 {
 664         struct cs42l43 *cs42l43 = context;
 665         const struct cs42l43_patch_header *hdr;
 666         unsigned int loadaddr, val;
 667         int ret;
 668
 669         if (!firmware) {
 670                 dev_err(cs42l43->dev, "Failed to load firmware\n");
 671                 cs42l43->firmware_error = -ENODEV;
 672                 goto err;
 673         }
 674
 675         hdr = (const struct cs42l43_patch_header *)&firmware->data[0];
 676         loadaddr = le32_to_cpu(hdr->load_addr);
 677
 678         if (le16_to_cpu(hdr->version) != CS42L43_MCU_UPDATE_FORMAT) {
 679                 dev_err(cs42l43->dev, "Bad firmware file format: %d\n", hdr->version);
 680                 cs42l43->firmware_error = -EINVAL;
 681                 goto err_release;
 682         }
 683
 684         regmap_write(cs42l43->regmap, CS42L43_PATCH_START_ADDR, loadaddr);
 685         regmap_bulk_write(cs42l43->regmap, loadaddr + CS42L43_MCU_UPDATE_OFFSET,
 686                           &firmware->data[0], firmware->size / sizeof(u32));
 687
 688         regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, CS42L43_PATCH_IND_MASK);
 689         regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, 0);
 690
 691         ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_SOFT_INT_SHADOW, val,
 692                                        (val & CS42L43_PATCH_APPLIED_INT_MASK),
 693                                        CS42L43_MCU_POLL, CS42L43_MCU_UPDATE_TIMEOUT);
 694         if (ret) {
 695                 dev_err(cs42l43->dev, "Failed to update firmware: %d, 0x%x\n", ret, val);
 696                 cs42l43->firmware_error = ret;
 697                 goto err_release;
 698         }
 699
 700 err_release:
 701         release_firmware(firmware);
 702 err:
 703         complete(&cs42l43->firmware_download);
 704 }
 705
 706 /*
 707  * The process of updating the firmware is split into a series of steps, at the
 708  * end of each step a soft reset of the device might be required which will
 709  * require the driver to wait for the device to re-attach on the SoundWire bus,
 710  * if that control bus is being used.
 711  */
 712 static int cs42l43_mcu_update_step(struct cs42l43 *cs42l43)
 713 {
 714         unsigned int mcu_rev, bios_rev, boot_status, secure_cfg;
 715         bool patched, shadow;
 716         int ret;
 717
 718         /* Clear any stale software interrupt bits. */
 719         regmap_read(cs42l43->regmap, CS42L43_SOFT_INT, &mcu_rev);
 720
 721         ret = regmap_read(cs42l43->regmap, CS42L43_BOOT_STATUS, &boot_status);
 722         if (ret) {
 723                 dev_err(cs42l43->dev, "Failed to read boot status: %d\n", ret);
 724                 return ret;
 725         }
 726
 727         ret = regmap_read(cs42l43->regmap, CS42L43_MCU_SW_REV, &mcu_rev);
 728         if (ret) {
 729                 dev_err(cs42l43->dev, "Failed to read firmware revision: %d\n", ret);
 730                 return ret;
 731         }
 732
 733         bios_rev = (((mcu_rev & CS42L43_BIOS_MAJOR_REV_MASK) << 12) |
 734                     ((mcu_rev & CS42L43_BIOS_MINOR_REV_MASK) << 4) |
 735                     ((mcu_rev & CS42L43_BIOS_SUBMINOR_REV_MASK) >> 8)) >>
 736                    CS42L43_BIOS_MAJOR_REV_SHIFT;
 737         mcu_rev = ((mcu_rev & CS42L43_FW_MAJOR_REV_MASK) << 12) |
 738                   ((mcu_rev & CS42L43_FW_MINOR_REV_MASK) << 4) |
 739                   ((mcu_rev & CS42L43_FW_SUBMINOR_REV_MASK) >> 8);
 740
 741         /*
 742          * The firmware has two revision numbers bringing either of them up to a
 743          * supported version will provide the features the driver requires.
 744          */
 745         patched = mcu_rev >= CS42L43_MCU_SUPPORTED_REV ||
 746                   bios_rev >= CS42L43_MCU_SUPPORTED_BIOS_REV;
 747         /*
 748          * Later versions of the firmwware require the driver to access some
 749          * features through a set of shadow registers.
 750          */
 751         shadow = mcu_rev >= CS42L43_MCU_SHADOW_REGS_REQUIRED_REV;
 752
 753         ret = regmap_read(cs42l43->regmap, CS42L43_BOOT_CONTROL, &secure_cfg);
 754         if (ret) {
 755                 dev_err(cs42l43->dev, "Failed to read security settings: %d\n", ret);
 756                 return ret;
 757         }
 758
 759         cs42l43->hw_lock = secure_cfg & CS42L43_LOCK_HW_STS_MASK;
 760
 761         if (!patched && cs42l43->hw_lock) {
 762                 dev_err(cs42l43->dev, "Unpatched secure device\n");
 763                 return -EPERM;
 764         }
 765
 766         dev_dbg(cs42l43->dev, "Firmware(0x%x, 0x%x) in boot stage %d\n",
 767                 mcu_rev, bios_rev, boot_status);
 768
 769         switch (boot_status) {
 770         case CS42L43_MCU_BOOT_STAGE2:
 771                 if (!patched) {
 772                         ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT,
 773                                                       "cs42l43.bin", cs42l43->dev,
 774                                                       GFP_KERNEL, cs42l43,
 775                                                       cs42l43_mcu_load_firmware);
 776                         if (ret) {
 777                                 dev_err(cs42l43->dev, "Failed to request firmware: %d\n", ret);
 778                                 return ret;
 779                         }
 780
 781                         wait_for_completion(&cs42l43->firmware_download);
 782
 783                         if (cs42l43->firmware_error)
 784                                 return cs42l43->firmware_error;
 785
 786                         return -EAGAIN;
 787                 } else {
 788                         return cs42l43_mcu_stage_2_3(cs42l43, shadow);
 789                 }
 790         case CS42L43_MCU_BOOT_STAGE3:
 791                 if (patched)
 792                         return cs42l43_mcu_disable(cs42l43);
 793                 else
 794                         return cs42l43_mcu_stage_3_2(cs42l43);
 795         case CS42L43_MCU_BOOT_STAGE4:
 796                 return 0;
 797         default:
 798                 dev_err(cs42l43->dev, "Invalid boot status: %d\n", boot_status);
 799                 return -EINVAL;
 800         }
 801 }
 802
 803 /*
 804  * Update the firmware running on the device.
 805  */
 806 static int cs42l43_mcu_update(struct cs42l43 *cs42l43)
 807 {
 808         int i, ret;
 809
 810         for (i = 0; i < CS42L43_MCU_UPDATE_RETRIES; i++) {
 811                 ret = cs42l43_mcu_update_step(cs42l43);
 812                 if (ret != -EAGAIN)
 813                         return ret;
 814
 815                 ret = cs42l43_wait_for_attach(cs42l43);
 816                 if (ret)
 817                         return ret;
 818         }
 819
 820         dev_err(cs42l43->dev, "Failed retrying update\n");
 821         return -ETIMEDOUT;
 822 }
 823
 824 static int cs42l43_irq_config(struct cs42l43 *cs42l43)
 825 {
 826         struct irq_data *irq_data;
 827         unsigned long irq_flags;
 828         int ret;
 829
 830         if (cs42l43->sdw)
 831                 cs42l43->irq = cs42l43->sdw->irq;
 832
 833         cs42l43->irq_chip = cs42l43_irq_chip;
 834         cs42l43->irq_chip.irq_drv_data = cs42l43;
 835
 836         irq_data = irq_get_irq_data(cs42l43->irq);
 837         if (!irq_data) {
 838                 dev_err(cs42l43->dev, "Invalid IRQ: %d\n", cs42l43->irq);
 839                 return -EINVAL;
 840         }
 841
 842         irq_flags = irqd_get_trigger_type(irq_data);
 843         switch (irq_flags) {
 844         case IRQF_TRIGGER_LOW:
 845         case IRQF_TRIGGER_HIGH:
 846         case IRQF_TRIGGER_RISING:
 847         case IRQF_TRIGGER_FALLING:
 848                 break;
 849         case IRQ_TYPE_NONE:
 850         default:
 851                 irq_flags = IRQF_TRIGGER_LOW;
 852                 break;
 853         }
 854
 855         irq_flags |= IRQF_ONESHOT;
 856
 857         ret = devm_regmap_add_irq_chip(cs42l43->dev, cs42l43->regmap,
 858                                        cs42l43->irq, irq_flags, 0,
 859                                        &cs42l43->irq_chip, &cs42l43->irq_data);
 860         if (ret) {
 861                 dev_err(cs42l43->dev, "Failed to add IRQ chip: %d\n", ret);
 862                 return ret;
 863         }
 864
 865         dev_dbg(cs42l43->dev, "Configured IRQ %d with flags 0x%lx\n",
 866                 cs42l43->irq, irq_flags);
 867
 868         return 0;
 869 }
 870
 871 static void cs42l43_boot_work(struct work_struct *work)
 872 {
 873         struct cs42l43 *cs42l43 = container_of(work, struct cs42l43, boot_work);
 874         unsigned int devid, revid, otp;
 875         int ret;
 876
 877         ret = cs42l43_wait_for_attach(cs42l43);
 878         if (ret)
 879                 goto err;
 880
 881         ret = regmap_read(cs42l43->regmap, CS42L43_DEVID, &devid);
 882         if (ret) {
 883                 dev_err(cs42l43->dev, "Failed to read devid: %d\n", ret);
 884                 goto err;
 885         }
 886
 887         switch (devid) {
 888         case CS42L43_DEVID_VAL:
 889                 break;
 890         default:
 891                 dev_err(cs42l43->dev, "Unrecognised devid: 0x%06x\n", devid);
 892                 goto err;
 893         }
 894
 895         ret = regmap_read(cs42l43->regmap, CS42L43_REVID, &revid);
 896         if (ret) {
 897                 dev_err(cs42l43->dev, "Failed to read rev: %d\n", ret);
 898                 goto err;
 899         }
 900
 901         ret = regmap_read(cs42l43->regmap, CS42L43_OTP_REVISION_ID, &otp);
 902         if (ret) {
 903                 dev_err(cs42l43->dev, "Failed to read otp rev: %d\n", ret);
 904                 goto err;
 905         }
 906
 907         dev_info(cs42l43->dev,
 908                  "devid: 0x%06x, rev: 0x%02x, otp: 0x%02x\n", devid, revid, otp);
 909
 910         ret = cs42l43_mcu_update(cs42l43);
 911         if (ret)
 912                 goto err;
 913
 914         ret = regmap_register_patch(cs42l43->regmap, cs42l43_reva_patch,
 915                                     ARRAY_SIZE(cs42l43_reva_patch));
 916         if (ret) {
 917                 dev_err(cs42l43->dev, "Failed to apply register patch: %d\n", ret);
 918                 goto err;
 919         }
 920
 921         ret = cs42l43_irq_config(cs42l43);
 922         if (ret)
 923                 goto err;
 924
 925         ret = devm_mfd_add_devices(cs42l43->dev, PLATFORM_DEVID_NONE,
 926                                    cs42l43_devs, ARRAY_SIZE(cs42l43_devs),
 927                                    NULL, 0, NULL);
 928         if (ret) {
 929                 dev_err(cs42l43->dev, "Failed to add subdevices: %d\n", ret);
 930                 goto err;
 931         }
 932
 933         pm_runtime_mark_last_busy(cs42l43->dev);
 934         pm_runtime_put_autosuspend(cs42l43->dev);
 935
 936         return;
 937
 938 err:
 939         pm_runtime_put_sync(cs42l43->dev);
 940         cs42l43_dev_remove(cs42l43);
 941 }
 942
 943 static int cs42l43_power_up(struct cs42l43 *cs42l43)
 944 {
 945         int ret;
 946
 947         ret = regulator_enable(cs42l43->vdd_p);
 948         if (ret) {
 949                 dev_err(cs42l43->dev, "Failed to enable vdd-p: %d\n", ret);
 950                 return ret;
 951         }
 952
 953         /* vdd-p must be on for 50uS before any other supply */
 954         usleep_range(CS42L43_VDDP_DELAY, 2 * CS42L43_VDDP_DELAY);
 955
 956         gpiod_set_value_cansleep(cs42l43->reset, 1);
 957
 958         ret = regulator_bulk_enable(CS42L43_N_SUPPLIES, cs42l43->core_supplies);
 959         if (ret) {
 960                 dev_err(cs42l43->dev, "Failed to enable core supplies: %d\n", ret);
 961                 goto err_reset;
 962         }
 963
 964         ret = regulator_enable(cs42l43->vdd_d);
 965         if (ret) {
 966                 dev_err(cs42l43->dev, "Failed to enable vdd-d: %d\n", ret);
 967                 goto err_core_supplies;
 968         }
 969
 970         usleep_range(CS42L43_VDDD_DELAY, 2 * CS42L43_VDDD_DELAY);
 971
 972         return 0;
 973
 974 err_core_supplies:
 975         regulator_bulk_disable(CS42L43_N_SUPPLIES, cs42l43->core_supplies);
 976 err_reset:
 977         gpiod_set_value_cansleep(cs42l43->reset, 0);
 978         regulator_disable(cs42l43->vdd_p);
 979
 980         return ret;
 981 }
 982
 983 static int cs42l43_power_down(struct cs42l43 *cs42l43)
 984 {
 985         int ret;
 986
 987         ret = regulator_disable(cs42l43->vdd_d);
 988         if (ret) {
 989                 dev_err(cs42l43->dev, "Failed to disable vdd-d: %d\n", ret);
 990                 return ret;
 991         }
 992
 993         ret = regulator_bulk_disable(CS42L43_N_SUPPLIES, cs42l43->core_supplies);
 994         if (ret) {
 995                 dev_err(cs42l43->dev, "Failed to disable core supplies: %d\n", ret);
 996                 return ret;
 997         }
 998
 999         gpiod_set_value_cansleep(cs42l43->reset, 0);
1000
1001         ret = regulator_disable(cs42l43->vdd_p);
1002         if (ret) {
1003                 dev_err(cs42l43->dev, "Failed to disable vdd-p: %d\n", ret);
1004                 return ret;
1005         }
1006
1007         return 0;
1008 }
1009
1010 int cs42l43_dev_probe(struct cs42l43 *cs42l43)
1011 {
1012         int i, ret;
1013
1014         dev_set_drvdata(cs42l43->dev, cs42l43);
1015
1016         mutex_init(&cs42l43->pll_lock);
1017         init_completion(&cs42l43->device_attach);
1018         init_completion(&cs42l43->device_detach);
1019         init_completion(&cs42l43->firmware_download);
1020         INIT_WORK(&cs42l43->boot_work, cs42l43_boot_work);
1021
1022         regcache_cache_only(cs42l43->regmap, true);
1023
1024         cs42l43->reset = devm_gpiod_get_optional(cs42l43->dev, "reset", GPIOD_OUT_LOW);
1025         if (IS_ERR(cs42l43->reset))
1026                 return dev_err_probe(cs42l43->dev, PTR_ERR(cs42l43->reset),
1027                                      "Failed to get reset\n");
1028
1029         cs42l43->vdd_p = devm_regulator_get(cs42l43->dev, "vdd-p");
1030         if (IS_ERR(cs42l43->vdd_p))
1031                 return dev_err_probe(cs42l43->dev, PTR_ERR(cs42l43->vdd_p),
1032                                      "Failed to get vdd-p\n");
1033
1034         cs42l43->vdd_d = devm_regulator_get(cs42l43->dev, "vdd-d");
1035         if (IS_ERR(cs42l43->vdd_d))
1036                 return dev_err_probe(cs42l43->dev, PTR_ERR(cs42l43->vdd_d),
1037                                      "Failed to get vdd-d\n");
1038
1039         BUILD_BUG_ON(ARRAY_SIZE(cs42l43_core_supplies) != CS42L43_N_SUPPLIES);
1040
1041         for (i = 0; i < CS42L43_N_SUPPLIES; i++)
1042                 cs42l43->core_supplies[i].supply = cs42l43_core_supplies[i];
1043
1044         ret = devm_regulator_bulk_get(cs42l43->dev, CS42L43_N_SUPPLIES,
1045                                       cs42l43->core_supplies);
1046         if (ret)
1047                 return dev_err_probe(cs42l43->dev, ret,
1048                                      "Failed to get core supplies\n");
1049
1050         ret = cs42l43_power_up(cs42l43);
1051         if (ret)
1052                 return ret;
1053
1054         pm_runtime_set_autosuspend_delay(cs42l43->dev, CS42L43_AUTOSUSPEND_TIME);
1055         pm_runtime_use_autosuspend(cs42l43->dev);
1056         pm_runtime_set_active(cs42l43->dev);
1057         /*
1058          * The device is already powered up, but keep it from suspending until
1059          * the boot work runs.
1060          */
1061         pm_runtime_get_noresume(cs42l43->dev);
1062         devm_pm_runtime_enable(cs42l43->dev);
1063
1064         queue_work(system_long_wq, &cs42l43->boot_work);
1065
1066         return 0;
1067 }
1068 EXPORT_SYMBOL_NS_GPL(cs42l43_dev_probe, MFD_CS42L43);
1069
1070 void cs42l43_dev_remove(struct cs42l43 *cs42l43)
1071 {
1072         cs42l43_power_down(cs42l43);
1073 }
1074 EXPORT_SYMBOL_NS_GPL(cs42l43_dev_remove, MFD_CS42L43);
1075
1076 static int cs42l43_suspend(struct device *dev)
1077 {
1078         struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
1079         int ret;
1080
1081         /*
1082          * Don't care about being resumed here, but the driver does want
1083          * force_resume to always trigger an actual resume, so that register
1084          * state for the MCU/GPIOs is returned as soon as possible after system
1085          * resume. force_resume will resume if the reference count is resumed on
1086          * suspend hence the get_noresume.
1087          */
1088         pm_runtime_get_noresume(dev);
1089
1090         ret = pm_runtime_force_suspend(dev);
1091         if (ret) {
1092                 dev_err(cs42l43->dev, "Failed to force suspend: %d\n", ret);
1093                 pm_runtime_put_noidle(dev);
1094                 return ret;
1095         }
1096
1097         pm_runtime_put_noidle(dev);
1098
1099         ret = cs42l43_power_down(cs42l43);
1100         if (ret)
1101                 return ret;
1102
1103         return 0;
1104 }
1105
1106 static int cs42l43_resume(struct device *dev)
1107 {
1108         struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
1109         int ret;
1110
1111         ret = cs42l43_power_up(cs42l43);
1112         if (ret)
1113                 return ret;
1114
1115         ret = pm_runtime_force_resume(dev);
1116         if (ret) {
1117                 dev_err(cs42l43->dev, "Failed to force resume: %d\n", ret);
1118                 return ret;
1119         }
1120
1121         return 0;
1122 }
1123
1124 static int cs42l43_runtime_suspend(struct device *dev)
1125 {
1126         struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
1127
1128         /*
1129          * Whilst the driver doesn't power the chip down here, going into runtime
1130          * suspend lets the SoundWire bus power down, which means the driver
1131          * can't communicate with the device any more.
1132          */
1133         regcache_cache_only(cs42l43->regmap, true);
1134
1135         return 0;
1136 }
1137
1138 static int cs42l43_runtime_resume(struct device *dev)
1139 {
1140         struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
1141         unsigned int reset_canary;
1142         int ret;
1143
1144         ret = cs42l43_wait_for_attach(cs42l43);
1145         if (ret)
1146                 return ret;
1147
1148         ret = regmap_read(cs42l43->regmap, CS42L43_RELID, &reset_canary);
1149         if (ret) {
1150                 dev_err(cs42l43->dev, "Failed to check reset canary: %d\n", ret);
1151                 goto err;
1152         }
1153
1154         if (!reset_canary) {
1155                 /*
1156                  * If the canary has cleared the chip has reset, re-handle the
1157                  * MCU and mark the cache as dirty to indicate the chip reset.
1158                  */
1159                 ret = cs42l43_mcu_update(cs42l43);
1160                 if (ret)
1161                         goto err;
1162
1163                 regcache_mark_dirty(cs42l43->regmap);
1164         }
1165
1166         ret = regcache_sync(cs42l43->regmap);
1167         if (ret) {
1168                 dev_err(cs42l43->dev, "Failed to restore register cache: %d\n", ret);
1169                 goto err;
1170         }
1171
1172         return 0;
1173
1174 err:
1175         regcache_cache_only(cs42l43->regmap, true);
1176
1177         return ret;
1178 }
1179
1180 EXPORT_NS_GPL_DEV_PM_OPS(cs42l43_pm_ops, MFD_CS42L43) = {
1181         SET_SYSTEM_SLEEP_PM_OPS(cs42l43_suspend, cs42l43_resume)
1182         SET_RUNTIME_PM_OPS(cs42l43_runtime_suspend, cs42l43_runtime_resume, NULL)
1183 };
1184
1185 MODULE_DESCRIPTION("CS42L43 Core Driver");
1186 MODULE_AUTHOR("Charles Keepax <ckeepax@opensource.cirrus.com>");
1187 MODULE_LICENSE("GPL");
1188 MODULE_FIRMWARE("cs42l43.bin");