1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Texas Instruments GPMC Driver
5 * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
8 /* GPMC register offsets */
9 #define GPMC_REVISION 0x00
10 #define GPMC_SYSCONFIG 0x10
11 #define GPMC_SYSSTATUS 0x14
12 #define GPMC_IRQSTATUS 0x18
13 #define GPMC_IRQENABLE 0x1c
14 #define GPMC_TIMEOUT_CONTROL 0x40
15 #define GPMC_ERR_ADDRESS 0x44
16 #define GPMC_ERR_TYPE 0x48
17 #define GPMC_CONFIG 0x50
18 #define GPMC_STATUS 0x54
19 #define GPMC_PREFETCH_CONFIG1 0x1e0
20 #define GPMC_PREFETCH_CONFIG2 0x1e4
21 #define GPMC_PREFETCH_CONTROL 0x1ec
22 #define GPMC_PREFETCH_STATUS 0x1f0
23 #define GPMC_ECC_CONFIG 0x1f4
24 #define GPMC_ECC_CONTROL 0x1f8
25 #define GPMC_ECC_SIZE_CONFIG 0x1fc
26 #define GPMC_ECC1_RESULT 0x200
27 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
28 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
29 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
30 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
31 #define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
32 #define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
33 #define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
35 /* GPMC ECC control settings */
36 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
37 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
38 #define GPMC_ECC_CTRL_ECCREG1 0x001
39 #define GPMC_ECC_CTRL_ECCREG2 0x002
40 #define GPMC_ECC_CTRL_ECCREG3 0x003
41 #define GPMC_ECC_CTRL_ECCREG4 0x004
42 #define GPMC_ECC_CTRL_ECCREG5 0x005
43 #define GPMC_ECC_CTRL_ECCREG6 0x006
44 #define GPMC_ECC_CTRL_ECCREG7 0x007
45 #define GPMC_ECC_CTRL_ECCREG8 0x008
46 #define GPMC_ECC_CTRL_ECCREG9 0x009
48 #define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
50 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0)
52 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
53 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
54 #define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
55 #define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
56 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
57 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
59 #define GPMC_CS0_OFFSET 0x60
60 #define GPMC_CS_SIZE 0x30
61 #define GPMC_BCH_SIZE 0x10
64 * The first 1MB of GPMC address space is typically mapped to
65 * the internal ROM. Never allocate the first page, to
66 * facilitate bug detection; even if we didn't boot from ROM.
67 * As GPMC minimum partition size is 16MB we can only start from
70 #define GPMC_MEM_START 0x1000000
71 #define GPMC_MEM_END 0x3FFFFFFF
73 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
74 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
76 #define CS_NUM_SHIFT 24
77 #define ENABLE_PREFETCH (0x1 << 7)
78 #define DMA_MPU_MODE 2
80 #define GPMC_REVISION_MAJOR(l) (((l) >> 4) & 0xf)
81 #define GPMC_REVISION_MINOR(l) ((l) & 0xf)
83 #define GPMC_HAS_WR_ACCESS 0x1
84 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
85 #define GPMC_HAS_MUX_AAD 0x4
87 #define GPMC_NR_WAITPINS 4
89 #define GPMC_CS_CONFIG1 0x00
90 #define GPMC_CS_CONFIG2 0x04
91 #define GPMC_CS_CONFIG3 0x08
92 #define GPMC_CS_CONFIG4 0x0c
93 #define GPMC_CS_CONFIG5 0x10
94 #define GPMC_CS_CONFIG6 0x14
95 #define GPMC_CS_CONFIG7 0x18
96 #define GPMC_CS_NAND_COMMAND 0x1c
97 #define GPMC_CS_NAND_ADDRESS 0x20
98 #define GPMC_CS_NAND_DATA 0x24
100 /* Control Commands */
101 #define GPMC_CONFIG_RDY_BSY 0x00000001
102 #define GPMC_CONFIG_DEV_SIZE 0x00000002
103 #define GPMC_CONFIG_DEV_TYPE 0x00000003
105 #define GPMC_CONFIG_WP 0x00000005
107 #define GPMC_CONFIG1_WRAPBURST_SUPP BIT(31)
108 #define GPMC_CONFIG1_READMULTIPLE_SUPP BIT(30)
109 #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
110 #define GPMC_CONFIG1_READTYPE_SYNC BIT(29)
111 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP BIT(28)
112 #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
113 #define GPMC_CONFIG1_WRITETYPE_SYNC BIT(27)
114 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25)
115 /** CLKACTIVATIONTIME Max Ticks */
116 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
117 #define GPMC_CONFIG1_PAGE_LEN(val) (((val) & 3) << 23)
118 /** ATTACHEDDEVICEPAGELENGTH Max Value */
119 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
120 #define GPMC_CONFIG1_WAIT_READ_MON BIT(22)
121 #define GPMC_CONFIG1_WAIT_WRITE_MON BIT(21)
122 #define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18)
123 /** WAITMONITORINGTIME Max Ticks */
124 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2
125 #define GPMC_CONFIG1_WAIT_PIN_SEL(val) (((val) & 3) << 16)
126 #define GPMC_CONFIG1_DEVICESIZE(val) (((val) & 3) << 12)
127 #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
128 /** DEVICESIZE Max Value */
129 #define GPMC_CONFIG1_DEVICESIZE_MAX 1
130 #define GPMC_CONFIG1_DEVICETYPE(val) (((val) & 3) << 10)
131 #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
132 #define GPMC_CONFIG1_MUXTYPE(val) (((val) & 3) << 8)
133 #define GPMC_CONFIG1_TIME_PARA_GRAN BIT(4)
134 #define GPMC_CONFIG1_FCLK_DIV(val) ((val) & 3)
135 #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
136 #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
137 #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
138 #define GPMC_CONFIG7_CSVALID BIT(6)
140 #define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f
141 #define GPMC_CONFIG7_CSVALID_MASK BIT(6)
142 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
143 #define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
144 /* All CONFIG7 bits except reserved bits */
145 #define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \
146 GPMC_CONFIG7_CSVALID_MASK | \
147 GPMC_CONFIG7_MASKADDRESS_MASK)
149 #define GPMC_DEVICETYPE_NOR 0
150 #define GPMC_DEVICETYPE_NAND 2
151 #define GPMC_CONFIG_WRITEPROTECT 0x00000010
152 #define WR_RD_PIN_MONITORING 0x00600000
155 #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
156 #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
157 #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
159 #define GPMC_NR_NAND_IRQS 2 /* number of NAND specific IRQs */
161 /* bool type time settings */
162 struct gpmc_bool_timings {
163 bool cycle2cyclediffcsen;
164 bool cycle2cyclesamecsen;
167 bool adv_extra_delay;
169 bool time_para_granularity;
173 * Note that all values in this struct are in nanoseconds except sync_clk
174 * (which is in picoseconds), while the register values are in gpmc_fck cycles.
176 struct gpmc_timings {
177 /* Minimum clock period for synchronous mode (in picoseconds) */
180 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
181 u32 cs_on; /* Assertion time */
182 u32 cs_rd_off; /* Read deassertion time */
183 u32 cs_wr_off; /* Write deassertion time */
185 /* ADV signal timings corresponding to GPMC_CONFIG3 */
186 u32 adv_on; /* Assertion time */
187 u32 adv_rd_off; /* Read deassertion time */
188 u32 adv_wr_off; /* Write deassertion time */
189 u32 adv_aad_mux_on; /* ADV assertion time for AAD */
190 u32 adv_aad_mux_rd_off; /* ADV read deassertion time for AAD */
191 u32 adv_aad_mux_wr_off; /* ADV write deassertion time for AAD */
193 /* WE signals timings corresponding to GPMC_CONFIG4 */
194 u32 we_on; /* WE assertion time */
195 u32 we_off; /* WE deassertion time */
197 /* OE signals timings corresponding to GPMC_CONFIG4 */
198 u32 oe_on; /* OE assertion time */
199 u32 oe_off; /* OE deassertion time */
200 u32 oe_aad_mux_on; /* OE assertion time for AAD */
201 u32 oe_aad_mux_off; /* OE deassertion time for AAD */
203 /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
204 u32 page_burst_access; /* Multiple access word delay */
205 u32 access; /* Start-cycle to first data valid delay */
206 u32 rd_cycle; /* Total read cycle time */
207 u32 wr_cycle; /* Total write cycle time */
210 u32 cycle2cycle_delay;
215 /* The following are only on OMAP3430 */
216 u32 wr_access; /* WRACCESSTIME */
217 u32 wr_data_mux_bus; /* WRDATAONADMUXBUS */
219 struct gpmc_bool_timings bool_timings;
222 /* Device timings in picoseconds */
223 struct gpmc_device_timings {
224 u32 t_ceasu; /* address setup to CS valid */
225 u32 t_avdasu; /* address setup to ADV valid */
226 /* XXX: try to combine t_avdp_r & t_avdp_w. Issue is
227 * of tusb using these timings even for sync whilst
228 * ideally for adv_rd/(wr)_off it should have considered
229 * t_avdh instead. This indirectly necessitates r/w
230 * variations of t_avdp as it is possible to have one
233 u32 t_avdp_r; /* ADV low time (what about t_cer ?) */
235 u32 t_aavdh; /* address hold time */
236 u32 t_oeasu; /* address setup to OE valid */
237 u32 t_aa; /* access time from ADV assertion */
238 u32 t_iaa; /* initial access time */
239 u32 t_oe; /* access time from OE assertion */
240 u32 t_ce; /* access time from CS asertion */
241 u32 t_rd_cycle; /* read cycle time */
242 u32 t_cez_r; /* read CS deassertion to high Z */
243 u32 t_cez_w; /* write CS deassertion to high Z */
244 u32 t_oez; /* OE deassertion to high Z */
245 u32 t_weasu; /* address setup to WE valid */
246 u32 t_wpl; /* write assertion time */
247 u32 t_wph; /* write deassertion time */
248 u32 t_wr_cycle; /* write cycle time */
251 u32 t_bacc; /* burst access valid clock to output delay */
252 u32 t_ces; /* CS setup time to clk */
253 u32 t_avds; /* ADV setup time to clk */
254 u32 t_avdh; /* ADV hold time from clk */
255 u32 t_ach; /* address hold time from clk */
256 u32 t_rdyo; /* clk to ready valid */
258 u32 t_ce_rdyz; /* XXX: description ?, or use t_cez instead */
259 u32 t_ce_avd; /* CS on to ADV on delay */
261 /* XXX: check the possibility of combining
262 * cyc_aavhd_oe & cyc_aavdh_we
264 u8 cyc_aavdh_oe;/* read address hold time in cycles */
265 u8 cyc_aavdh_we;/* write address hold time in cycles */
266 u8 cyc_oe; /* access time from OE assertion in cycles */
267 u8 cyc_wpl; /* write deassertion time in cycles */
268 u32 cyc_iaa; /* initial access time in cycles */
277 #define GPMC_BURST_4 4 /* 4 word burst */
278 #define GPMC_BURST_8 8 /* 8 word burst */
279 #define GPMC_BURST_16 16 /* 16 word burst */
280 #define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
281 #define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */
282 #define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */
283 #define GPMC_MUX_AD 2 /* Addr-Data multiplex */
285 struct gpmc_settings {
286 bool burst_wrap; /* enables wrap bursting */
287 bool burst_read; /* enables read page/burst mode */
288 bool burst_write; /* enables write page/burst mode */
289 bool device_nand; /* device is NAND */
290 bool sync_read; /* enables synchronous reads */
291 bool sync_write; /* enables synchronous writes */
292 bool wait_on_read; /* monitor wait on reads */
293 bool wait_on_write; /* monitor wait on writes */
294 u32 burst_len; /* page/burst length */
295 u32 device_width; /* device bus width (8 or 16 bit) */
296 u32 mux_add_data; /* multiplex address & data */
297 u32 wait_pin; /* wait-pin to be used */