drivers/memory/ti-gpmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Texas Instruments GPMC Driver
   4  *
   5  * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7
   8 #include <asm/io.h>
   9 #include <asm/arch/sys_proto.h>
  10 #include <clk.h>
  11 #include <common.h>
  12 #include <dm.h>
  13 #include <dm/device-internal.h>
  14 #include <dm/device_compat.h>
  15 #include <dm/devres.h>
  16 #include <dm/lists.h>
  17 #include <linux/mtd/omap_gpmc.h>
  18 #include <linux/ioport.h>
  19 #include <linux/io.h>
  20 #include "ti-gpmc.h"
  21
  22 enum gpmc_clk_domain {
  23         GPMC_CD_FCLK,
  24         GPMC_CD_CLK
  25 };
  26
  27 struct gpmc_cs_data {
  28         const char *name;
  29 #define GPMC_CS_RESERVED        BIT(0)
  30         u32 flags;
  31 };
  32
  33 struct ti_gpmc {
  34         void __iomem *base;
  35         u32 cs_num;
  36         u32 nr_waitpins;
  37         struct clk *l3_clk;
  38         u32 capability_flags;
  39         struct resource data;
  40 };
  41
  42 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
  43 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
  44 static unsigned int gpmc_nr_waitpins;
  45 static unsigned int gpmc_capability;
  46 static void __iomem *gpmc_base;
  47 static struct clk *gpmc_l3_clk;
  48
  49 /* Public, as required by nand/raw/omap_gpmc.c */
  50 const struct gpmc *gpmc_cfg;
  51
  52 /*
  53  * The first 1MB of GPMC address space is typically mapped to
  54  * the internal ROM. Never allocate the first page, to
  55  * facilitate bug detection; even if we didn't boot from ROM.
  56  * As GPMC minimum partition size is 16MB we can only start from
  57  * there.
  58  */
  59 #define GPMC_MEM_START          0x1000000
  60 #define GPMC_MEM_END            0x3FFFFFFF
  61
  62 static void gpmc_write_reg(int idx, u32 val)
  63 {
  64         writel_relaxed(val, gpmc_base + idx);
  65 }
  66
  67 static u32 gpmc_read_reg(int idx)
  68 {
  69         return readl_relaxed(gpmc_base + idx);
  70 }
  71
  72 static void gpmc_cs_write_reg(int cs, int idx, u32 val)
  73 {
  74         void __iomem *reg_addr;
  75
  76         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
  77         writel_relaxed(val, reg_addr);
  78 }
  79
  80 static u32 gpmc_cs_read_reg(int cs, int idx)
  81 {
  82         void __iomem *reg_addr;
  83
  84         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
  85         return readl_relaxed(reg_addr);
  86 }
  87
  88 static unsigned long gpmc_get_fclk_period(void)
  89 {
  90         unsigned long rate = clk_get_rate(gpmc_l3_clk);
  91
  92         rate /= 1000;
  93         rate = 1000000000 / rate;       /* In picoseconds */
  94
  95         return rate;
  96 }
  97
  98 /**
  99  * gpmc_get_clk_period - get period of selected clock domain in ps
 100  * @cs: Chip Select Region.
 101  * @cd: Clock Domain.
 102  *
 103  * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
 104  * prior to calling this function with GPMC_CD_CLK.
 105  */
 106 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
 107 {
 108         unsigned long tick_ps = gpmc_get_fclk_period();
 109         u32 l;
 110         int div;
 111
 112         switch (cd) {
 113         case GPMC_CD_CLK:
 114                 /* get current clk divider */
 115                 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 116                 div = (l & 0x03) + 1;
 117                 /* get GPMC_CLK period */
 118                 tick_ps *= div;
 119                 break;
 120         case GPMC_CD_FCLK:
 121         default:
 122                 break;
 123         }
 124
 125         return tick_ps;
 126 }
 127
 128 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
 129                                          enum gpmc_clk_domain cd)
 130 {
 131         unsigned long tick_ps;
 132
 133         /* Calculate in picosecs to yield more exact results */
 134         tick_ps = gpmc_get_clk_period(cs, cd);
 135
 136         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 137 }
 138
 139 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 140 {
 141         return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
 142 }
 143
 144 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 145 {
 146         unsigned long tick_ps;
 147
 148         /* Calculate in picosecs to yield more exact results */
 149         tick_ps = gpmc_get_fclk_period();
 150
 151         return (time_ps + tick_ps - 1) / tick_ps;
 152 }
 153
 154 static __maybe_unused unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs,
 155                                                         enum gpmc_clk_domain cd)
 156 {
 157         return ticks * gpmc_get_clk_period(cs, cd) / 1000;
 158 }
 159
 160 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
 161 {
 162         u32 l;
 163
 164         l = gpmc_cs_read_reg(cs, reg);
 165         if (value)
 166                 l |= mask;
 167         else
 168                 l &= ~mask;
 169         gpmc_cs_write_reg(cs, reg, l);
 170 }
 171
 172 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
 173 {
 174         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
 175                            GPMC_CONFIG1_TIME_PARA_GRAN,
 176                            p->time_para_granularity);
 177         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
 178                            GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
 179         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
 180                            GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
 181         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 182                            GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
 183         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 184                            GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
 185         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 186                            GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
 187                            p->cycle2cyclesamecsen);
 188         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 189                            GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
 190                            p->cycle2cyclediffcsen);
 191 }
 192
 193 #if IS_ENABLED(CONFIG_TI_GPMC_DEBUG)
 194 /**
 195  * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
 196  * @cs:      Chip Select Region
 197  * @reg:     GPMC_CS_CONFIGn register offset.
 198  * @st_bit:  Start Bit
 199  * @end_bit: End Bit. Must be >= @st_bit.
 200  * @max:     Maximum parameter value (before optional @shift).
 201  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 202  * @name:    DTS node name, w/o "gpmc,"
 203  * @cd:      Clock Domain of timing parameter.
 204  * @shift:   Parameter value left shifts @shift, which is then printed instead of value.
 205  * @raw:     Raw Format Option.
 206  *           raw format:  gpmc,name = <value>
 207  *           tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
 208  *           Where x ns -- y ns result in the same tick value.
 209  *           When @max is exceeded, "invalid" is printed inside comment.
 210  * @noval:   Parameter values equal to 0 are not printed.
 211  * @return:  Specified timing parameter (after optional @shift).
 212  *
 213  */
 214 static int get_gpmc_timing_reg(/* timing specifiers */
 215         int cs, int reg, int st_bit, int end_bit, int max,
 216         const char *name, const enum gpmc_clk_domain cd,
 217         /* value transform */
 218         int shift,
 219         /* format specifiers */
 220         bool raw, bool noval)
 221 {
 222         u32 l;
 223         int nr_bits;
 224         int mask;
 225         bool invalid;
 226
 227         l = gpmc_cs_read_reg(cs, reg);
 228         nr_bits = end_bit - st_bit + 1;
 229         mask = (1 << nr_bits) - 1;
 230         l = (l >> st_bit) & mask;
 231         if (!max)
 232                 max = mask;
 233         invalid = l > max;
 234         if (shift)
 235                 l = (shift << l);
 236         if (noval && l == 0)
 237                 return 0;
 238         if (!raw) {
 239                 /* DTS tick format for timings in ns */
 240                 unsigned int time_ns;
 241                 unsigned int time_ns_min = 0;
 242
 243                 if (l)
 244                         time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
 245                 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
 246                 pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
 247                         name, time_ns, time_ns_min, time_ns, l,
 248                         invalid ? "; invalid " : " ");
 249         } else {
 250                 /* raw format */
 251                 pr_info("gpmc,%s = <%u>;%s\n", name, l,
 252                         invalid ? " /* invalid */" : "");
 253         }
 254
 255         return l;
 256 }
 257
 258 #define GPMC_PRINT_CONFIG(cs, config) \
 259         pr_info("CS%i %s: 0x%08x\n", cs, #config, \
 260                 gpmc_cs_read_reg(cs, config))
 261 #define GPMC_GET_RAW(reg, st, end, field) \
 262         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
 263 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
 264         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
 265 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
 266         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
 267 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
 268         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
 269 #define GPMC_GET_TICKS(reg, st, end, field) \
 270         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
 271 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
 272         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
 273 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
 274         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
 275
 276 static void gpmc_show_regs(int cs, const char *desc)
 277 {
 278         pr_info("gpmc cs%i %s:\n", cs, desc);
 279         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
 280         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
 281         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
 282         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
 283         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
 284         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
 285 }
 286
 287 /*
 288  * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
 289  * see commit c9fb809.
 290  */
 291 static void gpmc_cs_show_timings(int cs, const char *desc)
 292 {
 293         gpmc_show_regs(cs, desc);
 294
 295         pr_info("gpmc cs%i access configuration:\n", cs);
 296         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
 297         GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
 298         GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
 299                                GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
 300         GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
 301         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
 302         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
 303         GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
 304                                GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
 305                                "burst-length");
 306         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
 307         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
 308         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
 309         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
 310         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
 311
 312         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2,  7,  7, "cs-extra-delay");
 313
 314         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3,  7,  7, "adv-extra-delay");
 315
 316         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
 317         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4,  7,  7, "oe-extra-delay");
 318
 319         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  7,  7, "cycle2cycle-samecsen");
 320         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  6,  6, "cycle2cycle-diffcsen");
 321
 322         pr_info("gpmc cs%i timings configuration:\n", cs);
 323         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  0,  3, "cs-on-ns");
 324         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  8, 12, "cs-rd-off-ns");
 325         GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
 326
 327         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  0,  3, "adv-on-ns");
 328         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  8, 12, "adv-rd-off-ns");
 329         GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
 330         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 331                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
 332                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
 333                                "adv-aad-mux-rd-off-ns");
 334                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
 335                                "adv-aad-mux-wr-off-ns");
 336         }
 337
 338         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  0,  3, "oe-on-ns");
 339         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  8, 12, "oe-off-ns");
 340         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 341                 GPMC_GET_TICKS(GPMC_CS_CONFIG4,  4,  6, "oe-aad-mux-on-ns");
 342                 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
 343         }
 344         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
 345         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
 346
 347         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  0,  4, "rd-cycle-ns");
 348         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  8, 12, "wr-cycle-ns");
 349         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
 350
 351         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
 352
 353         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
 354         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
 355
 356         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 357                               GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 358                               "wait-monitoring-ns", GPMC_CD_CLK);
 359         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 360                               GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 361                               "clk-activation-ns", GPMC_CD_FCLK);
 362
 363         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
 364         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
 365 }
 366 #else
 367 static inline void gpmc_cs_show_timings(int cs, const char *desc)
 368 {
 369 }
 370 #endif
 371
 372 /**
 373  * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
 374  * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
 375  * prior to calling this function with @cd equal to GPMC_CD_CLK.
 376  *
 377  * @cs:      Chip Select Region.
 378  * @reg:     GPMC_CS_CONFIGn register offset.
 379  * @st_bit:  Start Bit
 380  * @end_bit: End Bit. Must be >= @st_bit.
 381  * @max:     Maximum parameter value.
 382  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 383  * @time:    Timing parameter in ns.
 384  * @cd:      Timing parameter clock domain.
 385  * @name:    Timing parameter name.
 386  * @return:  0 on success, -1 on error.
 387  */
 388 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
 389                                int time, enum gpmc_clk_domain cd, const char *name)
 390 {
 391         u32 l;
 392         int ticks, mask, nr_bits;
 393
 394         if (time == 0)
 395                 ticks = 0;
 396         else
 397                 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
 398         nr_bits = end_bit - st_bit + 1;
 399         mask = (1 << nr_bits) - 1;
 400
 401         if (!max)
 402                 max = mask;
 403
 404         if (ticks > max) {
 405                 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
 406                        __func__, cs, name, time, ticks, max);
 407
 408                 return -1;
 409         }
 410
 411         l = gpmc_cs_read_reg(cs, reg);
 412         if (IS_ENABLED(CONFIG_TI_GPMC_DEBUG)) {
 413                 pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
 414                         cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
 415                                 (l >> st_bit) & mask, time);
 416         }
 417
 418         l &= ~(mask << st_bit);
 419         l |= ticks << st_bit;
 420         gpmc_cs_write_reg(cs, reg, l);
 421
 422         return 0;
 423 }
 424
 425 /**
 426  * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
 427  * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
 428  * read  --> don't sample bus too early
 429  * write --> data is longer on bus
 430  *
 431  * Formula:
 432  * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
 433  *                    / waitmonitoring_ticks)
 434  * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
 435  * div <= 0 check.
 436  *
 437  * @wait_monitoring: WAITMONITORINGTIME in ns.
 438  * @return:          -1 on failure to scale, else proper divider > 0.
 439  */
 440 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
 441 {
 442         int div = gpmc_ns_to_ticks(wait_monitoring);
 443
 444         div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
 445         div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
 446
 447         if (div > 4)
 448                 return -1;
 449         if (div <= 0)
 450                 div = 1;
 451
 452         return div;
 453 }
 454
 455 /**
 456  * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
 457  * @sync_clk: GPMC_CLK period in ps.
 458  * @return:   Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
 459  *            Else, returns -1.
 460  */
 461 static int gpmc_calc_divider(unsigned int sync_clk)
 462 {
 463         int div = gpmc_ps_to_ticks(sync_clk);
 464
 465         if (div > 4)
 466                 return -1;
 467         if (div <= 0)
 468                 div = 1;
 469
 470         return div;
 471 }
 472
 473 /**
 474  * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
 475  * @cs:     Chip Select Region.
 476  * @t:      GPMC timing parameters.
 477  * @s:      GPMC timing settings.
 478  * @return: 0 on success, -1 on error.
 479  */
 480 static int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
 481                                const struct gpmc_settings *s)
 482 {
 483         int div, ret;
 484         u32 l;
 485
 486         div = gpmc_calc_divider(t->sync_clk);
 487         if (div < 0)
 488                 return -EINVAL;
 489
 490         /*
 491          * See if we need to change the divider for waitmonitoringtime.
 492          *
 493          * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
 494          * pure asynchronous accesses, i.e. both read and write asynchronous.
 495          * However, only do so if WAITMONITORINGTIME is actually used, i.e.
 496          * either WAITREADMONITORING or WAITWRITEMONITORING is set.
 497          *
 498          * This statement must not change div to scale async WAITMONITORINGTIME
 499          * to protect mixed synchronous and asynchronous accesses.
 500          *
 501          * We raise an error later if WAITMONITORINGTIME does not fit.
 502          */
 503         if (!s->sync_read && !s->sync_write &&
 504             (s->wait_on_read || s->wait_on_write)
 505            ) {
 506                 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
 507                 if (div < 0) {
 508                         pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
 509                                __func__,
 510                                t->wait_monitoring
 511                                );
 512                         return -ENXIO;
 513                 }
 514         }
 515
 516         ret = 0;
 517         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 0, 3, 0, t->cs_on,
 518                                    GPMC_CD_FCLK, "cs_on");
 519         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 8, 12, 0, t->cs_rd_off,
 520                                    GPMC_CD_FCLK, "cs_rd_off");
 521         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 16, 20, 0, t->cs_wr_off,
 522                                    GPMC_CD_FCLK, "cs_wr_off");
 523         if (ret)
 524                 return -ENXIO;
 525
 526         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 0, 3, 0, t->adv_on,
 527                                    GPMC_CD_FCLK, "adv_on");
 528         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 8, 12, 0, t->adv_rd_off,
 529                                    GPMC_CD_FCLK, "adv_rd_off");
 530         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 16, 20, 0, t->adv_wr_off,
 531                                    GPMC_CD_FCLK, "adv_wr_off");
 532         if (ret)
 533                 return -ENXIO;
 534
 535         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 536                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 4, 6, 0,
 537                                            t->adv_aad_mux_on, GPMC_CD_FCLK,
 538                                            "adv_aad_mux_on");
 539                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 24, 26, 0,
 540                                            t->adv_aad_mux_rd_off, GPMC_CD_FCLK,
 541                                            "adv_aad_mux_rd_off");
 542                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 28, 30, 0,
 543                                            t->adv_aad_mux_wr_off, GPMC_CD_FCLK,
 544                                            "adv_aad_mux_wr_off");
 545                 if (ret)
 546                         return -ENXIO;
 547         }
 548
 549         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 0, 3, 0, t->oe_on,
 550                                    GPMC_CD_FCLK, "oe_on");
 551         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 8, 12, 0, t->oe_off,
 552                                    GPMC_CD_FCLK, "oe_off");
 553         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 554                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 4, 6, 0,
 555                                            t->oe_aad_mux_on, GPMC_CD_FCLK,
 556                                            "oe_aad_mux_on");
 557                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 13, 15, 0,
 558                                            t->oe_aad_mux_off, GPMC_CD_FCLK,
 559                                            "oe_aad_mux_off");
 560         }
 561         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 16, 19, 0, t->we_on,
 562                                    GPMC_CD_FCLK, "we_on");
 563         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 24, 28, 0, t->we_off,
 564                                    GPMC_CD_FCLK, "we_off");
 565         if (ret)
 566                 return -ENXIO;
 567
 568         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 0, 4, 0, t->rd_cycle,
 569                                    GPMC_CD_FCLK, "rd_cycle");
 570         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 8, 12, 0, t->wr_cycle,
 571                                    GPMC_CD_FCLK, "wr_cycle");
 572         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 16, 20, 0, t->access,
 573                                    GPMC_CD_FCLK, "access");
 574         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 24, 27, 0,
 575                                    t->page_burst_access, GPMC_CD_FCLK,
 576                                    "page_burst_access");
 577         if (ret)
 578                 return -ENXIO;
 579
 580         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 0, 3, 0,
 581                                    t->bus_turnaround, GPMC_CD_FCLK,
 582                                    "bus_turnaround");
 583         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 8, 11, 0,
 584                                    t->cycle2cycle_delay, GPMC_CD_FCLK,
 585                                    "cycle2cycle_delay");
 586         if (ret)
 587                 return -ENXIO;
 588
 589         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) {
 590                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 16, 19, 0,
 591                                            t->wr_data_mux_bus, GPMC_CD_FCLK,
 592                                            "wr_data_mux_bus");
 593                 if (ret)
 594                         return -ENXIO;
 595         }
 596         if (gpmc_capability & GPMC_HAS_WR_ACCESS) {
 597                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 24, 28, 0,
 598                                            t->wr_access, GPMC_CD_FCLK,
 599                                            "wr_access");
 600                 if (ret)
 601                         return -ENXIO;
 602         }
 603
 604         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 605         l &= ~0x03;
 606         l |= (div - 1);
 607         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 608
 609         ret = 0;
 610         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 18, 19,
 611                                    GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 612                                    t->wait_monitoring, GPMC_CD_CLK,
 613                                    "wait_monitoring");
 614         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 25, 26,
 615                                    GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 616                                    t->clk_activation, GPMC_CD_FCLK,
 617                                    "clk_activation");
 618         if (ret)
 619                 return -ENXIO;
 620
 621         if (IS_ENABLED(CONFIG_TI_GPMC_DEBUG)) {
 622                 pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
 623                         cs, (div * gpmc_get_fclk_period()) / 1000, div);
 624         }
 625
 626         gpmc_cs_bool_timings(cs, &t->bool_timings);
 627         gpmc_cs_show_timings(cs, "after gpmc_set_timings");
 628
 629         return 0;
 630 }
 631
 632 static int gpmc_cs_set_memconf(int cs, resource_size_t base, u32 size)
 633 {
 634         u32 l;
 635         u32 mask;
 636
 637         /*
 638          * Ensure that base address is aligned on a
 639          * boundary equal to or greater than size.
 640          */
 641         if (base & (size - 1))
 642                 return -EINVAL;
 643
 644         base >>= GPMC_CHUNK_SHIFT;
 645         mask = (1 << GPMC_SECTION_SHIFT) - size;
 646         mask >>= GPMC_CHUNK_SHIFT;
 647         mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
 648
 649         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 650         l &= ~GPMC_CONFIG7_MASK;
 651         l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
 652         l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
 653         l |= GPMC_CONFIG7_CSVALID;
 654         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 655
 656         return 0;
 657 }
 658
 659 static void gpmc_cs_enable_mem(int cs)
 660 {
 661         u32 l;
 662
 663         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 664         l |= GPMC_CONFIG7_CSVALID;
 665         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 666 }
 667
 668 static void gpmc_cs_disable_mem(int cs)
 669 {
 670         u32 l;
 671
 672         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 673         l &= ~GPMC_CONFIG7_CSVALID;
 674         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 675 }
 676
 677 static void gpmc_cs_set_reserved(int cs, int reserved)
 678 {
 679         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 680
 681         gpmc->flags |= GPMC_CS_RESERVED;
 682 }
 683
 684 static bool gpmc_cs_reserved(int cs)
 685 {
 686         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 687
 688         return gpmc->flags & GPMC_CS_RESERVED;
 689 }
 690
 691 static unsigned long gpmc_mem_align(unsigned long size)
 692 {
 693         int order;
 694
 695         size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
 696         order = GPMC_CHUNK_SHIFT - 1;
 697         do {
 698                 size >>= 1;
 699                 order++;
 700         } while (size);
 701         size = 1 << order;
 702         return size;
 703 }
 704
 705 static int gpmc_cs_request(ofnode node, int cs, struct resource *res)
 706 {
 707         int r = -1;
 708         u32 size;
 709         resource_size_t addr_base = res->start;
 710
 711         if (cs >= gpmc_cs_num) {
 712                 pr_err("%s: requested chip-select is disabled\n", __func__);
 713                 return -ENODEV;
 714         }
 715
 716         size = gpmc_mem_align(resource_size(res));
 717         if (size > (1 << GPMC_SECTION_SHIFT))
 718                 return -ENOMEM;
 719
 720         if (gpmc_cs_reserved(cs)) {
 721                 r = -EBUSY;
 722                 goto out;
 723         }
 724
 725         if (addr_base & (SZ_16M - 1)) {
 726                 pr_err("CS region should be aligned to 16M boundary\n");
 727                 goto out;
 728         }
 729
 730         /* Disable CS while changing base address and size mask */
 731         gpmc_cs_disable_mem(cs);
 732
 733         r = gpmc_cs_set_memconf(cs, addr_base, size);
 734         if (r < 0)
 735                 goto out;
 736
 737         /* Enable CS */
 738         gpmc_cs_enable_mem(cs);
 739         gpmc_cs_set_reserved(cs, 1);
 740 out:
 741         return r;
 742 }
 743
 744 static void gpmc_cs_free(int cs)
 745 {
 746         if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
 747                 pr_warn("Trying to free non-reserved GPMC CS%d\n", cs);
 748                 return;
 749         }
 750
 751         gpmc_cs_disable_mem(cs);
 752         gpmc_cs_set_reserved(cs, 0);
 753 }
 754
 755 /**
 756  * gpmc_configure - write request to configure gpmc
 757  * @cmd: command type
 758  * @wval: value to write
 759  * @return status of the operation
 760  */
 761 static int gpmc_configure(int cmd, int wval)
 762 {
 763         u32 regval;
 764
 765         switch (cmd) {
 766         case GPMC_CONFIG_WP:
 767                 regval = gpmc_read_reg(GPMC_CONFIG);
 768                 if (wval)
 769                         regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
 770                 else
 771                         regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
 772                 gpmc_write_reg(GPMC_CONFIG, regval);
 773                 break;
 774
 775         default:
 776                 pr_err("%s: command not supported\n", __func__);
 777                 return -EINVAL;
 778         }
 779
 780         return 0;
 781 }
 782
 783 /**
 784  * gpmc_cs_program_settings - programs non-timing related settings
 785  * @cs:         GPMC chip-select to program
 786  * @p:          pointer to GPMC settings structure
 787  *
 788  * Programs non-timing related settings for a GPMC chip-select, such as
 789  * bus-width, burst configuration, etc. Function should be called once
 790  * for each chip-select that is being used and must be called before
 791  * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
 792  * register will be initialised to zero by this function. Returns 0 on
 793  * success and appropriate negative error code on failure.
 794  */
 795 static int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
 796 {
 797         u32 config1;
 798
 799         if (!p->device_width || p->device_width > GPMC_DEVWIDTH_16BIT) {
 800                 pr_err("%s: invalid width %d!", __func__, p->device_width);
 801                 return -EINVAL;
 802         }
 803
 804         /* Address-data multiplexing not supported for NAND devices */
 805         if (p->device_nand && p->mux_add_data) {
 806                 pr_err("%s: invalid configuration!\n", __func__);
 807                 return -EINVAL;
 808         }
 809
 810         if (p->mux_add_data > GPMC_MUX_AD ||
 811             (p->mux_add_data == GPMC_MUX_AAD &&
 812              !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
 813                 pr_err("%s: invalid multiplex configuration!\n", __func__);
 814                 return -EINVAL;
 815         }
 816
 817         /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
 818         if (p->burst_read || p->burst_write) {
 819                 switch (p->burst_len) {
 820                 case GPMC_BURST_4:
 821                 case GPMC_BURST_8:
 822                 case GPMC_BURST_16:
 823                         break;
 824                 default:
 825                         pr_err("%s: invalid page/burst-length (%d)\n",
 826                                __func__, p->burst_len);
 827                         return -EINVAL;
 828                 }
 829         }
 830
 831         if (p->wait_pin > gpmc_nr_waitpins) {
 832                 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
 833                 return -EINVAL;
 834         }
 835
 836         config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
 837
 838         if (p->sync_read)
 839                 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
 840         if (p->sync_write)
 841                 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
 842         if (p->wait_on_read)
 843                 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
 844         if (p->wait_on_write)
 845                 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
 846         if (p->wait_on_read || p->wait_on_write)
 847                 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
 848         if (p->device_nand)
 849                 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
 850         if (p->mux_add_data)
 851                 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
 852         if (p->burst_read)
 853                 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
 854         if (p->burst_write)
 855                 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
 856         if (p->burst_read || p->burst_write) {
 857                 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
 858                 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
 859         }
 860
 861         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
 862
 863         return 0;
 864 }
 865
 866 static void gpmc_cs_set_name(int cs, const char *name)
 867 {
 868         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 869
 870         gpmc->name = name;
 871 }
 872
 873 static const char *gpmc_cs_get_name(int cs)
 874 {
 875         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 876
 877         return gpmc->name;
 878 }
 879
 880 /**
 881  * gpmc_read_settings_dt - read gpmc settings from device-tree
 882  * @np:         pointer to device-tree node for a gpmc child device
 883  * @p:          pointer to gpmc settings structure
 884  *
 885  * Reads the GPMC settings for a GPMC child device from device-tree and
 886  * stores them in the GPMC settings structure passed. The GPMC settings
 887  * structure is initialised to zero by this function and so any
 888  * previously stored settings will be cleared.
 889  */
 890 static void gpmc_read_settings_dt(ofnode np, struct gpmc_settings *p)
 891 {
 892         memset(p, 0, sizeof(struct gpmc_settings));
 893
 894         p->sync_read = ofnode_read_bool(np, "gpmc,sync-read");
 895         p->sync_write = ofnode_read_bool(np, "gpmc,sync-write");
 896         ofnode_read_u32(np, "gpmc,device-width", &p->device_width);
 897         ofnode_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
 898
 899         if (!ofnode_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
 900                 p->burst_wrap = ofnode_read_bool(np, "gpmc,burst-wrap");
 901                 p->burst_read = ofnode_read_bool(np, "gpmc,burst-read");
 902                 p->burst_write = ofnode_read_bool(np, "gpmc,burst-write");
 903                 if (!p->burst_read && !p->burst_write)
 904                         pr_warn("%s: page/burst-length set but not used!\n",
 905                                 __func__);
 906         }
 907
 908         if (!ofnode_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
 909                 p->wait_on_read = ofnode_read_bool(np,
 910                                                    "gpmc,wait-on-read");
 911                 p->wait_on_write = ofnode_read_bool(np,
 912                                                     "gpmc,wait-on-write");
 913                 if (!p->wait_on_read && !p->wait_on_write)
 914                         pr_debug("%s: rd/wr wait monitoring not enabled!\n",
 915                                  __func__);
 916         }
 917 }
 918
 919 static void gpmc_read_timings_dt(ofnode np,
 920                                  struct gpmc_timings *gpmc_t)
 921 {
 922         struct gpmc_bool_timings *p;
 923
 924         if (!gpmc_t)
 925                 return;
 926
 927         memset(gpmc_t, 0, sizeof(*gpmc_t));
 928
 929         /* minimum clock period for syncronous mode */
 930         ofnode_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
 931
 932         /* chip select timtings */
 933         ofnode_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
 934         ofnode_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
 935         ofnode_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
 936
 937         /* ADV signal timings */
 938         ofnode_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
 939         ofnode_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
 940         ofnode_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
 941         ofnode_read_u32(np, "gpmc,adv-aad-mux-on-ns",
 942                         &gpmc_t->adv_aad_mux_on);
 943         ofnode_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
 944                         &gpmc_t->adv_aad_mux_rd_off);
 945         ofnode_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
 946                         &gpmc_t->adv_aad_mux_wr_off);
 947
 948         /* WE signal timings */
 949         ofnode_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
 950         ofnode_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
 951
 952         /* OE signal timings */
 953         ofnode_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
 954         ofnode_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
 955         ofnode_read_u32(np, "gpmc,oe-aad-mux-on-ns",
 956                         &gpmc_t->oe_aad_mux_on);
 957         ofnode_read_u32(np, "gpmc,oe-aad-mux-off-ns",
 958                         &gpmc_t->oe_aad_mux_off);
 959
 960         /* access and cycle timings */
 961         ofnode_read_u32(np, "gpmc,page-burst-access-ns",
 962                         &gpmc_t->page_burst_access);
 963         ofnode_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
 964         ofnode_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
 965         ofnode_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
 966         ofnode_read_u32(np, "gpmc,bus-turnaround-ns",
 967                         &gpmc_t->bus_turnaround);
 968         ofnode_read_u32(np, "gpmc,cycle2cycle-delay-ns",
 969                         &gpmc_t->cycle2cycle_delay);
 970         ofnode_read_u32(np, "gpmc,wait-monitoring-ns",
 971                         &gpmc_t->wait_monitoring);
 972         ofnode_read_u32(np, "gpmc,clk-activation-ns",
 973                         &gpmc_t->clk_activation);
 974
 975         /* only applicable to OMAP3+ */
 976         ofnode_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
 977         ofnode_read_u32(np, "gpmc,wr-data-mux-bus-ns",
 978                         &gpmc_t->wr_data_mux_bus);
 979
 980         /* bool timing parameters */
 981         p = &gpmc_t->bool_timings;
 982
 983         p->cycle2cyclediffcsen =
 984                 ofnode_read_bool(np, "gpmc,cycle2cycle-diffcsen");
 985         p->cycle2cyclesamecsen =
 986                 ofnode_read_bool(np, "gpmc,cycle2cycle-samecsen");
 987         p->we_extra_delay = ofnode_read_bool(np, "gpmc,we-extra-delay");
 988         p->oe_extra_delay = ofnode_read_bool(np, "gpmc,oe-extra-delay");
 989         p->adv_extra_delay = ofnode_read_bool(np, "gpmc,adv-extra-delay");
 990         p->cs_extra_delay = ofnode_read_bool(np, "gpmc,cs-extra-delay");
 991         p->time_para_granularity =
 992                 ofnode_read_bool(np, "gpmc,time-para-granularity");
 993 }
 994
 995 /**
 996  * gpmc_probe_generic_child - configures the gpmc for a child device
 997  * @dev:        pointer to gpmc platform device
 998  * @child:      pointer to device-tree node for child device
 999  *
1000  * Allocates and configures a GPMC chip-select for a child device.
1001  * Returns 0 on success and appropriate negative error code on failure.
1002  */
1003 static int gpmc_probe_generic_child(struct udevice *dev,
1004                                     ofnode child)
1005 {
1006         struct gpmc_settings gpmc_s;
1007         struct gpmc_timings gpmc_t;
1008         struct resource res;
1009         const char *name;
1010         int ret;
1011         u32 val, cs;
1012
1013         if (ofnode_read_u32(child, "reg", &cs) < 0) {
1014                 dev_err(dev, "can't get reg property of child %s\n",
1015                         ofnode_get_name(child));
1016                 return -ENODEV;
1017         }
1018
1019         if (ofnode_read_resource(child, 0, &res) < 0) {
1020                 dev_err(dev, "%s has malformed 'reg' property\n",
1021                         ofnode_get_name(child));
1022                 return -ENODEV;
1023         }
1024
1025         /*
1026          * Check if we have multiple instances of the same device
1027          * on a single chip select. If so, use the already initialized
1028          * timings.
1029          */
1030         name = gpmc_cs_get_name(cs);
1031         if (name && !strcmp(name, ofnode_get_name(child)))
1032                 goto no_timings;
1033
1034         ret = gpmc_cs_request(child, cs, &res);
1035         if (ret < 0) {
1036                 dev_err(dev, "cannot request GPMC CS %d\n", cs);
1037                 return ret;
1038         }
1039         gpmc_cs_set_name(cs, ofnode_get_name(child));
1040
1041         gpmc_read_settings_dt(child, &gpmc_s);
1042         gpmc_read_timings_dt(child, &gpmc_t);
1043
1044         /*
1045          * For some GPMC devices we still need to rely on the bootloader
1046          * timings because the devices can be connected via FPGA.
1047          * REVISIT: Add timing support from slls644g.pdf.
1048          */
1049         if (!gpmc_t.cs_rd_off) {
1050                 pr_warn("enable GPMC debug to configure .dts timings for CS%i\n",
1051                         cs);
1052                 gpmc_cs_show_timings(cs,
1053                                      "please add GPMC bootloader timings to .dts");
1054                 goto no_timings;
1055         }
1056
1057         /* CS must be disabled while making changes to gpmc configuration */
1058         gpmc_cs_disable_mem(cs);
1059
1060         if (!ofnode_read_u32(child, "nand-bus-width", &val)) {
1061                 /* NAND specific setup */
1062                 ofnode_read_u32(child, "nand-bus-width", &val);
1063                 switch (val) {
1064                 case 8:
1065                         gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
1066                         break;
1067                 case 16:
1068                         gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
1069                         break;
1070                 default:
1071                         dev_err(dev, "%s: invalid 'nand-bus-width'\n",
1072                                 ofnode_get_name(child));
1073                         ret = -EINVAL;
1074                         goto err;
1075                 }
1076
1077                 /* disable write protect */
1078                 gpmc_configure(GPMC_CONFIG_WP, 0);
1079                 gpmc_s.device_nand = true;
1080         } else {
1081                 ret = ofnode_read_u32(child, "bank-width",
1082                                       &gpmc_s.device_width);
1083                 if (ret < 0 && !gpmc_s.device_width) {
1084                         dev_err(dev,
1085                                 "%s has no 'gpmc,device-width' property\n",
1086                                 ofnode_get_name(child));
1087                         goto err;
1088                 }
1089         }
1090
1091         gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
1092
1093         ret = gpmc_cs_program_settings(cs, &gpmc_s);
1094         if (ret < 0)
1095                 goto err;
1096
1097         ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
1098         if (ret) {
1099                 dev_err(dev, "failed to set gpmc timings for: %s\n",
1100                         ofnode_get_name(child));
1101                 goto err;
1102         }
1103
1104         /* Clear limited address i.e. enable A26-A11 */
1105         val = gpmc_read_reg(GPMC_CONFIG);
1106         val &= ~GPMC_CONFIG_LIMITEDADDRESS;
1107         gpmc_write_reg(GPMC_CONFIG, val);
1108
1109         /* Enable CS region */
1110         gpmc_cs_enable_mem(cs);
1111
1112 no_timings:
1113
1114         return 0;
1115
1116 err:
1117         gpmc_cs_free(cs);
1118
1119         return ret;
1120 }
1121
1122 static void gpmc_probe_dt_children(struct udevice *dev)
1123 {
1124         int ret;
1125         ofnode child;
1126
1127         ofnode_for_each_subnode(child, dev_ofnode(dev)) {
1128                 ret = gpmc_probe_generic_child(dev, child);
1129                 if (ret) {
1130                         dev_err(dev, "Cannot parse child %s:%d",
1131                                 ofnode_get_name(child), ret);
1132                 }
1133         }
1134 }
1135
1136 static int gpmc_parse_dt(struct udevice *dev, struct ti_gpmc *gpmc)
1137 {
1138         int ret;
1139         u32 val;
1140
1141         ret = ofnode_read_u32(dev_ofnode(dev), "gpmc,num-cs",
1142                               &val);
1143         if (ret < 0) {
1144                 pr_err("%s: number of chip-selects not defined\n", __func__);
1145                 return ret;
1146         } else if (val < 1) {
1147                 pr_err("%s: all chip-selects are disabled\n", __func__);
1148                 return -EINVAL;
1149         } else if (val > GPMC_CS_NUM) {
1150                 pr_err("%s: number of supported chip-selects cannot be > %d\n",
1151                        __func__, GPMC_CS_NUM);
1152                 return -EINVAL;
1153         }
1154
1155         gpmc->cs_num = val;
1156         gpmc_cs_num = val;
1157
1158         ret = ofnode_read_u32(dev_ofnode(dev), "gpmc,num-waitpins",
1159                               &gpmc->nr_waitpins);
1160         if (ret < 0) {
1161                 pr_err("%s: number of wait pins not found!\n", __func__);
1162                 return ret;
1163         }
1164
1165         gpmc_nr_waitpins = gpmc->nr_waitpins;
1166
1167         return 0;
1168 }
1169
1170 static int gpmc_probe(struct udevice *dev)
1171 {
1172         struct ti_gpmc *priv = dev_get_priv(dev);
1173         int ret;
1174         struct resource res;
1175
1176         ret = dev_read_resource_byname(dev, "cfg", &res);
1177         if (ret) {
1178                 /* Legacy DT */
1179                 dev_read_resource(dev, 0, &res);
1180                 priv->base = devm_ioremap(dev, res.start, resource_size(&res));
1181
1182                 priv->data.start = GPMC_MEM_START;
1183                 priv->data.end = GPMC_MEM_END;
1184         } else {
1185                 priv->base = devm_ioremap(dev, res.start, resource_size(&res));
1186                 ret = dev_read_resource_byname(dev, "data", &res);
1187                 if (ret)
1188                         return -ENOENT;
1189
1190                 priv->data = res;
1191         }
1192
1193         if (!priv->base)
1194                 return -ENOMEM;
1195
1196         gpmc_cfg = (struct gpmc *)priv->base;
1197         gpmc_base = priv->base;
1198
1199         priv->l3_clk = devm_clk_get(dev, "fck");
1200         if (IS_ERR(priv->l3_clk))
1201                 return PTR_ERR(priv->l3_clk);
1202
1203         if (!clk_get_rate(priv->l3_clk))
1204                 return -EINVAL;
1205
1206         gpmc_l3_clk = priv->l3_clk;
1207
1208         ret = gpmc_parse_dt(dev, priv);
1209         if (ret)
1210                 return ret;
1211
1212         priv->capability_flags = dev->driver->of_match->data;
1213         gpmc_capability = priv->capability_flags;
1214
1215         gpmc_probe_dt_children(dev);
1216
1217         return 0;
1218 }
1219
1220 #define GPMC_DATA_REV2_4 0
1221 #define GPMC_DATA_REV5 (GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS)
1222 #define GPMC_DATA_REV6 (GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS | GPMC_HAS_MUX_AAD)
1223
1224 static const struct udevice_id gpmc_dt_ids[] = {
1225         { .compatible = "ti,am64-gpmc", .data = GPMC_DATA_REV6, },
1226         { .compatible = "ti,am3352-gpmc", .data = GPMC_DATA_REV5, },
1227         { .compatible = "ti,omap2420-gpmc", .data = GPMC_DATA_REV2_4, },
1228         { .compatible = "ti,omap2430-gpmc", .data = GPMC_DATA_REV2_4, },
1229         { .compatible = "ti,omap3430-gpmc", .data = GPMC_DATA_REV5, },
1230         { .compatible = "ti,omap4430-gpmc", .data = GPMC_DATA_REV6, },
1231         { } /* sentinel */
1232 };
1233
1234 U_BOOT_DRIVER(ti_gpmc) = {
1235         .name   = "ti-gpmc",
1236         .id     = UCLASS_MEMORY,
1237         .of_match = gpmc_dt_ids,
1238         .probe  = gpmc_probe,
1239         .flags  = DM_FLAG_ALLOC_PRIV_DMA,
1240 };