drivers/memory/tegra/tegra186.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2017-2021 NVIDIA CORPORATION.  All rights reserved.
   4  */
   5
   6 #include <linux/io.h>
   7 #include <linux/iommu.h>
   8 #include <linux/module.h>
   9 #include <linux/mod_devicetable.h>
  10 #include <linux/of.h>
  11 #include <linux/of_platform.h>
  12 #include <linux/platform_device.h>
  13
  14 #include <soc/tegra/mc.h>
  15
  16 #if defined(CONFIG_ARCH_TEGRA_186_SOC)
  17 #include <dt-bindings/memory/tegra186-mc.h>
  18 #endif
  19
  20 #include "mc.h"
  21
  22 #define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0)
  23 #define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16)
  24 #define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8)
  25
  26 static int tegra186_mc_probe(struct tegra_mc *mc)
  27 {
  28         struct platform_device *pdev = to_platform_device(mc->dev);
  29         unsigned int i;
  30         char name[8];
  31         int err;
  32
  33         mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev, "broadcast");
  34         if (IS_ERR(mc->bcast_ch_regs)) {
  35                 if (PTR_ERR(mc->bcast_ch_regs) == -EINVAL) {
  36                         dev_warn(&pdev->dev,
  37                                  "Broadcast channel is missing, please update your device-tree\n");
  38                         mc->bcast_ch_regs = NULL;
  39                         goto populate;
  40                 }
  41
  42                 return PTR_ERR(mc->bcast_ch_regs);
  43         }
  44
  45         mc->ch_regs = devm_kcalloc(mc->dev, mc->soc->num_channels, sizeof(*mc->ch_regs),
  46                                    GFP_KERNEL);
  47         if (!mc->ch_regs)
  48                 return -ENOMEM;
  49
  50         for (i = 0; i < mc->soc->num_channels; i++) {
  51                 snprintf(name, sizeof(name), "ch%u", i);
  52
  53                 mc->ch_regs[i] = devm_platform_ioremap_resource_byname(pdev, name);
  54                 if (IS_ERR(mc->ch_regs[i]))
  55                         return PTR_ERR(mc->ch_regs[i]);
  56         }
  57
  58 populate:
  59         err = of_platform_populate(mc->dev->of_node, NULL, NULL, mc->dev);
  60         if (err < 0)
  61                 return err;
  62
  63         return 0;
  64 }
  65
  66 static void tegra186_mc_remove(struct tegra_mc *mc)
  67 {
  68         of_platform_depopulate(mc->dev);
  69 }
  70
  71 #if IS_ENABLED(CONFIG_IOMMU_API)
  72 static void tegra186_mc_client_sid_override(struct tegra_mc *mc,
  73                                             const struct tegra_mc_client *client,
  74                                             unsigned int sid)
  75 {
  76         u32 value, old;
  77
  78         value = readl(mc->regs + client->regs.sid.security);
  79         if ((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0) {
  80                 /*
  81                  * If the secure firmware has locked this down the override
  82                  * for this memory client, there's nothing we can do here.
  83                  */
  84                 if (value & MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED)
  85                         return;
  86
  87                 /*
  88                  * Otherwise, try to set the override itself. Typically the
  89                  * secure firmware will never have set this configuration.
  90                  * Instead, it will either have disabled write access to
  91                  * this field, or it will already have set an explicit
  92                  * override itself.
  93                  */
  94                 WARN_ON((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0);
  95
  96                 value |= MC_SID_STREAMID_SECURITY_OVERRIDE;
  97                 writel(value, mc->regs + client->regs.sid.security);
  98         }
  99
 100         value = readl(mc->regs + client->regs.sid.override);
 101         old = value & MC_SID_STREAMID_OVERRIDE_MASK;
 102
 103         if (old != sid) {
 104                 dev_dbg(mc->dev, "overriding SID %x for %s with %x\n", old,
 105                         client->name, sid);
 106                 writel(sid, mc->regs + client->regs.sid.override);
 107         }
 108 }
 109 #endif
 110
 111 static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)
 112 {
 113 #if IS_ENABLED(CONFIG_IOMMU_API)
 114         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 115         struct of_phandle_args args;
 116         unsigned int i, index = 0;
 117
 118         while (!of_parse_phandle_with_args(dev->of_node, "interconnects", "#interconnect-cells",
 119                                            index, &args)) {
 120                 if (args.np == mc->dev->of_node && args.args_count != 0) {
 121                         for (i = 0; i < mc->soc->num_clients; i++) {
 122                                 const struct tegra_mc_client *client = &mc->soc->clients[i];
 123
 124                                 if (client->id == args.args[0]) {
 125                                         u32 sid = fwspec->ids[0] & MC_SID_STREAMID_OVERRIDE_MASK;
 126
 127                                         tegra186_mc_client_sid_override(mc, client, sid);
 128                                 }
 129                         }
 130                 }
 131
 132                 index++;
 133         }
 134 #endif
 135
 136         return 0;
 137 }
 138
 139 const struct tegra_mc_ops tegra186_mc_ops = {
 140         .probe = tegra186_mc_probe,
 141         .remove = tegra186_mc_remove,
 142         .probe_device = tegra186_mc_probe_device,
 143         .handle_irq = tegra30_mc_handle_irq,
 144 };
 145
 146 #if defined(CONFIG_ARCH_TEGRA_186_SOC)
 147 static const struct tegra_mc_client tegra186_mc_clients[] = {
 148         {
 149                 .id = TEGRA186_MEMORY_CLIENT_PTCR,
 150                 .name = "ptcr",
 151                 .sid = TEGRA186_SID_PASSTHROUGH,
 152                 .regs = {
 153                         .sid = {
 154                                 .override = 0x000,
 155                                 .security = 0x004,
 156                         },
 157                 },
 158         }, {
 159                 .id = TEGRA186_MEMORY_CLIENT_AFIR,
 160                 .name = "afir",
 161                 .sid = TEGRA186_SID_AFI,
 162                 .regs = {
 163                         .sid = {
 164                                 .override = 0x070,
 165                                 .security = 0x074,
 166                         },
 167                 },
 168         }, {
 169                 .id = TEGRA186_MEMORY_CLIENT_HDAR,
 170                 .name = "hdar",
 171                 .sid = TEGRA186_SID_HDA,
 172                 .regs = {
 173                         .sid = {
 174                                 .override = 0x0a8,
 175                                 .security = 0x0ac,
 176                         },
 177                 },
 178         }, {
 179                 .id = TEGRA186_MEMORY_CLIENT_HOST1XDMAR,
 180                 .name = "host1xdmar",
 181                 .sid = TEGRA186_SID_HOST1X,
 182                 .regs = {
 183                         .sid = {
 184                                 .override = 0x0b0,
 185                                 .security = 0x0b4,
 186                         },
 187                 },
 188         }, {
 189                 .id = TEGRA186_MEMORY_CLIENT_NVENCSRD,
 190                 .name = "nvencsrd",
 191                 .sid = TEGRA186_SID_NVENC,
 192                 .regs = {
 193                         .sid = {
 194                                 .override = 0x0e0,
 195                                 .security = 0x0e4,
 196                         },
 197                 },
 198         }, {
 199                 .id = TEGRA186_MEMORY_CLIENT_SATAR,
 200                 .name = "satar",
 201                 .sid = TEGRA186_SID_SATA,
 202                 .regs = {
 203                         .sid = {
 204                                 .override = 0x0f8,
 205                                 .security = 0x0fc,
 206                         },
 207                 },
 208         }, {
 209                 .id = TEGRA186_MEMORY_CLIENT_MPCORER,
 210                 .name = "mpcorer",
 211                 .sid = TEGRA186_SID_PASSTHROUGH,
 212                 .regs = {
 213                         .sid = {
 214                                 .override = 0x138,
 215                                 .security = 0x13c,
 216                         },
 217                 },
 218         }, {
 219                 .id = TEGRA186_MEMORY_CLIENT_NVENCSWR,
 220                 .name = "nvencswr",
 221                 .sid = TEGRA186_SID_NVENC,
 222                 .regs = {
 223                         .sid = {
 224                                 .override = 0x158,
 225                                 .security = 0x15c,
 226                         },
 227                 },
 228         }, {
 229                 .id = TEGRA186_MEMORY_CLIENT_AFIW,
 230                 .name = "afiw",
 231                 .sid = TEGRA186_SID_AFI,
 232                 .regs = {
 233                         .sid = {
 234                                 .override = 0x188,
 235                                 .security = 0x18c,
 236                         },
 237                 },
 238         }, {
 239                 .id = TEGRA186_MEMORY_CLIENT_HDAW,
 240                 .name = "hdaw",
 241                 .sid = TEGRA186_SID_HDA,
 242                 .regs = {
 243                         .sid = {
 244                                 .override = 0x1a8,
 245                                 .security = 0x1ac,
 246                         },
 247                 },
 248         }, {
 249                 .id = TEGRA186_MEMORY_CLIENT_MPCOREW,
 250                 .name = "mpcorew",
 251                 .sid = TEGRA186_SID_PASSTHROUGH,
 252                 .regs = {
 253                         .sid = {
 254                                 .override = 0x1c8,
 255                                 .security = 0x1cc,
 256                         },
 257                 },
 258         }, {
 259                 .id = TEGRA186_MEMORY_CLIENT_SATAW,
 260                 .name = "sataw",
 261                 .sid = TEGRA186_SID_SATA,
 262                 .regs = {
 263                         .sid = {
 264                                 .override = 0x1e8,
 265                                 .security = 0x1ec,
 266                         },
 267                 },
 268         }, {
 269                 .id = TEGRA186_MEMORY_CLIENT_ISPRA,
 270                 .name = "ispra",
 271                 .sid = TEGRA186_SID_ISP,
 272                 .regs = {
 273                         .sid = {
 274                                 .override = 0x220,
 275                                 .security = 0x224,
 276                         },
 277                 },
 278         }, {
 279                 .id = TEGRA186_MEMORY_CLIENT_ISPWA,
 280                 .name = "ispwa",
 281                 .sid = TEGRA186_SID_ISP,
 282                 .regs = {
 283                         .sid = {
 284                                 .override = 0x230,
 285                                 .security = 0x234,
 286                         },
 287                 },
 288         }, {
 289                 .id = TEGRA186_MEMORY_CLIENT_ISPWB,
 290                 .name = "ispwb",
 291                 .sid = TEGRA186_SID_ISP,
 292                 .regs = {
 293                         .sid = {
 294                                 .override = 0x238,
 295                                 .security = 0x23c,
 296                         },
 297                 },
 298         }, {
 299                 .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTR,
 300                 .name = "xusb_hostr",
 301                 .sid = TEGRA186_SID_XUSB_HOST,
 302                 .regs = {
 303                         .sid = {
 304                                 .override = 0x250,
 305                                 .security = 0x254,
 306                         },
 307                 },
 308         }, {
 309                 .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTW,
 310                 .name = "xusb_hostw",
 311                 .sid = TEGRA186_SID_XUSB_HOST,
 312                 .regs = {
 313                         .sid = {
 314                                 .override = 0x258,
 315                                 .security = 0x25c,
 316                         },
 317                 },
 318         }, {
 319                 .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVR,
 320                 .name = "xusb_devr",
 321                 .sid = TEGRA186_SID_XUSB_DEV,
 322                 .regs = {
 323                         .sid = {
 324                                 .override = 0x260,
 325                                 .security = 0x264,
 326                         },
 327                 },
 328         }, {
 329                 .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVW,
 330                 .name = "xusb_devw",
 331                 .sid = TEGRA186_SID_XUSB_DEV,
 332                 .regs = {
 333                         .sid = {
 334                                 .override = 0x268,
 335                                 .security = 0x26c,
 336                         },
 337                 },
 338         }, {
 339                 .id = TEGRA186_MEMORY_CLIENT_TSECSRD,
 340                 .name = "tsecsrd",
 341                 .sid = TEGRA186_SID_TSEC,
 342                 .regs = {
 343                         .sid = {
 344                                 .override = 0x2a0,
 345                                 .security = 0x2a4,
 346                         },
 347                 },
 348         }, {
 349                 .id = TEGRA186_MEMORY_CLIENT_TSECSWR,
 350                 .name = "tsecswr",
 351                 .sid = TEGRA186_SID_TSEC,
 352                 .regs = {
 353                         .sid = {
 354                                 .override = 0x2a8,
 355                                 .security = 0x2ac,
 356                         },
 357                 },
 358         }, {
 359                 .id = TEGRA186_MEMORY_CLIENT_GPUSRD,
 360                 .name = "gpusrd",
 361                 .sid = TEGRA186_SID_GPU,
 362                 .regs = {
 363                         .sid = {
 364                                 .override = 0x2c0,
 365                                 .security = 0x2c4,
 366                         },
 367                 },
 368         }, {
 369                 .id = TEGRA186_MEMORY_CLIENT_GPUSWR,
 370                 .name = "gpuswr",
 371                 .sid = TEGRA186_SID_GPU,
 372                 .regs = {
 373                         .sid = {
 374                                 .override = 0x2c8,
 375                                 .security = 0x2cc,
 376                         },
 377                 },
 378         }, {
 379                 .id = TEGRA186_MEMORY_CLIENT_SDMMCRA,
 380                 .name = "sdmmcra",
 381                 .sid = TEGRA186_SID_SDMMC1,
 382                 .regs = {
 383                         .sid = {
 384                                 .override = 0x300,
 385                                 .security = 0x304,
 386                         },
 387                 },
 388         }, {
 389                 .id = TEGRA186_MEMORY_CLIENT_SDMMCRAA,
 390                 .name = "sdmmcraa",
 391                 .sid = TEGRA186_SID_SDMMC2,
 392                 .regs = {
 393                         .sid = {
 394                                 .override = 0x308,
 395                                 .security = 0x30c,
 396                         },
 397                 },
 398         }, {
 399                 .id = TEGRA186_MEMORY_CLIENT_SDMMCR,
 400                 .name = "sdmmcr",
 401                 .sid = TEGRA186_SID_SDMMC3,
 402                 .regs = {
 403                         .sid = {
 404                                 .override = 0x310,
 405                                 .security = 0x314,
 406                         },
 407                 },
 408         }, {
 409                 .id = TEGRA186_MEMORY_CLIENT_SDMMCRAB,
 410                 .name = "sdmmcrab",
 411                 .sid = TEGRA186_SID_SDMMC4,
 412                 .regs = {
 413                         .sid = {
 414                                 .override = 0x318,
 415                                 .security = 0x31c,
 416                         },
 417                 },
 418         }, {
 419                 .id = TEGRA186_MEMORY_CLIENT_SDMMCWA,
 420                 .name = "sdmmcwa",
 421                 .sid = TEGRA186_SID_SDMMC1,
 422                 .regs = {
 423                         .sid = {
 424                                 .override = 0x320,
 425                                 .security = 0x324,
 426                         },
 427                 },
 428         }, {
 429                 .id = TEGRA186_MEMORY_CLIENT_SDMMCWAA,
 430                 .name = "sdmmcwaa",
 431                 .sid = TEGRA186_SID_SDMMC2,
 432                 .regs = {
 433                         .sid = {
 434                                 .override = 0x328,
 435                                 .security = 0x32c,
 436                         },
 437                 },
 438         }, {
 439                 .id = TEGRA186_MEMORY_CLIENT_SDMMCW,
 440                 .name = "sdmmcw",
 441                 .sid = TEGRA186_SID_SDMMC3,
 442                 .regs = {
 443                         .sid = {
 444                                 .override = 0x330,
 445                                 .security = 0x334,
 446                         },
 447                 },
 448         }, {
 449                 .id = TEGRA186_MEMORY_CLIENT_SDMMCWAB,
 450                 .name = "sdmmcwab",
 451                 .sid = TEGRA186_SID_SDMMC4,
 452                 .regs = {
 453                         .sid = {
 454                                 .override = 0x338,
 455                                 .security = 0x33c,
 456                         },
 457                 },
 458         }, {
 459                 .id = TEGRA186_MEMORY_CLIENT_VICSRD,
 460                 .name = "vicsrd",
 461                 .sid = TEGRA186_SID_VIC,
 462                 .regs = {
 463                         .sid = {
 464                                 .override = 0x360,
 465                                 .security = 0x364,
 466                         },
 467                 },
 468         }, {
 469                 .id = TEGRA186_MEMORY_CLIENT_VICSWR,
 470                 .name = "vicswr",
 471                 .sid = TEGRA186_SID_VIC,
 472                 .regs = {
 473                         .sid = {
 474                                 .override = 0x368,
 475                                 .security = 0x36c,
 476                         },
 477                 },
 478         }, {
 479                 .id = TEGRA186_MEMORY_CLIENT_VIW,
 480                 .name = "viw",
 481                 .sid = TEGRA186_SID_VI,
 482                 .regs = {
 483                         .sid = {
 484                                 .override = 0x390,
 485                                 .security = 0x394,
 486                         },
 487                 },
 488         }, {
 489                 .id = TEGRA186_MEMORY_CLIENT_NVDECSRD,
 490                 .name = "nvdecsrd",
 491                 .sid = TEGRA186_SID_NVDEC,
 492                 .regs = {
 493                         .sid = {
 494                                 .override = 0x3c0,
 495                                 .security = 0x3c4,
 496                         },
 497                 },
 498         }, {
 499                 .id = TEGRA186_MEMORY_CLIENT_NVDECSWR,
 500                 .name = "nvdecswr",
 501                 .sid = TEGRA186_SID_NVDEC,
 502                 .regs = {
 503                         .sid = {
 504                                 .override = 0x3c8,
 505                                 .security = 0x3cc,
 506                         },
 507                 },
 508         }, {
 509                 .id = TEGRA186_MEMORY_CLIENT_APER,
 510                 .name = "aper",
 511                 .sid = TEGRA186_SID_APE,
 512                 .regs = {
 513                         .sid = {
 514                                 .override = 0x3d0,
 515                                 .security = 0x3d4,
 516                         },
 517                 },
 518         }, {
 519                 .id = TEGRA186_MEMORY_CLIENT_APEW,
 520                 .name = "apew",
 521                 .sid = TEGRA186_SID_APE,
 522                 .regs = {
 523                         .sid = {
 524                                 .override = 0x3d8,
 525                                 .security = 0x3dc,
 526                         },
 527                 },
 528         }, {
 529                 .id = TEGRA186_MEMORY_CLIENT_NVJPGSRD,
 530                 .name = "nvjpgsrd",
 531                 .sid = TEGRA186_SID_NVJPG,
 532                 .regs = {
 533                         .sid = {
 534                                 .override = 0x3f0,
 535                                 .security = 0x3f4,
 536                         },
 537                 },
 538         }, {
 539                 .id = TEGRA186_MEMORY_CLIENT_NVJPGSWR,
 540                 .name = "nvjpgswr",
 541                 .sid = TEGRA186_SID_NVJPG,
 542                 .regs = {
 543                         .sid = {
 544                                 .override = 0x3f8,
 545                                 .security = 0x3fc,
 546                         },
 547                 },
 548         }, {
 549                 .id = TEGRA186_MEMORY_CLIENT_SESRD,
 550                 .name = "sesrd",
 551                 .sid = TEGRA186_SID_SE,
 552                 .regs = {
 553                         .sid = {
 554                                 .override = 0x400,
 555                                 .security = 0x404,
 556                         },
 557                 },
 558         }, {
 559                 .id = TEGRA186_MEMORY_CLIENT_SESWR,
 560                 .name = "seswr",
 561                 .sid = TEGRA186_SID_SE,
 562                 .regs = {
 563                         .sid = {
 564                                 .override = 0x408,
 565                                 .security = 0x40c,
 566                         },
 567                 },
 568         }, {
 569                 .id = TEGRA186_MEMORY_CLIENT_ETRR,
 570                 .name = "etrr",
 571                 .sid = TEGRA186_SID_ETR,
 572                 .regs = {
 573                         .sid = {
 574                                 .override = 0x420,
 575                                 .security = 0x424,
 576                         },
 577                 },
 578         }, {
 579                 .id = TEGRA186_MEMORY_CLIENT_ETRW,
 580                 .name = "etrw",
 581                 .sid = TEGRA186_SID_ETR,
 582                 .regs = {
 583                         .sid = {
 584                                 .override = 0x428,
 585                                 .security = 0x42c,
 586                         },
 587                 },
 588         }, {
 589                 .id = TEGRA186_MEMORY_CLIENT_TSECSRDB,
 590                 .name = "tsecsrdb",
 591                 .sid = TEGRA186_SID_TSECB,
 592                 .regs = {
 593                         .sid = {
 594                                 .override = 0x430,
 595                                 .security = 0x434,
 596                         },
 597                 },
 598         }, {
 599                 .id = TEGRA186_MEMORY_CLIENT_TSECSWRB,
 600                 .name = "tsecswrb",
 601                 .sid = TEGRA186_SID_TSECB,
 602                 .regs = {
 603                         .sid = {
 604                                 .override = 0x438,
 605                                 .security = 0x43c,
 606                         },
 607                 },
 608         }, {
 609                 .id = TEGRA186_MEMORY_CLIENT_GPUSRD2,
 610                 .name = "gpusrd2",
 611                 .sid = TEGRA186_SID_GPU,
 612                 .regs = {
 613                         .sid = {
 614                                 .override = 0x440,
 615                                 .security = 0x444,
 616                         },
 617                 },
 618         }, {
 619                 .id = TEGRA186_MEMORY_CLIENT_GPUSWR2,
 620                 .name = "gpuswr2",
 621                 .sid = TEGRA186_SID_GPU,
 622                 .regs = {
 623                         .sid = {
 624                                 .override = 0x448,
 625                                 .security = 0x44c,
 626                         },
 627                 },
 628         }, {
 629                 .id = TEGRA186_MEMORY_CLIENT_AXISR,
 630                 .name = "axisr",
 631                 .sid = TEGRA186_SID_GPCDMA_0,
 632                 .regs = {
 633                         .sid = {
 634                                 .override = 0x460,
 635                                 .security = 0x464,
 636                         },
 637                 },
 638         }, {
 639                 .id = TEGRA186_MEMORY_CLIENT_AXISW,
 640                 .name = "axisw",
 641                 .sid = TEGRA186_SID_GPCDMA_0,
 642                 .regs = {
 643                         .sid = {
 644                                 .override = 0x468,
 645                                 .security = 0x46c,
 646                         },
 647                 },
 648         }, {
 649                 .id = TEGRA186_MEMORY_CLIENT_EQOSR,
 650                 .name = "eqosr",
 651                 .sid = TEGRA186_SID_EQOS,
 652                 .regs = {
 653                         .sid = {
 654                                 .override = 0x470,
 655                                 .security = 0x474,
 656                         },
 657                 },
 658         }, {
 659                 .id = TEGRA186_MEMORY_CLIENT_EQOSW,
 660                 .name = "eqosw",
 661                 .sid = TEGRA186_SID_EQOS,
 662                 .regs = {
 663                         .sid = {
 664                                 .override = 0x478,
 665                                 .security = 0x47c,
 666                         },
 667                 },
 668         }, {
 669                 .id = TEGRA186_MEMORY_CLIENT_UFSHCR,
 670                 .name = "ufshcr",
 671                 .sid = TEGRA186_SID_UFSHC,
 672                 .regs = {
 673                         .sid = {
 674                                 .override = 0x480,
 675                                 .security = 0x484,
 676                         },
 677                 },
 678         }, {
 679                 .id = TEGRA186_MEMORY_CLIENT_UFSHCW,
 680                 .name = "ufshcw",
 681                 .sid = TEGRA186_SID_UFSHC,
 682                 .regs = {
 683                         .sid = {
 684                                 .override = 0x488,
 685                                 .security = 0x48c,
 686                         },
 687                 },
 688         }, {
 689                 .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR,
 690                 .name = "nvdisplayr",
 691                 .sid = TEGRA186_SID_NVDISPLAY,
 692                 .regs = {
 693                         .sid = {
 694                                 .override = 0x490,
 695                                 .security = 0x494,
 696                         },
 697                 },
 698         }, {
 699                 .id = TEGRA186_MEMORY_CLIENT_BPMPR,
 700                 .name = "bpmpr",
 701                 .sid = TEGRA186_SID_BPMP,
 702                 .regs = {
 703                         .sid = {
 704                                 .override = 0x498,
 705                                 .security = 0x49c,
 706                         },
 707                 },
 708         }, {
 709                 .id = TEGRA186_MEMORY_CLIENT_BPMPW,
 710                 .name = "bpmpw",
 711                 .sid = TEGRA186_SID_BPMP,
 712                 .regs = {
 713                         .sid = {
 714                                 .override = 0x4a0,
 715                                 .security = 0x4a4,
 716                         },
 717                 },
 718         }, {
 719                 .id = TEGRA186_MEMORY_CLIENT_BPMPDMAR,
 720                 .name = "bpmpdmar",
 721                 .sid = TEGRA186_SID_BPMP,
 722                 .regs = {
 723                         .sid = {
 724                                 .override = 0x4a8,
 725                                 .security = 0x4ac,
 726                         },
 727                 },
 728         }, {
 729                 .id = TEGRA186_MEMORY_CLIENT_BPMPDMAW,
 730                 .name = "bpmpdmaw",
 731                 .sid = TEGRA186_SID_BPMP,
 732                 .regs = {
 733                         .sid = {
 734                                 .override = 0x4b0,
 735                                 .security = 0x4b4,
 736                         },
 737                 },
 738         }, {
 739                 .id = TEGRA186_MEMORY_CLIENT_AONR,
 740                 .name = "aonr",
 741                 .sid = TEGRA186_SID_AON,
 742                 .regs = {
 743                         .sid = {
 744                                 .override = 0x4b8,
 745                                 .security = 0x4bc,
 746                         },
 747                 },
 748         }, {
 749                 .id = TEGRA186_MEMORY_CLIENT_AONW,
 750                 .name = "aonw",
 751                 .sid = TEGRA186_SID_AON,
 752                 .regs = {
 753                         .sid = {
 754                                 .override = 0x4c0,
 755                                 .security = 0x4c4,
 756                         },
 757                 },
 758         }, {
 759                 .id = TEGRA186_MEMORY_CLIENT_AONDMAR,
 760                 .name = "aondmar",
 761                 .sid = TEGRA186_SID_AON,
 762                 .regs = {
 763                         .sid = {
 764                                 .override = 0x4c8,
 765                                 .security = 0x4cc,
 766                         },
 767                 },
 768         }, {
 769                 .id = TEGRA186_MEMORY_CLIENT_AONDMAW,
 770                 .name = "aondmaw",
 771                 .sid = TEGRA186_SID_AON,
 772                 .regs = {
 773                         .sid = {
 774                                 .override = 0x4d0,
 775                                 .security = 0x4d4,
 776                         },
 777                 },
 778         }, {
 779                 .id = TEGRA186_MEMORY_CLIENT_SCER,
 780                 .name = "scer",
 781                 .sid = TEGRA186_SID_SCE,
 782                 .regs = {
 783                         .sid = {
 784                                 .override = 0x4d8,
 785                                 .security = 0x4dc,
 786                         },
 787                 },
 788         }, {
 789                 .id = TEGRA186_MEMORY_CLIENT_SCEW,
 790                 .name = "scew",
 791                 .sid = TEGRA186_SID_SCE,
 792                 .regs = {
 793                         .sid = {
 794                                 .override = 0x4e0,
 795                                 .security = 0x4e4,
 796                         },
 797                 },
 798         }, {
 799                 .id = TEGRA186_MEMORY_CLIENT_SCEDMAR,
 800                 .name = "scedmar",
 801                 .sid = TEGRA186_SID_SCE,
 802                 .regs = {
 803                         .sid = {
 804                                 .override = 0x4e8,
 805                                 .security = 0x4ec,
 806                         },
 807                 },
 808         }, {
 809                 .id = TEGRA186_MEMORY_CLIENT_SCEDMAW,
 810                 .name = "scedmaw",
 811                 .sid = TEGRA186_SID_SCE,
 812                 .regs = {
 813                         .sid = {
 814                                 .override = 0x4f0,
 815                                 .security = 0x4f4,
 816                         },
 817                 },
 818         }, {
 819                 .id = TEGRA186_MEMORY_CLIENT_APEDMAR,
 820                 .name = "apedmar",
 821                 .sid = TEGRA186_SID_APE,
 822                 .regs = {
 823                         .sid = {
 824                                 .override = 0x4f8,
 825                                 .security = 0x4fc,
 826                         },
 827                 },
 828         }, {
 829                 .id = TEGRA186_MEMORY_CLIENT_APEDMAW,
 830                 .name = "apedmaw",
 831                 .sid = TEGRA186_SID_APE,
 832                 .regs = {
 833                         .sid = {
 834                                 .override = 0x500,
 835                                 .security = 0x504,
 836                         },
 837                 },
 838         }, {
 839                 .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR1,
 840                 .name = "nvdisplayr1",
 841                 .sid = TEGRA186_SID_NVDISPLAY,
 842                 .regs = {
 843                         .sid = {
 844                                 .override = 0x508,
 845                                 .security = 0x50c,
 846                         },
 847                 },
 848         }, {
 849                 .id = TEGRA186_MEMORY_CLIENT_VICSRD1,
 850                 .name = "vicsrd1",
 851                 .sid = TEGRA186_SID_VIC,
 852                 .regs = {
 853                         .sid = {
 854                                 .override = 0x510,
 855                                 .security = 0x514,
 856                         },
 857                 },
 858         }, {
 859                 .id = TEGRA186_MEMORY_CLIENT_NVDECSRD1,
 860                 .name = "nvdecsrd1",
 861                 .sid = TEGRA186_SID_NVDEC,
 862                 .regs = {
 863                         .sid = {
 864                                 .override = 0x518,
 865                                 .security = 0x51c,
 866                         },
 867                 },
 868         },
 869 };
 870
 871 const struct tegra_mc_soc tegra186_mc_soc = {
 872         .num_clients = ARRAY_SIZE(tegra186_mc_clients),
 873         .clients = tegra186_mc_clients,
 874         .num_address_bits = 40,
 875         .num_channels = 4,
 876         .client_id_mask = 0xff,
 877         .intmask = MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
 878                    MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
 879                    MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
 880         .ops = &tegra186_mc_ops,
 881         .ch_intmask = 0x0000000f,
 882         .global_intstatus_channel_shift = 0,
 883 };
 884 #endif