1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2020
6 #include <linux/bitfield.h>
8 #include <linux/mfd/syscon.h>
9 #include <linux/module.h>
10 #include <linux/of_platform.h>
11 #include <linux/pinctrl/consumer.h>
12 #include <linux/regmap.h>
13 #include <linux/reset.h>
15 /* FMC2 Controller Registers */
18 #define FMC2_BCR(x) ((x) * 0x8 + FMC2_BCR1)
19 #define FMC2_BTR(x) ((x) * 0x8 + FMC2_BTR1)
20 #define FMC2_PCSCNTR 0x20
21 #define FMC2_BWTR1 0x104
22 #define FMC2_BWTR(x) ((x) * 0x8 + FMC2_BWTR1)
24 /* Register: FMC2_BCR1 */
25 #define FMC2_BCR1_CCLKEN BIT(20)
26 #define FMC2_BCR1_FMC2EN BIT(31)
28 /* Register: FMC2_BCRx */
29 #define FMC2_BCR_MBKEN BIT(0)
30 #define FMC2_BCR_MUXEN BIT(1)
31 #define FMC2_BCR_MTYP GENMASK(3, 2)
32 #define FMC2_BCR_MWID GENMASK(5, 4)
33 #define FMC2_BCR_FACCEN BIT(6)
34 #define FMC2_BCR_BURSTEN BIT(8)
35 #define FMC2_BCR_WAITPOL BIT(9)
36 #define FMC2_BCR_WAITCFG BIT(11)
37 #define FMC2_BCR_WREN BIT(12)
38 #define FMC2_BCR_WAITEN BIT(13)
39 #define FMC2_BCR_EXTMOD BIT(14)
40 #define FMC2_BCR_ASYNCWAIT BIT(15)
41 #define FMC2_BCR_CPSIZE GENMASK(18, 16)
42 #define FMC2_BCR_CBURSTRW BIT(19)
43 #define FMC2_BCR_NBLSET GENMASK(23, 22)
45 /* Register: FMC2_BTRx/FMC2_BWTRx */
46 #define FMC2_BXTR_ADDSET GENMASK(3, 0)
47 #define FMC2_BXTR_ADDHLD GENMASK(7, 4)
48 #define FMC2_BXTR_DATAST GENMASK(15, 8)
49 #define FMC2_BXTR_BUSTURN GENMASK(19, 16)
50 #define FMC2_BTR_CLKDIV GENMASK(23, 20)
51 #define FMC2_BTR_DATLAT GENMASK(27, 24)
52 #define FMC2_BXTR_ACCMOD GENMASK(29, 28)
53 #define FMC2_BXTR_DATAHLD GENMASK(31, 30)
55 /* Register: FMC2_PCSCNTR */
56 #define FMC2_PCSCNTR_CSCOUNT GENMASK(15, 0)
57 #define FMC2_PCSCNTR_CNTBEN(x) BIT((x) + 16)
59 #define FMC2_MAX_EBI_CE 4
60 #define FMC2_MAX_BANKS 5
62 #define FMC2_BCR_CPSIZE_0 0x0
63 #define FMC2_BCR_CPSIZE_128 0x1
64 #define FMC2_BCR_CPSIZE_256 0x2
65 #define FMC2_BCR_CPSIZE_512 0x3
66 #define FMC2_BCR_CPSIZE_1024 0x4
68 #define FMC2_BCR_MWID_8 0x0
69 #define FMC2_BCR_MWID_16 0x1
71 #define FMC2_BCR_MTYP_SRAM 0x0
72 #define FMC2_BCR_MTYP_PSRAM 0x1
73 #define FMC2_BCR_MTYP_NOR 0x2
75 #define FMC2_BXTR_EXTMOD_A 0x0
76 #define FMC2_BXTR_EXTMOD_B 0x1
77 #define FMC2_BXTR_EXTMOD_C 0x2
78 #define FMC2_BXTR_EXTMOD_D 0x3
80 #define FMC2_BCR_NBLSET_MAX 0x3
81 #define FMC2_BXTR_ADDSET_MAX 0xf
82 #define FMC2_BXTR_ADDHLD_MAX 0xf
83 #define FMC2_BXTR_DATAST_MAX 0xff
84 #define FMC2_BXTR_BUSTURN_MAX 0xf
85 #define FMC2_BXTR_DATAHLD_MAX 0x3
86 #define FMC2_BTR_CLKDIV_MAX 0xf
87 #define FMC2_BTR_DATLAT_MAX 0xf
88 #define FMC2_PCSCNTR_CSCOUNT_MAX 0xff
90 enum stm32_fmc2_ebi_bank {
98 enum stm32_fmc2_ebi_register_type {
105 enum stm32_fmc2_ebi_transaction_type {
106 FMC2_ASYNC_MODE_1_SRAM = 0,
107 FMC2_ASYNC_MODE_1_PSRAM,
108 FMC2_ASYNC_MODE_A_SRAM,
109 FMC2_ASYNC_MODE_A_PSRAM,
110 FMC2_ASYNC_MODE_2_NOR,
111 FMC2_ASYNC_MODE_B_NOR,
112 FMC2_ASYNC_MODE_C_NOR,
113 FMC2_ASYNC_MODE_D_NOR,
114 FMC2_SYNC_READ_SYNC_WRITE_PSRAM,
115 FMC2_SYNC_READ_ASYNC_WRITE_PSRAM,
116 FMC2_SYNC_READ_SYNC_WRITE_NOR,
117 FMC2_SYNC_READ_ASYNC_WRITE_NOR
120 enum stm32_fmc2_ebi_buswidth {
122 FMC2_BUSWIDTH_16 = 16
125 enum stm32_fmc2_ebi_cpsize {
127 FMC2_CPSIZE_128 = 128,
128 FMC2_CPSIZE_256 = 256,
129 FMC2_CPSIZE_512 = 512,
130 FMC2_CPSIZE_1024 = 1024
133 struct stm32_fmc2_ebi {
136 struct regmap *regmap;
139 u32 bcr[FMC2_MAX_EBI_CE];
140 u32 btr[FMC2_MAX_EBI_CE];
141 u32 bwtr[FMC2_MAX_EBI_CE];
146 * struct stm32_fmc2_prop - STM32 FMC2 EBI property
147 * @name: the device tree binding name of the property
148 * @bprop: indicate that it is a boolean property
149 * @mprop: indicate that it is a mandatory property
150 * @reg_type: the register that have to be modified
151 * @reg_mask: the bit that have to be modified in the selected register
152 * in case of it is a boolean property
153 * @reset_val: the default value that have to be set in case the property
154 * has not been defined in the device tree
155 * @check: this callback ckecks that the property is compliant with the
156 * transaction type selected
157 * @calculate: this callback is called to calculate for exemple a timing
158 * set in nanoseconds in the device tree in clock cycles or in
160 * @set: this callback applies the values in the registers
162 struct stm32_fmc2_prop {
169 int (*check)(struct stm32_fmc2_ebi *ebi,
170 const struct stm32_fmc2_prop *prop, int cs);
171 u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
172 int (*set)(struct stm32_fmc2_ebi *ebi,
173 const struct stm32_fmc2_prop *prop,
177 static int stm32_fmc2_ebi_check_mux(struct stm32_fmc2_ebi *ebi,
178 const struct stm32_fmc2_prop *prop,
183 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
185 if (bcr & FMC2_BCR_MTYP)
191 static int stm32_fmc2_ebi_check_waitcfg(struct stm32_fmc2_ebi *ebi,
192 const struct stm32_fmc2_prop *prop,
195 u32 bcr, val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
197 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
199 if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN)
205 static int stm32_fmc2_ebi_check_sync_trans(struct stm32_fmc2_ebi *ebi,
206 const struct stm32_fmc2_prop *prop,
211 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
213 if (bcr & FMC2_BCR_BURSTEN)
219 static int stm32_fmc2_ebi_check_async_trans(struct stm32_fmc2_ebi *ebi,
220 const struct stm32_fmc2_prop *prop,
225 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
227 if (!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW))
233 static int stm32_fmc2_ebi_check_cpsize(struct stm32_fmc2_ebi *ebi,
234 const struct stm32_fmc2_prop *prop,
237 u32 bcr, val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
239 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
241 if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN)
247 static int stm32_fmc2_ebi_check_address_hold(struct stm32_fmc2_ebi *ebi,
248 const struct stm32_fmc2_prop *prop,
251 u32 bcr, bxtr, val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
253 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
254 if (prop->reg_type == FMC2_REG_BWTR)
255 regmap_read(ebi->regmap, FMC2_BWTR(cs), &bxtr);
257 regmap_read(ebi->regmap, FMC2_BTR(cs), &bxtr);
259 if ((!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW)) &&
260 ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN))
266 static int stm32_fmc2_ebi_check_clk_period(struct stm32_fmc2_ebi *ebi,
267 const struct stm32_fmc2_prop *prop,
272 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
274 regmap_read(ebi->regmap, FMC2_BCR1, &bcr1);
278 if (bcr & FMC2_BCR_BURSTEN && (!cs || !(bcr1 & FMC2_BCR1_CCLKEN)))
284 static int stm32_fmc2_ebi_check_cclk(struct stm32_fmc2_ebi *ebi,
285 const struct stm32_fmc2_prop *prop,
291 return stm32_fmc2_ebi_check_sync_trans(ebi, prop, cs);
294 static u32 stm32_fmc2_ebi_ns_to_clock_cycles(struct stm32_fmc2_ebi *ebi,
297 unsigned long hclk = clk_get_rate(ebi->clk);
298 unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000);
300 return DIV_ROUND_UP(setup * 1000, hclkp);
303 static u32 stm32_fmc2_ebi_ns_to_clk_period(struct stm32_fmc2_ebi *ebi,
306 u32 nb_clk_cycles = stm32_fmc2_ebi_ns_to_clock_cycles(ebi, cs, setup);
307 u32 bcr, btr, clk_period;
309 regmap_read(ebi->regmap, FMC2_BCR1, &bcr);
310 if (bcr & FMC2_BCR1_CCLKEN || !cs)
311 regmap_read(ebi->regmap, FMC2_BTR1, &btr);
313 regmap_read(ebi->regmap, FMC2_BTR(cs), &btr);
315 clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1;
317 return DIV_ROUND_UP(nb_clk_cycles, clk_period);
320 static int stm32_fmc2_ebi_get_reg(int reg_type, int cs, u32 *reg)
330 *reg = FMC2_BWTR(cs);
332 case FMC2_REG_PCSCNTR:
342 static int stm32_fmc2_ebi_set_bit_field(struct stm32_fmc2_ebi *ebi,
343 const struct stm32_fmc2_prop *prop,
349 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®);
353 regmap_update_bits(ebi->regmap, reg, prop->reg_mask,
354 setup ? prop->reg_mask : 0);
359 static int stm32_fmc2_ebi_set_trans_type(struct stm32_fmc2_ebi *ebi,
360 const struct stm32_fmc2_prop *prop,
363 u32 bcr_mask, bcr = FMC2_BCR_WREN;
364 u32 btr_mask, btr = 0;
365 u32 bwtr_mask, bwtr = 0;
367 bwtr_mask = FMC2_BXTR_ACCMOD;
368 btr_mask = FMC2_BXTR_ACCMOD;
369 bcr_mask = FMC2_BCR_MUXEN | FMC2_BCR_MTYP | FMC2_BCR_FACCEN |
370 FMC2_BCR_WREN | FMC2_BCR_WAITEN | FMC2_BCR_BURSTEN |
371 FMC2_BCR_EXTMOD | FMC2_BCR_CBURSTRW;
374 case FMC2_ASYNC_MODE_1_SRAM:
375 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM);
377 * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
378 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
381 case FMC2_ASYNC_MODE_1_PSRAM:
383 * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
384 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
386 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
388 case FMC2_ASYNC_MODE_A_SRAM:
390 * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
391 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0
393 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM);
394 bcr |= FMC2_BCR_EXTMOD;
395 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
396 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
398 case FMC2_ASYNC_MODE_A_PSRAM:
400 * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
401 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0
403 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
404 bcr |= FMC2_BCR_EXTMOD;
405 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
406 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
408 case FMC2_ASYNC_MODE_2_NOR:
410 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
411 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
413 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
414 bcr |= FMC2_BCR_FACCEN;
416 case FMC2_ASYNC_MODE_B_NOR:
418 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
419 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 1
421 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
422 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
423 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B);
424 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B);
426 case FMC2_ASYNC_MODE_C_NOR:
428 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
429 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 2
431 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
432 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
433 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C);
434 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C);
436 case FMC2_ASYNC_MODE_D_NOR:
438 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
439 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 3
441 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
442 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
443 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
444 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
446 case FMC2_SYNC_READ_SYNC_WRITE_PSRAM:
448 * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0,
449 * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0
451 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
452 bcr |= FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW;
454 case FMC2_SYNC_READ_ASYNC_WRITE_PSRAM:
456 * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0,
457 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
459 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
460 bcr |= FMC2_BCR_BURSTEN;
462 case FMC2_SYNC_READ_SYNC_WRITE_NOR:
464 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0,
465 * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0
467 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
468 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW;
470 case FMC2_SYNC_READ_ASYNC_WRITE_NOR:
472 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0,
473 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
475 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
476 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN;
479 /* Type of transaction not supported */
483 if (bcr & FMC2_BCR_EXTMOD)
484 regmap_update_bits(ebi->regmap, FMC2_BWTR(cs),
486 regmap_update_bits(ebi->regmap, FMC2_BTR(cs), btr_mask, btr);
487 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), bcr_mask, bcr);
492 static int stm32_fmc2_ebi_set_buswidth(struct stm32_fmc2_ebi *ebi,
493 const struct stm32_fmc2_prop *prop,
499 case FMC2_BUSWIDTH_8:
500 val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_8);
502 case FMC2_BUSWIDTH_16:
503 val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_16);
506 /* Buswidth not supported */
510 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_MWID, val);
515 static int stm32_fmc2_ebi_set_cpsize(struct stm32_fmc2_ebi *ebi,
516 const struct stm32_fmc2_prop *prop,
523 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_0);
525 case FMC2_CPSIZE_128:
526 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_128);
528 case FMC2_CPSIZE_256:
529 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_256);
531 case FMC2_CPSIZE_512:
532 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_512);
534 case FMC2_CPSIZE_1024:
535 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_1024);
538 /* Cpsize not supported */
542 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_CPSIZE, val);
547 static int stm32_fmc2_ebi_set_bl_setup(struct stm32_fmc2_ebi *ebi,
548 const struct stm32_fmc2_prop *prop,
553 val = min_t(u32, setup, FMC2_BCR_NBLSET_MAX);
554 val = FIELD_PREP(FMC2_BCR_NBLSET, val);
555 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_NBLSET, val);
560 static int stm32_fmc2_ebi_set_address_setup(struct stm32_fmc2_ebi *ebi,
561 const struct stm32_fmc2_prop *prop,
565 u32 val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
568 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®);
572 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
573 if (prop->reg_type == FMC2_REG_BWTR)
574 regmap_read(ebi->regmap, FMC2_BWTR(cs), &bxtr);
576 regmap_read(ebi->regmap, FMC2_BTR(cs), &bxtr);
578 if ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN)
579 val = clamp_val(setup, 1, FMC2_BXTR_ADDSET_MAX);
581 val = min_t(u32, setup, FMC2_BXTR_ADDSET_MAX);
582 val = FIELD_PREP(FMC2_BXTR_ADDSET, val);
583 regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_ADDSET, val);
588 static int stm32_fmc2_ebi_set_address_hold(struct stm32_fmc2_ebi *ebi,
589 const struct stm32_fmc2_prop *prop,
595 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®);
599 val = clamp_val(setup, 1, FMC2_BXTR_ADDHLD_MAX);
600 val = FIELD_PREP(FMC2_BXTR_ADDHLD, val);
601 regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_ADDHLD, val);
606 static int stm32_fmc2_ebi_set_data_setup(struct stm32_fmc2_ebi *ebi,
607 const struct stm32_fmc2_prop *prop,
613 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®);
617 val = clamp_val(setup, 1, FMC2_BXTR_DATAST_MAX);
618 val = FIELD_PREP(FMC2_BXTR_DATAST, val);
619 regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_DATAST, val);
624 static int stm32_fmc2_ebi_set_bus_turnaround(struct stm32_fmc2_ebi *ebi,
625 const struct stm32_fmc2_prop *prop,
631 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®);
635 val = setup ? min_t(u32, setup - 1, FMC2_BXTR_BUSTURN_MAX) : 0;
636 val = FIELD_PREP(FMC2_BXTR_BUSTURN, val);
637 regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_BUSTURN, val);
642 static int stm32_fmc2_ebi_set_data_hold(struct stm32_fmc2_ebi *ebi,
643 const struct stm32_fmc2_prop *prop,
649 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®);
653 if (prop->reg_type == FMC2_REG_BWTR)
654 val = setup ? min_t(u32, setup - 1, FMC2_BXTR_DATAHLD_MAX) : 0;
656 val = min_t(u32, setup, FMC2_BXTR_DATAHLD_MAX);
657 val = FIELD_PREP(FMC2_BXTR_DATAHLD, val);
658 regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_DATAHLD, val);
663 static int stm32_fmc2_ebi_set_clk_period(struct stm32_fmc2_ebi *ebi,
664 const struct stm32_fmc2_prop *prop,
669 val = setup ? clamp_val(setup - 1, 1, FMC2_BTR_CLKDIV_MAX) : 1;
670 val = FIELD_PREP(FMC2_BTR_CLKDIV, val);
671 regmap_update_bits(ebi->regmap, FMC2_BTR(cs), FMC2_BTR_CLKDIV, val);
676 static int stm32_fmc2_ebi_set_data_latency(struct stm32_fmc2_ebi *ebi,
677 const struct stm32_fmc2_prop *prop,
682 val = setup > 1 ? min_t(u32, setup - 2, FMC2_BTR_DATLAT_MAX) : 0;
683 val = FIELD_PREP(FMC2_BTR_DATLAT, val);
684 regmap_update_bits(ebi->regmap, FMC2_BTR(cs), FMC2_BTR_DATLAT, val);
689 static int stm32_fmc2_ebi_set_max_low_pulse(struct stm32_fmc2_ebi *ebi,
690 const struct stm32_fmc2_prop *prop,
693 u32 old_val, new_val, pcscntr;
698 regmap_read(ebi->regmap, FMC2_PCSCNTR, &pcscntr);
700 /* Enable counter for the bank */
701 regmap_update_bits(ebi->regmap, FMC2_PCSCNTR,
702 FMC2_PCSCNTR_CNTBEN(cs),
703 FMC2_PCSCNTR_CNTBEN(cs));
705 new_val = min_t(u32, setup - 1, FMC2_PCSCNTR_CSCOUNT_MAX);
706 old_val = FIELD_GET(FMC2_PCSCNTR_CSCOUNT, pcscntr);
707 if (old_val && new_val > old_val)
708 /* Keep current counter value */
711 new_val = FIELD_PREP(FMC2_PCSCNTR_CSCOUNT, new_val);
712 regmap_update_bits(ebi->regmap, FMC2_PCSCNTR,
713 FMC2_PCSCNTR_CSCOUNT, new_val);
718 static const struct stm32_fmc2_prop stm32_fmc2_child_props[] = {
719 /* st,fmc2-ebi-cs-trans-type must be the first property */
721 .name = "st,fmc2-ebi-cs-transaction-type",
723 .set = stm32_fmc2_ebi_set_trans_type,
726 .name = "st,fmc2-ebi-cs-cclk-enable",
728 .reg_type = FMC2_REG_BCR,
729 .reg_mask = FMC2_BCR1_CCLKEN,
730 .check = stm32_fmc2_ebi_check_cclk,
731 .set = stm32_fmc2_ebi_set_bit_field,
734 .name = "st,fmc2-ebi-cs-mux-enable",
736 .reg_type = FMC2_REG_BCR,
737 .reg_mask = FMC2_BCR_MUXEN,
738 .check = stm32_fmc2_ebi_check_mux,
739 .set = stm32_fmc2_ebi_set_bit_field,
742 .name = "st,fmc2-ebi-cs-buswidth",
743 .reset_val = FMC2_BUSWIDTH_16,
744 .set = stm32_fmc2_ebi_set_buswidth,
747 .name = "st,fmc2-ebi-cs-waitpol-high",
749 .reg_type = FMC2_REG_BCR,
750 .reg_mask = FMC2_BCR_WAITPOL,
751 .set = stm32_fmc2_ebi_set_bit_field,
754 .name = "st,fmc2-ebi-cs-waitcfg-enable",
756 .reg_type = FMC2_REG_BCR,
757 .reg_mask = FMC2_BCR_WAITCFG,
758 .check = stm32_fmc2_ebi_check_waitcfg,
759 .set = stm32_fmc2_ebi_set_bit_field,
762 .name = "st,fmc2-ebi-cs-wait-enable",
764 .reg_type = FMC2_REG_BCR,
765 .reg_mask = FMC2_BCR_WAITEN,
766 .check = stm32_fmc2_ebi_check_sync_trans,
767 .set = stm32_fmc2_ebi_set_bit_field,
770 .name = "st,fmc2-ebi-cs-asyncwait-enable",
772 .reg_type = FMC2_REG_BCR,
773 .reg_mask = FMC2_BCR_ASYNCWAIT,
774 .check = stm32_fmc2_ebi_check_async_trans,
775 .set = stm32_fmc2_ebi_set_bit_field,
778 .name = "st,fmc2-ebi-cs-cpsize",
779 .check = stm32_fmc2_ebi_check_cpsize,
780 .set = stm32_fmc2_ebi_set_cpsize,
783 .name = "st,fmc2-ebi-cs-byte-lane-setup-ns",
784 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
785 .set = stm32_fmc2_ebi_set_bl_setup,
788 .name = "st,fmc2-ebi-cs-address-setup-ns",
789 .reg_type = FMC2_REG_BTR,
790 .reset_val = FMC2_BXTR_ADDSET_MAX,
791 .check = stm32_fmc2_ebi_check_async_trans,
792 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
793 .set = stm32_fmc2_ebi_set_address_setup,
796 .name = "st,fmc2-ebi-cs-address-hold-ns",
797 .reg_type = FMC2_REG_BTR,
798 .reset_val = FMC2_BXTR_ADDHLD_MAX,
799 .check = stm32_fmc2_ebi_check_address_hold,
800 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
801 .set = stm32_fmc2_ebi_set_address_hold,
804 .name = "st,fmc2-ebi-cs-data-setup-ns",
805 .reg_type = FMC2_REG_BTR,
806 .reset_val = FMC2_BXTR_DATAST_MAX,
807 .check = stm32_fmc2_ebi_check_async_trans,
808 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
809 .set = stm32_fmc2_ebi_set_data_setup,
812 .name = "st,fmc2-ebi-cs-bus-turnaround-ns",
813 .reg_type = FMC2_REG_BTR,
814 .reset_val = FMC2_BXTR_BUSTURN_MAX + 1,
815 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
816 .set = stm32_fmc2_ebi_set_bus_turnaround,
819 .name = "st,fmc2-ebi-cs-data-hold-ns",
820 .reg_type = FMC2_REG_BTR,
821 .check = stm32_fmc2_ebi_check_async_trans,
822 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
823 .set = stm32_fmc2_ebi_set_data_hold,
826 .name = "st,fmc2-ebi-cs-clk-period-ns",
827 .reset_val = FMC2_BTR_CLKDIV_MAX + 1,
828 .check = stm32_fmc2_ebi_check_clk_period,
829 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
830 .set = stm32_fmc2_ebi_set_clk_period,
833 .name = "st,fmc2-ebi-cs-data-latency-ns",
834 .check = stm32_fmc2_ebi_check_sync_trans,
835 .calculate = stm32_fmc2_ebi_ns_to_clk_period,
836 .set = stm32_fmc2_ebi_set_data_latency,
839 .name = "st,fmc2-ebi-cs-write-address-setup-ns",
840 .reg_type = FMC2_REG_BWTR,
841 .reset_val = FMC2_BXTR_ADDSET_MAX,
842 .check = stm32_fmc2_ebi_check_async_trans,
843 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
844 .set = stm32_fmc2_ebi_set_address_setup,
847 .name = "st,fmc2-ebi-cs-write-address-hold-ns",
848 .reg_type = FMC2_REG_BWTR,
849 .reset_val = FMC2_BXTR_ADDHLD_MAX,
850 .check = stm32_fmc2_ebi_check_address_hold,
851 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
852 .set = stm32_fmc2_ebi_set_address_hold,
855 .name = "st,fmc2-ebi-cs-write-data-setup-ns",
856 .reg_type = FMC2_REG_BWTR,
857 .reset_val = FMC2_BXTR_DATAST_MAX,
858 .check = stm32_fmc2_ebi_check_async_trans,
859 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
860 .set = stm32_fmc2_ebi_set_data_setup,
863 .name = "st,fmc2-ebi-cs-write-bus-turnaround-ns",
864 .reg_type = FMC2_REG_BWTR,
865 .reset_val = FMC2_BXTR_BUSTURN_MAX + 1,
866 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
867 .set = stm32_fmc2_ebi_set_bus_turnaround,
870 .name = "st,fmc2-ebi-cs-write-data-hold-ns",
871 .reg_type = FMC2_REG_BWTR,
872 .check = stm32_fmc2_ebi_check_async_trans,
873 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
874 .set = stm32_fmc2_ebi_set_data_hold,
877 .name = "st,fmc2-ebi-cs-max-low-pulse-ns",
878 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
879 .set = stm32_fmc2_ebi_set_max_low_pulse,
883 static int stm32_fmc2_ebi_parse_prop(struct stm32_fmc2_ebi *ebi,
884 struct device_node *dev_node,
885 const struct stm32_fmc2_prop *prop,
888 struct device *dev = ebi->dev;
892 dev_err(dev, "property %s is not well defined\n", prop->name);
896 if (prop->check && prop->check(ebi, prop, cs))
897 /* Skeep this property */
903 bprop = of_property_read_bool(dev_node, prop->name);
904 if (prop->mprop && !bprop) {
905 dev_err(dev, "mandatory property %s not defined in the device tree\n",
916 ret = of_property_read_u32(dev_node, prop->name, &val);
917 if (prop->mprop && ret) {
918 dev_err(dev, "mandatory property %s not defined in the device tree\n",
924 setup = prop->reset_val;
925 else if (prop->calculate)
926 setup = prop->calculate(ebi, cs, val);
931 return prop->set(ebi, prop, cs, setup);
934 static void stm32_fmc2_ebi_enable_bank(struct stm32_fmc2_ebi *ebi, int cs)
936 regmap_update_bits(ebi->regmap, FMC2_BCR(cs),
937 FMC2_BCR_MBKEN, FMC2_BCR_MBKEN);
940 static void stm32_fmc2_ebi_disable_bank(struct stm32_fmc2_ebi *ebi, int cs)
942 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_MBKEN, 0);
945 static void stm32_fmc2_ebi_save_setup(struct stm32_fmc2_ebi *ebi)
949 for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
950 regmap_read(ebi->regmap, FMC2_BCR(cs), &ebi->bcr[cs]);
951 regmap_read(ebi->regmap, FMC2_BTR(cs), &ebi->btr[cs]);
952 regmap_read(ebi->regmap, FMC2_BWTR(cs), &ebi->bwtr[cs]);
955 regmap_read(ebi->regmap, FMC2_PCSCNTR, &ebi->pcscntr);
958 static void stm32_fmc2_ebi_set_setup(struct stm32_fmc2_ebi *ebi)
962 for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
963 regmap_write(ebi->regmap, FMC2_BCR(cs), ebi->bcr[cs]);
964 regmap_write(ebi->regmap, FMC2_BTR(cs), ebi->btr[cs]);
965 regmap_write(ebi->regmap, FMC2_BWTR(cs), ebi->bwtr[cs]);
968 regmap_write(ebi->regmap, FMC2_PCSCNTR, ebi->pcscntr);
971 static void stm32_fmc2_ebi_disable_banks(struct stm32_fmc2_ebi *ebi)
975 for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
976 if (!(ebi->bank_assigned & BIT(cs)))
979 stm32_fmc2_ebi_disable_bank(ebi, cs);
983 /* NWAIT signal can not be connected to EBI controller and NAND controller */
984 static bool stm32_fmc2_ebi_nwait_used_by_ctrls(struct stm32_fmc2_ebi *ebi)
989 for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
990 if (!(ebi->bank_assigned & BIT(cs)))
993 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
994 if ((bcr & FMC2_BCR_WAITEN || bcr & FMC2_BCR_ASYNCWAIT) &&
995 ebi->bank_assigned & BIT(FMC2_NAND))
1002 static void stm32_fmc2_ebi_enable(struct stm32_fmc2_ebi *ebi)
1004 regmap_update_bits(ebi->regmap, FMC2_BCR1,
1005 FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN);
1008 static void stm32_fmc2_ebi_disable(struct stm32_fmc2_ebi *ebi)
1010 regmap_update_bits(ebi->regmap, FMC2_BCR1, FMC2_BCR1_FMC2EN, 0);
1013 static int stm32_fmc2_ebi_setup_cs(struct stm32_fmc2_ebi *ebi,
1014 struct device_node *dev_node,
1020 stm32_fmc2_ebi_disable_bank(ebi, cs);
1022 for (i = 0; i < ARRAY_SIZE(stm32_fmc2_child_props); i++) {
1023 const struct stm32_fmc2_prop *p = &stm32_fmc2_child_props[i];
1025 ret = stm32_fmc2_ebi_parse_prop(ebi, dev_node, p, cs);
1027 dev_err(ebi->dev, "property %s could not be set: %d\n",
1033 stm32_fmc2_ebi_enable_bank(ebi, cs);
1038 static int stm32_fmc2_ebi_parse_dt(struct stm32_fmc2_ebi *ebi)
1040 struct device *dev = ebi->dev;
1041 struct device_node *child;
1042 bool child_found = false;
1046 for_each_available_child_of_node(dev->of_node, child) {
1047 ret = of_property_read_u32(child, "reg", &bank);
1049 dev_err(dev, "could not retrieve reg property: %d\n",
1055 if (bank >= FMC2_MAX_BANKS) {
1056 dev_err(dev, "invalid reg value: %d\n", bank);
1061 if (ebi->bank_assigned & BIT(bank)) {
1062 dev_err(dev, "bank already assigned: %d\n", bank);
1067 if (bank < FMC2_MAX_EBI_CE) {
1068 ret = stm32_fmc2_ebi_setup_cs(ebi, child, bank);
1070 dev_err(dev, "setup chip select %d failed: %d\n",
1077 ebi->bank_assigned |= BIT(bank);
1082 dev_warn(dev, "no subnodes found, disable the driver.\n");
1086 if (stm32_fmc2_ebi_nwait_used_by_ctrls(ebi)) {
1087 dev_err(dev, "NWAIT signal connected to EBI and NAND controllers\n");
1091 stm32_fmc2_ebi_enable(ebi);
1093 return of_platform_populate(dev->of_node, NULL, NULL, dev);
1096 static int stm32_fmc2_ebi_probe(struct platform_device *pdev)
1098 struct device *dev = &pdev->dev;
1099 struct stm32_fmc2_ebi *ebi;
1100 struct reset_control *rstc;
1103 ebi = devm_kzalloc(&pdev->dev, sizeof(*ebi), GFP_KERNEL);
1109 ebi->regmap = device_node_to_regmap(dev->of_node);
1110 if (IS_ERR(ebi->regmap))
1111 return PTR_ERR(ebi->regmap);
1113 ebi->clk = devm_clk_get(dev, NULL);
1114 if (IS_ERR(ebi->clk))
1115 return PTR_ERR(ebi->clk);
1117 rstc = devm_reset_control_get(dev, NULL);
1118 if (PTR_ERR(rstc) == -EPROBE_DEFER)
1119 return -EPROBE_DEFER;
1121 ret = clk_prepare_enable(ebi->clk);
1125 if (!IS_ERR(rstc)) {
1126 reset_control_assert(rstc);
1127 reset_control_deassert(rstc);
1130 ret = stm32_fmc2_ebi_parse_dt(ebi);
1134 stm32_fmc2_ebi_save_setup(ebi);
1135 platform_set_drvdata(pdev, ebi);
1140 stm32_fmc2_ebi_disable_banks(ebi);
1141 stm32_fmc2_ebi_disable(ebi);
1142 clk_disable_unprepare(ebi->clk);
1147 static int stm32_fmc2_ebi_remove(struct platform_device *pdev)
1149 struct stm32_fmc2_ebi *ebi = platform_get_drvdata(pdev);
1151 of_platform_depopulate(&pdev->dev);
1152 stm32_fmc2_ebi_disable_banks(ebi);
1153 stm32_fmc2_ebi_disable(ebi);
1154 clk_disable_unprepare(ebi->clk);
1159 static int __maybe_unused stm32_fmc2_ebi_suspend(struct device *dev)
1161 struct stm32_fmc2_ebi *ebi = dev_get_drvdata(dev);
1163 stm32_fmc2_ebi_disable(ebi);
1164 clk_disable_unprepare(ebi->clk);
1165 pinctrl_pm_select_sleep_state(dev);
1170 static int __maybe_unused stm32_fmc2_ebi_resume(struct device *dev)
1172 struct stm32_fmc2_ebi *ebi = dev_get_drvdata(dev);
1175 pinctrl_pm_select_default_state(dev);
1177 ret = clk_prepare_enable(ebi->clk);
1181 stm32_fmc2_ebi_set_setup(ebi);
1182 stm32_fmc2_ebi_enable(ebi);
1187 static SIMPLE_DEV_PM_OPS(stm32_fmc2_ebi_pm_ops, stm32_fmc2_ebi_suspend,
1188 stm32_fmc2_ebi_resume);
1190 static const struct of_device_id stm32_fmc2_ebi_match[] = {
1191 {.compatible = "st,stm32mp1-fmc2-ebi"},
1194 MODULE_DEVICE_TABLE(of, stm32_fmc2_ebi_match);
1196 static struct platform_driver stm32_fmc2_ebi_driver = {
1197 .probe = stm32_fmc2_ebi_probe,
1198 .remove = stm32_fmc2_ebi_remove,
1200 .name = "stm32_fmc2_ebi",
1201 .of_match_table = stm32_fmc2_ebi_match,
1202 .pm = &stm32_fmc2_ebi_pm_ops,
1205 module_platform_driver(stm32_fmc2_ebi_driver);
1207 MODULE_ALIAS("platform:stm32_fmc2_ebi");
1208 MODULE_AUTHOR("Christophe Kerello <christophe.kerello@st.com>");
1209 MODULE_DESCRIPTION("STMicroelectronics STM32 FMC2 ebi driver");
1210 MODULE_LICENSE("GPL v2");