drivers/memory/stm32-fmc2-ebi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics 2020
   4  */
   5
   6 #include <linux/bitfield.h>
   7 #include <linux/clk.h>
   8 #include <linux/mfd/syscon.h>
   9 #include <linux/module.h>
  10 #include <linux/of_platform.h>
  11 #include <linux/pinctrl/consumer.h>
  12 #include <linux/regmap.h>
  13 #include <linux/reset.h>
  14
  15 /* FMC2 Controller Registers */
  16 #define FMC2_BCR1                       0x0
  17 #define FMC2_BTR1                       0x4
  18 #define FMC2_BCR(x)                     ((x) * 0x8 + FMC2_BCR1)
  19 #define FMC2_BTR(x)                     ((x) * 0x8 + FMC2_BTR1)
  20 #define FMC2_PCSCNTR                    0x20
  21 #define FMC2_BWTR1                      0x104
  22 #define FMC2_BWTR(x)                    ((x) * 0x8 + FMC2_BWTR1)
  23
  24 /* Register: FMC2_BCR1 */
  25 #define FMC2_BCR1_CCLKEN                BIT(20)
  26 #define FMC2_BCR1_FMC2EN                BIT(31)
  27
  28 /* Register: FMC2_BCRx */
  29 #define FMC2_BCR_MBKEN                  BIT(0)
  30 #define FMC2_BCR_MUXEN                  BIT(1)
  31 #define FMC2_BCR_MTYP                   GENMASK(3, 2)
  32 #define FMC2_BCR_MWID                   GENMASK(5, 4)
  33 #define FMC2_BCR_FACCEN                 BIT(6)
  34 #define FMC2_BCR_BURSTEN                BIT(8)
  35 #define FMC2_BCR_WAITPOL                BIT(9)
  36 #define FMC2_BCR_WAITCFG                BIT(11)
  37 #define FMC2_BCR_WREN                   BIT(12)
  38 #define FMC2_BCR_WAITEN                 BIT(13)
  39 #define FMC2_BCR_EXTMOD                 BIT(14)
  40 #define FMC2_BCR_ASYNCWAIT              BIT(15)
  41 #define FMC2_BCR_CPSIZE                 GENMASK(18, 16)
  42 #define FMC2_BCR_CBURSTRW               BIT(19)
  43 #define FMC2_BCR_NBLSET                 GENMASK(23, 22)
  44
  45 /* Register: FMC2_BTRx/FMC2_BWTRx */
  46 #define FMC2_BXTR_ADDSET                GENMASK(3, 0)
  47 #define FMC2_BXTR_ADDHLD                GENMASK(7, 4)
  48 #define FMC2_BXTR_DATAST                GENMASK(15, 8)
  49 #define FMC2_BXTR_BUSTURN               GENMASK(19, 16)
  50 #define FMC2_BTR_CLKDIV                 GENMASK(23, 20)
  51 #define FMC2_BTR_DATLAT                 GENMASK(27, 24)
  52 #define FMC2_BXTR_ACCMOD                GENMASK(29, 28)
  53 #define FMC2_BXTR_DATAHLD               GENMASK(31, 30)
  54
  55 /* Register: FMC2_PCSCNTR */
  56 #define FMC2_PCSCNTR_CSCOUNT            GENMASK(15, 0)
  57 #define FMC2_PCSCNTR_CNTBEN(x)          BIT((x) + 16)
  58
  59 #define FMC2_MAX_EBI_CE                 4
  60 #define FMC2_MAX_BANKS                  5
  61
  62 #define FMC2_BCR_CPSIZE_0               0x0
  63 #define FMC2_BCR_CPSIZE_128             0x1
  64 #define FMC2_BCR_CPSIZE_256             0x2
  65 #define FMC2_BCR_CPSIZE_512             0x3
  66 #define FMC2_BCR_CPSIZE_1024            0x4
  67
  68 #define FMC2_BCR_MWID_8                 0x0
  69 #define FMC2_BCR_MWID_16                0x1
  70
  71 #define FMC2_BCR_MTYP_SRAM              0x0
  72 #define FMC2_BCR_MTYP_PSRAM             0x1
  73 #define FMC2_BCR_MTYP_NOR               0x2
  74
  75 #define FMC2_BXTR_EXTMOD_A              0x0
  76 #define FMC2_BXTR_EXTMOD_B              0x1
  77 #define FMC2_BXTR_EXTMOD_C              0x2
  78 #define FMC2_BXTR_EXTMOD_D              0x3
  79
  80 #define FMC2_BCR_NBLSET_MAX             0x3
  81 #define FMC2_BXTR_ADDSET_MAX            0xf
  82 #define FMC2_BXTR_ADDHLD_MAX            0xf
  83 #define FMC2_BXTR_DATAST_MAX            0xff
  84 #define FMC2_BXTR_BUSTURN_MAX           0xf
  85 #define FMC2_BXTR_DATAHLD_MAX           0x3
  86 #define FMC2_BTR_CLKDIV_MAX             0xf
  87 #define FMC2_BTR_DATLAT_MAX             0xf
  88 #define FMC2_PCSCNTR_CSCOUNT_MAX        0xff
  89
  90 enum stm32_fmc2_ebi_bank {
  91         FMC2_EBI1 = 0,
  92         FMC2_EBI2,
  93         FMC2_EBI3,
  94         FMC2_EBI4,
  95         FMC2_NAND
  96 };
  97
  98 enum stm32_fmc2_ebi_register_type {
  99         FMC2_REG_BCR = 1,
 100         FMC2_REG_BTR,
 101         FMC2_REG_BWTR,
 102         FMC2_REG_PCSCNTR
 103 };
 104
 105 enum stm32_fmc2_ebi_transaction_type {
 106         FMC2_ASYNC_MODE_1_SRAM = 0,
 107         FMC2_ASYNC_MODE_1_PSRAM,
 108         FMC2_ASYNC_MODE_A_SRAM,
 109         FMC2_ASYNC_MODE_A_PSRAM,
 110         FMC2_ASYNC_MODE_2_NOR,
 111         FMC2_ASYNC_MODE_B_NOR,
 112         FMC2_ASYNC_MODE_C_NOR,
 113         FMC2_ASYNC_MODE_D_NOR,
 114         FMC2_SYNC_READ_SYNC_WRITE_PSRAM,
 115         FMC2_SYNC_READ_ASYNC_WRITE_PSRAM,
 116         FMC2_SYNC_READ_SYNC_WRITE_NOR,
 117         FMC2_SYNC_READ_ASYNC_WRITE_NOR
 118 };
 119
 120 enum stm32_fmc2_ebi_buswidth {
 121         FMC2_BUSWIDTH_8 = 8,
 122         FMC2_BUSWIDTH_16 = 16
 123 };
 124
 125 enum stm32_fmc2_ebi_cpsize {
 126         FMC2_CPSIZE_0 = 0,
 127         FMC2_CPSIZE_128 = 128,
 128         FMC2_CPSIZE_256 = 256,
 129         FMC2_CPSIZE_512 = 512,
 130         FMC2_CPSIZE_1024 = 1024
 131 };
 132
 133 struct stm32_fmc2_ebi {
 134         struct device *dev;
 135         struct clk *clk;
 136         struct regmap *regmap;
 137         u8 bank_assigned;
 138
 139         u32 bcr[FMC2_MAX_EBI_CE];
 140         u32 btr[FMC2_MAX_EBI_CE];
 141         u32 bwtr[FMC2_MAX_EBI_CE];
 142         u32 pcscntr;
 143 };
 144
 145 /*
 146  * struct stm32_fmc2_prop - STM32 FMC2 EBI property
 147  * @name: the device tree binding name of the property
 148  * @bprop: indicate that it is a boolean property
 149  * @mprop: indicate that it is a mandatory property
 150  * @reg_type: the register that have to be modified
 151  * @reg_mask: the bit that have to be modified in the selected register
 152  *            in case of it is a boolean property
 153  * @reset_val: the default value that have to be set in case the property
 154  *             has not been defined in the device tree
 155  * @check: this callback ckecks that the property is compliant with the
 156  *         transaction type selected
 157  * @calculate: this callback is called to calculate for exemple a timing
 158  *             set in nanoseconds in the device tree in clock cycles or in
 159  *             clock period
 160  * @set: this callback applies the values in the registers
 161  */
 162 struct stm32_fmc2_prop {
 163         const char *name;
 164         bool bprop;
 165         bool mprop;
 166         int reg_type;
 167         u32 reg_mask;
 168         u32 reset_val;
 169         int (*check)(struct stm32_fmc2_ebi *ebi,
 170                      const struct stm32_fmc2_prop *prop, int cs);
 171         u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
 172         int (*set)(struct stm32_fmc2_ebi *ebi,
 173                    const struct stm32_fmc2_prop *prop,
 174                    int cs, u32 setup);
 175 };
 176
 177 static int stm32_fmc2_ebi_check_mux(struct stm32_fmc2_ebi *ebi,
 178                                     const struct stm32_fmc2_prop *prop,
 179                                     int cs)
 180 {
 181         u32 bcr;
 182
 183         regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
 184
 185         if (bcr & FMC2_BCR_MTYP)
 186                 return 0;
 187
 188         return -EINVAL;
 189 }
 190
 191 static int stm32_fmc2_ebi_check_waitcfg(struct stm32_fmc2_ebi *ebi,
 192                                         const struct stm32_fmc2_prop *prop,
 193                                         int cs)
 194 {
 195         u32 bcr, val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 196
 197         regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
 198
 199         if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN)
 200                 return 0;
 201
 202         return -EINVAL;
 203 }
 204
 205 static int stm32_fmc2_ebi_check_sync_trans(struct stm32_fmc2_ebi *ebi,
 206                                            const struct stm32_fmc2_prop *prop,
 207                                            int cs)
 208 {
 209         u32 bcr;
 210
 211         regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
 212
 213         if (bcr & FMC2_BCR_BURSTEN)
 214                 return 0;
 215
 216         return -EINVAL;
 217 }
 218
 219 static int stm32_fmc2_ebi_check_async_trans(struct stm32_fmc2_ebi *ebi,
 220                                             const struct stm32_fmc2_prop *prop,
 221                                             int cs)
 222 {
 223         u32 bcr;
 224
 225         regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
 226
 227         if (!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW))
 228                 return 0;
 229
 230         return -EINVAL;
 231 }
 232
 233 static int stm32_fmc2_ebi_check_cpsize(struct stm32_fmc2_ebi *ebi,
 234                                        const struct stm32_fmc2_prop *prop,
 235                                        int cs)
 236 {
 237         u32 bcr, val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
 238
 239         regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
 240
 241         if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN)
 242                 return 0;
 243
 244         return -EINVAL;
 245 }
 246
 247 static int stm32_fmc2_ebi_check_address_hold(struct stm32_fmc2_ebi *ebi,
 248                                              const struct stm32_fmc2_prop *prop,
 249                                              int cs)
 250 {
 251         u32 bcr, bxtr, val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
 252
 253         regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
 254         if (prop->reg_type == FMC2_REG_BWTR)
 255                 regmap_read(ebi->regmap, FMC2_BWTR(cs), &bxtr);
 256         else
 257                 regmap_read(ebi->regmap, FMC2_BTR(cs), &bxtr);
 258
 259         if ((!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW)) &&
 260             ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN))
 261                 return 0;
 262
 263         return -EINVAL;
 264 }
 265
 266 static int stm32_fmc2_ebi_check_clk_period(struct stm32_fmc2_ebi *ebi,
 267                                            const struct stm32_fmc2_prop *prop,
 268                                            int cs)
 269 {
 270         u32 bcr, bcr1;
 271
 272         regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
 273         if (cs)
 274                 regmap_read(ebi->regmap, FMC2_BCR1, &bcr1);
 275         else
 276                 bcr1 = bcr;
 277
 278         if (bcr & FMC2_BCR_BURSTEN && (!cs || !(bcr1 & FMC2_BCR1_CCLKEN)))
 279                 return 0;
 280
 281         return -EINVAL;
 282 }
 283
 284 static int stm32_fmc2_ebi_check_cclk(struct stm32_fmc2_ebi *ebi,
 285                                      const struct stm32_fmc2_prop *prop,
 286                                      int cs)
 287 {
 288         if (cs)
 289                 return -EINVAL;
 290
 291         return stm32_fmc2_ebi_check_sync_trans(ebi, prop, cs);
 292 }
 293
 294 static u32 stm32_fmc2_ebi_ns_to_clock_cycles(struct stm32_fmc2_ebi *ebi,
 295                                              int cs, u32 setup)
 296 {
 297         unsigned long hclk = clk_get_rate(ebi->clk);
 298         unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000);
 299
 300         return DIV_ROUND_UP(setup * 1000, hclkp);
 301 }
 302
 303 static u32 stm32_fmc2_ebi_ns_to_clk_period(struct stm32_fmc2_ebi *ebi,
 304                                            int cs, u32 setup)
 305 {
 306         u32 nb_clk_cycles = stm32_fmc2_ebi_ns_to_clock_cycles(ebi, cs, setup);
 307         u32 bcr, btr, clk_period;
 308
 309         regmap_read(ebi->regmap, FMC2_BCR1, &bcr);
 310         if (bcr & FMC2_BCR1_CCLKEN || !cs)
 311                 regmap_read(ebi->regmap, FMC2_BTR1, &btr);
 312         else
 313                 regmap_read(ebi->regmap, FMC2_BTR(cs), &btr);
 314
 315         clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1;
 316
 317         return DIV_ROUND_UP(nb_clk_cycles, clk_period);
 318 }
 319
 320 static int stm32_fmc2_ebi_get_reg(int reg_type, int cs, u32 *reg)
 321 {
 322         switch (reg_type) {
 323         case FMC2_REG_BCR:
 324                 *reg = FMC2_BCR(cs);
 325                 break;
 326         case FMC2_REG_BTR:
 327                 *reg = FMC2_BTR(cs);
 328                 break;
 329         case FMC2_REG_BWTR:
 330                 *reg = FMC2_BWTR(cs);
 331                 break;
 332         case FMC2_REG_PCSCNTR:
 333                 *reg = FMC2_PCSCNTR;
 334                 break;
 335         default:
 336                 return -EINVAL;
 337         }
 338
 339         return 0;
 340 }
 341
 342 static int stm32_fmc2_ebi_set_bit_field(struct stm32_fmc2_ebi *ebi,
 343                                         const struct stm32_fmc2_prop *prop,
 344                                         int cs, u32 setup)
 345 {
 346         u32 reg;
 347         int ret;
 348
 349         ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
 350         if (ret)
 351                 return ret;
 352
 353         regmap_update_bits(ebi->regmap, reg, prop->reg_mask,
 354                            setup ? prop->reg_mask : 0);
 355
 356         return 0;
 357 }
 358
 359 static int stm32_fmc2_ebi_set_trans_type(struct stm32_fmc2_ebi *ebi,
 360                                          const struct stm32_fmc2_prop *prop,
 361                                          int cs, u32 setup)
 362 {
 363         u32 bcr_mask, bcr = FMC2_BCR_WREN;
 364         u32 btr_mask, btr = 0;
 365         u32 bwtr_mask, bwtr = 0;
 366
 367         bwtr_mask = FMC2_BXTR_ACCMOD;
 368         btr_mask = FMC2_BXTR_ACCMOD;
 369         bcr_mask = FMC2_BCR_MUXEN | FMC2_BCR_MTYP | FMC2_BCR_FACCEN |
 370                    FMC2_BCR_WREN | FMC2_BCR_WAITEN | FMC2_BCR_BURSTEN |
 371                    FMC2_BCR_EXTMOD | FMC2_BCR_CBURSTRW;
 372
 373         switch (setup) {
 374         case FMC2_ASYNC_MODE_1_SRAM:
 375                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM);
 376                 /*
 377                  * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
 378                  * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
 379                  */
 380                 break;
 381         case FMC2_ASYNC_MODE_1_PSRAM:
 382                 /*
 383                  * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
 384                  * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
 385                  */
 386                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
 387                 break;
 388         case FMC2_ASYNC_MODE_A_SRAM:
 389                 /*
 390                  * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
 391                  * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0
 392                  */
 393                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM);
 394                 bcr |= FMC2_BCR_EXTMOD;
 395                 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
 396                 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
 397                 break;
 398         case FMC2_ASYNC_MODE_A_PSRAM:
 399                 /*
 400                  * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
 401                  * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0
 402                  */
 403                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
 404                 bcr |= FMC2_BCR_EXTMOD;
 405                 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
 406                 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
 407                 break;
 408         case FMC2_ASYNC_MODE_2_NOR:
 409                 /*
 410                  * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
 411                  * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
 412                  */
 413                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 414                 bcr |= FMC2_BCR_FACCEN;
 415                 break;
 416         case FMC2_ASYNC_MODE_B_NOR:
 417                 /*
 418                  * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
 419                  * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 1
 420                  */
 421                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 422                 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
 423                 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B);
 424                 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B);
 425                 break;
 426         case FMC2_ASYNC_MODE_C_NOR:
 427                 /*
 428                  * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
 429                  * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 2
 430                  */
 431                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 432                 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
 433                 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C);
 434                 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C);
 435                 break;
 436         case FMC2_ASYNC_MODE_D_NOR:
 437                 /*
 438                  * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
 439                  * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 3
 440                  */
 441                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 442                 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
 443                 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
 444                 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
 445                 break;
 446         case FMC2_SYNC_READ_SYNC_WRITE_PSRAM:
 447                 /*
 448                  * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0,
 449                  * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0
 450                  */
 451                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
 452                 bcr |= FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW;
 453                 break;
 454         case FMC2_SYNC_READ_ASYNC_WRITE_PSRAM:
 455                 /*
 456                  * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0,
 457                  * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
 458                  */
 459                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
 460                 bcr |= FMC2_BCR_BURSTEN;
 461                 break;
 462         case FMC2_SYNC_READ_SYNC_WRITE_NOR:
 463                 /*
 464                  * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0,
 465                  * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0
 466                  */
 467                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 468                 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW;
 469                 break;
 470         case FMC2_SYNC_READ_ASYNC_WRITE_NOR:
 471                 /*
 472                  * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0,
 473                  * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
 474                  */
 475                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 476                 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN;
 477                 break;
 478         default:
 479                 /* Type of transaction not supported */
 480                 return -EINVAL;
 481         }
 482
 483         if (bcr & FMC2_BCR_EXTMOD)
 484                 regmap_update_bits(ebi->regmap, FMC2_BWTR(cs),
 485                                    bwtr_mask, bwtr);
 486         regmap_update_bits(ebi->regmap, FMC2_BTR(cs), btr_mask, btr);
 487         regmap_update_bits(ebi->regmap, FMC2_BCR(cs), bcr_mask, bcr);
 488
 489         return 0;
 490 }
 491
 492 static int stm32_fmc2_ebi_set_buswidth(struct stm32_fmc2_ebi *ebi,
 493                                        const struct stm32_fmc2_prop *prop,
 494                                        int cs, u32 setup)
 495 {
 496         u32 val;
 497
 498         switch (setup) {
 499         case FMC2_BUSWIDTH_8:
 500                 val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_8);
 501                 break;
 502         case FMC2_BUSWIDTH_16:
 503                 val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_16);
 504                 break;
 505         default:
 506                 /* Buswidth not supported */
 507                 return -EINVAL;
 508         }
 509
 510         regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_MWID, val);
 511
 512         return 0;
 513 }
 514
 515 static int stm32_fmc2_ebi_set_cpsize(struct stm32_fmc2_ebi *ebi,
 516                                      const struct stm32_fmc2_prop *prop,
 517                                      int cs, u32 setup)
 518 {
 519         u32 val;
 520
 521         switch (setup) {
 522         case FMC2_CPSIZE_0:
 523                 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_0);
 524                 break;
 525         case FMC2_CPSIZE_128:
 526                 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_128);
 527                 break;
 528         case FMC2_CPSIZE_256:
 529                 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_256);
 530                 break;
 531         case FMC2_CPSIZE_512:
 532                 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_512);
 533                 break;
 534         case FMC2_CPSIZE_1024:
 535                 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_1024);
 536                 break;
 537         default:
 538                 /* Cpsize not supported */
 539                 return -EINVAL;
 540         }
 541
 542         regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_CPSIZE, val);
 543
 544         return 0;
 545 }
 546
 547 static int stm32_fmc2_ebi_set_bl_setup(struct stm32_fmc2_ebi *ebi,
 548                                        const struct stm32_fmc2_prop *prop,
 549                                        int cs, u32 setup)
 550 {
 551         u32 val;
 552
 553         val = min_t(u32, setup, FMC2_BCR_NBLSET_MAX);
 554         val = FIELD_PREP(FMC2_BCR_NBLSET, val);
 555         regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_NBLSET, val);
 556
 557         return 0;
 558 }
 559
 560 static int stm32_fmc2_ebi_set_address_setup(struct stm32_fmc2_ebi *ebi,
 561                                             const struct stm32_fmc2_prop *prop,
 562                                             int cs, u32 setup)
 563 {
 564         u32 bcr, bxtr, reg;
 565         u32 val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
 566         int ret;
 567
 568         ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
 569         if (ret)
 570                 return ret;
 571
 572         regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
 573         if (prop->reg_type == FMC2_REG_BWTR)
 574                 regmap_read(ebi->regmap, FMC2_BWTR(cs), &bxtr);
 575         else
 576                 regmap_read(ebi->regmap, FMC2_BTR(cs), &bxtr);
 577
 578         if ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN)
 579                 val = clamp_val(setup, 1, FMC2_BXTR_ADDSET_MAX);
 580         else
 581                 val = min_t(u32, setup, FMC2_BXTR_ADDSET_MAX);
 582         val = FIELD_PREP(FMC2_BXTR_ADDSET, val);
 583         regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_ADDSET, val);
 584
 585         return 0;
 586 }
 587
 588 static int stm32_fmc2_ebi_set_address_hold(struct stm32_fmc2_ebi *ebi,
 589                                            const struct stm32_fmc2_prop *prop,
 590                                            int cs, u32 setup)
 591 {
 592         u32 val, reg;
 593         int ret;
 594
 595         ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
 596         if (ret)
 597                 return ret;
 598
 599         val = clamp_val(setup, 1, FMC2_BXTR_ADDHLD_MAX);
 600         val = FIELD_PREP(FMC2_BXTR_ADDHLD, val);
 601         regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_ADDHLD, val);
 602
 603         return 0;
 604 }
 605
 606 static int stm32_fmc2_ebi_set_data_setup(struct stm32_fmc2_ebi *ebi,
 607                                          const struct stm32_fmc2_prop *prop,
 608                                          int cs, u32 setup)
 609 {
 610         u32 val, reg;
 611         int ret;
 612
 613         ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
 614         if (ret)
 615                 return ret;
 616
 617         val = clamp_val(setup, 1, FMC2_BXTR_DATAST_MAX);
 618         val = FIELD_PREP(FMC2_BXTR_DATAST, val);
 619         regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_DATAST, val);
 620
 621         return 0;
 622 }
 623
 624 static int stm32_fmc2_ebi_set_bus_turnaround(struct stm32_fmc2_ebi *ebi,
 625                                              const struct stm32_fmc2_prop *prop,
 626                                              int cs, u32 setup)
 627 {
 628         u32 val, reg;
 629         int ret;
 630
 631         ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
 632         if (ret)
 633                 return ret;
 634
 635         val = setup ? min_t(u32, setup - 1, FMC2_BXTR_BUSTURN_MAX) : 0;
 636         val = FIELD_PREP(FMC2_BXTR_BUSTURN, val);
 637         regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_BUSTURN, val);
 638
 639         return 0;
 640 }
 641
 642 static int stm32_fmc2_ebi_set_data_hold(struct stm32_fmc2_ebi *ebi,
 643                                         const struct stm32_fmc2_prop *prop,
 644                                         int cs, u32 setup)
 645 {
 646         u32 val, reg;
 647         int ret;
 648
 649         ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
 650         if (ret)
 651                 return ret;
 652
 653         if (prop->reg_type == FMC2_REG_BWTR)
 654                 val = setup ? min_t(u32, setup - 1, FMC2_BXTR_DATAHLD_MAX) : 0;
 655         else
 656                 val = min_t(u32, setup, FMC2_BXTR_DATAHLD_MAX);
 657         val = FIELD_PREP(FMC2_BXTR_DATAHLD, val);
 658         regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_DATAHLD, val);
 659
 660         return 0;
 661 }
 662
 663 static int stm32_fmc2_ebi_set_clk_period(struct stm32_fmc2_ebi *ebi,
 664                                          const struct stm32_fmc2_prop *prop,
 665                                          int cs, u32 setup)
 666 {
 667         u32 val;
 668
 669         val = setup ? clamp_val(setup - 1, 1, FMC2_BTR_CLKDIV_MAX) : 1;
 670         val = FIELD_PREP(FMC2_BTR_CLKDIV, val);
 671         regmap_update_bits(ebi->regmap, FMC2_BTR(cs), FMC2_BTR_CLKDIV, val);
 672
 673         return 0;
 674 }
 675
 676 static int stm32_fmc2_ebi_set_data_latency(struct stm32_fmc2_ebi *ebi,
 677                                            const struct stm32_fmc2_prop *prop,
 678                                            int cs, u32 setup)
 679 {
 680         u32 val;
 681
 682         val = setup > 1 ? min_t(u32, setup - 2, FMC2_BTR_DATLAT_MAX) : 0;
 683         val = FIELD_PREP(FMC2_BTR_DATLAT, val);
 684         regmap_update_bits(ebi->regmap, FMC2_BTR(cs), FMC2_BTR_DATLAT, val);
 685
 686         return 0;
 687 }
 688
 689 static int stm32_fmc2_ebi_set_max_low_pulse(struct stm32_fmc2_ebi *ebi,
 690                                             const struct stm32_fmc2_prop *prop,
 691                                             int cs, u32 setup)
 692 {
 693         u32 old_val, new_val, pcscntr;
 694
 695         if (setup < 1)
 696                 return 0;
 697
 698         regmap_read(ebi->regmap, FMC2_PCSCNTR, &pcscntr);
 699
 700         /* Enable counter for the bank */
 701         regmap_update_bits(ebi->regmap, FMC2_PCSCNTR,
 702                            FMC2_PCSCNTR_CNTBEN(cs),
 703                            FMC2_PCSCNTR_CNTBEN(cs));
 704
 705         new_val = min_t(u32, setup - 1, FMC2_PCSCNTR_CSCOUNT_MAX);
 706         old_val = FIELD_GET(FMC2_PCSCNTR_CSCOUNT, pcscntr);
 707         if (old_val && new_val > old_val)
 708                 /* Keep current counter value */
 709                 return 0;
 710
 711         new_val = FIELD_PREP(FMC2_PCSCNTR_CSCOUNT, new_val);
 712         regmap_update_bits(ebi->regmap, FMC2_PCSCNTR,
 713                            FMC2_PCSCNTR_CSCOUNT, new_val);
 714
 715         return 0;
 716 }
 717
 718 static const struct stm32_fmc2_prop stm32_fmc2_child_props[] = {
 719         /* st,fmc2-ebi-cs-trans-type must be the first property */
 720         {
 721                 .name = "st,fmc2-ebi-cs-transaction-type",
 722                 .mprop = true,
 723                 .set = stm32_fmc2_ebi_set_trans_type,
 724         },
 725         {
 726                 .name = "st,fmc2-ebi-cs-cclk-enable",
 727                 .bprop = true,
 728                 .reg_type = FMC2_REG_BCR,
 729                 .reg_mask = FMC2_BCR1_CCLKEN,
 730                 .check = stm32_fmc2_ebi_check_cclk,
 731                 .set = stm32_fmc2_ebi_set_bit_field,
 732         },
 733         {
 734                 .name = "st,fmc2-ebi-cs-mux-enable",
 735                 .bprop = true,
 736                 .reg_type = FMC2_REG_BCR,
 737                 .reg_mask = FMC2_BCR_MUXEN,
 738                 .check = stm32_fmc2_ebi_check_mux,
 739                 .set = stm32_fmc2_ebi_set_bit_field,
 740         },
 741         {
 742                 .name = "st,fmc2-ebi-cs-buswidth",
 743                 .reset_val = FMC2_BUSWIDTH_16,
 744                 .set = stm32_fmc2_ebi_set_buswidth,
 745         },
 746         {
 747                 .name = "st,fmc2-ebi-cs-waitpol-high",
 748                 .bprop = true,
 749                 .reg_type = FMC2_REG_BCR,
 750                 .reg_mask = FMC2_BCR_WAITPOL,
 751                 .set = stm32_fmc2_ebi_set_bit_field,
 752         },
 753         {
 754                 .name = "st,fmc2-ebi-cs-waitcfg-enable",
 755                 .bprop = true,
 756                 .reg_type = FMC2_REG_BCR,
 757                 .reg_mask = FMC2_BCR_WAITCFG,
 758                 .check = stm32_fmc2_ebi_check_waitcfg,
 759                 .set = stm32_fmc2_ebi_set_bit_field,
 760         },
 761         {
 762                 .name = "st,fmc2-ebi-cs-wait-enable",
 763                 .bprop = true,
 764                 .reg_type = FMC2_REG_BCR,
 765                 .reg_mask = FMC2_BCR_WAITEN,
 766                 .check = stm32_fmc2_ebi_check_sync_trans,
 767                 .set = stm32_fmc2_ebi_set_bit_field,
 768         },
 769         {
 770                 .name = "st,fmc2-ebi-cs-asyncwait-enable",
 771                 .bprop = true,
 772                 .reg_type = FMC2_REG_BCR,
 773                 .reg_mask = FMC2_BCR_ASYNCWAIT,
 774                 .check = stm32_fmc2_ebi_check_async_trans,
 775                 .set = stm32_fmc2_ebi_set_bit_field,
 776         },
 777         {
 778                 .name = "st,fmc2-ebi-cs-cpsize",
 779                 .check = stm32_fmc2_ebi_check_cpsize,
 780                 .set = stm32_fmc2_ebi_set_cpsize,
 781         },
 782         {
 783                 .name = "st,fmc2-ebi-cs-byte-lane-setup-ns",
 784                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 785                 .set = stm32_fmc2_ebi_set_bl_setup,
 786         },
 787         {
 788                 .name = "st,fmc2-ebi-cs-address-setup-ns",
 789                 .reg_type = FMC2_REG_BTR,
 790                 .reset_val = FMC2_BXTR_ADDSET_MAX,
 791                 .check = stm32_fmc2_ebi_check_async_trans,
 792                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 793                 .set = stm32_fmc2_ebi_set_address_setup,
 794         },
 795         {
 796                 .name = "st,fmc2-ebi-cs-address-hold-ns",
 797                 .reg_type = FMC2_REG_BTR,
 798                 .reset_val = FMC2_BXTR_ADDHLD_MAX,
 799                 .check = stm32_fmc2_ebi_check_address_hold,
 800                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 801                 .set = stm32_fmc2_ebi_set_address_hold,
 802         },
 803         {
 804                 .name = "st,fmc2-ebi-cs-data-setup-ns",
 805                 .reg_type = FMC2_REG_BTR,
 806                 .reset_val = FMC2_BXTR_DATAST_MAX,
 807                 .check = stm32_fmc2_ebi_check_async_trans,
 808                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 809                 .set = stm32_fmc2_ebi_set_data_setup,
 810         },
 811         {
 812                 .name = "st,fmc2-ebi-cs-bus-turnaround-ns",
 813                 .reg_type = FMC2_REG_BTR,
 814                 .reset_val = FMC2_BXTR_BUSTURN_MAX + 1,
 815                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 816                 .set = stm32_fmc2_ebi_set_bus_turnaround,
 817         },
 818         {
 819                 .name = "st,fmc2-ebi-cs-data-hold-ns",
 820                 .reg_type = FMC2_REG_BTR,
 821                 .check = stm32_fmc2_ebi_check_async_trans,
 822                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 823                 .set = stm32_fmc2_ebi_set_data_hold,
 824         },
 825         {
 826                 .name = "st,fmc2-ebi-cs-clk-period-ns",
 827                 .reset_val = FMC2_BTR_CLKDIV_MAX + 1,
 828                 .check = stm32_fmc2_ebi_check_clk_period,
 829                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 830                 .set = stm32_fmc2_ebi_set_clk_period,
 831         },
 832         {
 833                 .name = "st,fmc2-ebi-cs-data-latency-ns",
 834                 .check = stm32_fmc2_ebi_check_sync_trans,
 835                 .calculate = stm32_fmc2_ebi_ns_to_clk_period,
 836                 .set = stm32_fmc2_ebi_set_data_latency,
 837         },
 838         {
 839                 .name = "st,fmc2-ebi-cs-write-address-setup-ns",
 840                 .reg_type = FMC2_REG_BWTR,
 841                 .reset_val = FMC2_BXTR_ADDSET_MAX,
 842                 .check = stm32_fmc2_ebi_check_async_trans,
 843                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 844                 .set = stm32_fmc2_ebi_set_address_setup,
 845         },
 846         {
 847                 .name = "st,fmc2-ebi-cs-write-address-hold-ns",
 848                 .reg_type = FMC2_REG_BWTR,
 849                 .reset_val = FMC2_BXTR_ADDHLD_MAX,
 850                 .check = stm32_fmc2_ebi_check_address_hold,
 851                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 852                 .set = stm32_fmc2_ebi_set_address_hold,
 853         },
 854         {
 855                 .name = "st,fmc2-ebi-cs-write-data-setup-ns",
 856                 .reg_type = FMC2_REG_BWTR,
 857                 .reset_val = FMC2_BXTR_DATAST_MAX,
 858                 .check = stm32_fmc2_ebi_check_async_trans,
 859                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 860                 .set = stm32_fmc2_ebi_set_data_setup,
 861         },
 862         {
 863                 .name = "st,fmc2-ebi-cs-write-bus-turnaround-ns",
 864                 .reg_type = FMC2_REG_BWTR,
 865                 .reset_val = FMC2_BXTR_BUSTURN_MAX + 1,
 866                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 867                 .set = stm32_fmc2_ebi_set_bus_turnaround,
 868         },
 869         {
 870                 .name = "st,fmc2-ebi-cs-write-data-hold-ns",
 871                 .reg_type = FMC2_REG_BWTR,
 872                 .check = stm32_fmc2_ebi_check_async_trans,
 873                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 874                 .set = stm32_fmc2_ebi_set_data_hold,
 875         },
 876         {
 877                 .name = "st,fmc2-ebi-cs-max-low-pulse-ns",
 878                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 879                 .set = stm32_fmc2_ebi_set_max_low_pulse,
 880         },
 881 };
 882
 883 static int stm32_fmc2_ebi_parse_prop(struct stm32_fmc2_ebi *ebi,
 884                                      struct device_node *dev_node,
 885                                      const struct stm32_fmc2_prop *prop,
 886                                      int cs)
 887 {
 888         struct device *dev = ebi->dev;
 889         u32 setup = 0;
 890
 891         if (!prop->set) {
 892                 dev_err(dev, "property %s is not well defined\n", prop->name);
 893                 return -EINVAL;
 894         }
 895
 896         if (prop->check && prop->check(ebi, prop, cs))
 897                 /* Skeep this property */
 898                 return 0;
 899
 900         if (prop->bprop) {
 901                 bool bprop;
 902
 903                 bprop = of_property_read_bool(dev_node, prop->name);
 904                 if (prop->mprop && !bprop) {
 905                         dev_err(dev, "mandatory property %s not defined in the device tree\n",
 906                                 prop->name);
 907                         return -EINVAL;
 908                 }
 909
 910                 if (bprop)
 911                         setup = 1;
 912         } else {
 913                 u32 val;
 914                 int ret;
 915
 916                 ret = of_property_read_u32(dev_node, prop->name, &val);
 917                 if (prop->mprop && ret) {
 918                         dev_err(dev, "mandatory property %s not defined in the device tree\n",
 919                                 prop->name);
 920                         return ret;
 921                 }
 922
 923                 if (ret)
 924                         setup = prop->reset_val;
 925                 else if (prop->calculate)
 926                         setup = prop->calculate(ebi, cs, val);
 927                 else
 928                         setup = val;
 929         }
 930
 931         return prop->set(ebi, prop, cs, setup);
 932 }
 933
 934 static void stm32_fmc2_ebi_enable_bank(struct stm32_fmc2_ebi *ebi, int cs)
 935 {
 936         regmap_update_bits(ebi->regmap, FMC2_BCR(cs),
 937                            FMC2_BCR_MBKEN, FMC2_BCR_MBKEN);
 938 }
 939
 940 static void stm32_fmc2_ebi_disable_bank(struct stm32_fmc2_ebi *ebi, int cs)
 941 {
 942         regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_MBKEN, 0);
 943 }
 944
 945 static void stm32_fmc2_ebi_save_setup(struct stm32_fmc2_ebi *ebi)
 946 {
 947         unsigned int cs;
 948
 949         for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
 950                 regmap_read(ebi->regmap, FMC2_BCR(cs), &ebi->bcr[cs]);
 951                 regmap_read(ebi->regmap, FMC2_BTR(cs), &ebi->btr[cs]);
 952                 regmap_read(ebi->regmap, FMC2_BWTR(cs), &ebi->bwtr[cs]);
 953         }
 954
 955         regmap_read(ebi->regmap, FMC2_PCSCNTR, &ebi->pcscntr);
 956 }
 957
 958 static void stm32_fmc2_ebi_set_setup(struct stm32_fmc2_ebi *ebi)
 959 {
 960         unsigned int cs;
 961
 962         for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
 963                 regmap_write(ebi->regmap, FMC2_BCR(cs), ebi->bcr[cs]);
 964                 regmap_write(ebi->regmap, FMC2_BTR(cs), ebi->btr[cs]);
 965                 regmap_write(ebi->regmap, FMC2_BWTR(cs), ebi->bwtr[cs]);
 966         }
 967
 968         regmap_write(ebi->regmap, FMC2_PCSCNTR, ebi->pcscntr);
 969 }
 970
 971 static void stm32_fmc2_ebi_disable_banks(struct stm32_fmc2_ebi *ebi)
 972 {
 973         unsigned int cs;
 974
 975         for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
 976                 if (!(ebi->bank_assigned & BIT(cs)))
 977                         continue;
 978
 979                 stm32_fmc2_ebi_disable_bank(ebi, cs);
 980         }
 981 }
 982
 983 /* NWAIT signal can not be connected to EBI controller and NAND controller */
 984 static bool stm32_fmc2_ebi_nwait_used_by_ctrls(struct stm32_fmc2_ebi *ebi)
 985 {
 986         unsigned int cs;
 987         u32 bcr;
 988
 989         for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
 990                 if (!(ebi->bank_assigned & BIT(cs)))
 991                         continue;
 992
 993                 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
 994                 if ((bcr & FMC2_BCR_WAITEN || bcr & FMC2_BCR_ASYNCWAIT) &&
 995                     ebi->bank_assigned & BIT(FMC2_NAND))
 996                         return true;
 997         }
 998
 999         return false;
1000 }
1001
1002 static void stm32_fmc2_ebi_enable(struct stm32_fmc2_ebi *ebi)
1003 {
1004         regmap_update_bits(ebi->regmap, FMC2_BCR1,
1005                            FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN);
1006 }
1007
1008 static void stm32_fmc2_ebi_disable(struct stm32_fmc2_ebi *ebi)
1009 {
1010         regmap_update_bits(ebi->regmap, FMC2_BCR1, FMC2_BCR1_FMC2EN, 0);
1011 }
1012
1013 static int stm32_fmc2_ebi_setup_cs(struct stm32_fmc2_ebi *ebi,
1014                                    struct device_node *dev_node,
1015                                    u32 cs)
1016 {
1017         unsigned int i;
1018         int ret;
1019
1020         stm32_fmc2_ebi_disable_bank(ebi, cs);
1021
1022         for (i = 0; i < ARRAY_SIZE(stm32_fmc2_child_props); i++) {
1023                 const struct stm32_fmc2_prop *p = &stm32_fmc2_child_props[i];
1024
1025                 ret = stm32_fmc2_ebi_parse_prop(ebi, dev_node, p, cs);
1026                 if (ret) {
1027                         dev_err(ebi->dev, "property %s could not be set: %d\n",
1028                                 p->name, ret);
1029                         return ret;
1030                 }
1031         }
1032
1033         stm32_fmc2_ebi_enable_bank(ebi, cs);
1034
1035         return 0;
1036 }
1037
1038 static int stm32_fmc2_ebi_parse_dt(struct stm32_fmc2_ebi *ebi)
1039 {
1040         struct device *dev = ebi->dev;
1041         struct device_node *child;
1042         bool child_found = false;
1043         u32 bank;
1044         int ret;
1045
1046         for_each_available_child_of_node(dev->of_node, child) {
1047                 ret = of_property_read_u32(child, "reg", &bank);
1048                 if (ret) {
1049                         dev_err(dev, "could not retrieve reg property: %d\n",
1050                                 ret);
1051                         of_node_put(child);
1052                         return ret;
1053                 }
1054
1055                 if (bank >= FMC2_MAX_BANKS) {
1056                         dev_err(dev, "invalid reg value: %d\n", bank);
1057                         of_node_put(child);
1058                         return -EINVAL;
1059                 }
1060
1061                 if (ebi->bank_assigned & BIT(bank)) {
1062                         dev_err(dev, "bank already assigned: %d\n", bank);
1063                         of_node_put(child);
1064                         return -EINVAL;
1065                 }
1066
1067                 if (bank < FMC2_MAX_EBI_CE) {
1068                         ret = stm32_fmc2_ebi_setup_cs(ebi, child, bank);
1069                         if (ret) {
1070                                 dev_err(dev, "setup chip select %d failed: %d\n",
1071                                         bank, ret);
1072                                 of_node_put(child);
1073                                 return ret;
1074                         }
1075                 }
1076
1077                 ebi->bank_assigned |= BIT(bank);
1078                 child_found = true;
1079         }
1080
1081         if (!child_found) {
1082                 dev_warn(dev, "no subnodes found, disable the driver.\n");
1083                 return -ENODEV;
1084         }
1085
1086         if (stm32_fmc2_ebi_nwait_used_by_ctrls(ebi)) {
1087                 dev_err(dev, "NWAIT signal connected to EBI and NAND controllers\n");
1088                 return -EINVAL;
1089         }
1090
1091         stm32_fmc2_ebi_enable(ebi);
1092
1093         return of_platform_populate(dev->of_node, NULL, NULL, dev);
1094 }
1095
1096 static int stm32_fmc2_ebi_probe(struct platform_device *pdev)
1097 {
1098         struct device *dev = &pdev->dev;
1099         struct stm32_fmc2_ebi *ebi;
1100         struct reset_control *rstc;
1101         int ret;
1102
1103         ebi = devm_kzalloc(&pdev->dev, sizeof(*ebi), GFP_KERNEL);
1104         if (!ebi)
1105                 return -ENOMEM;
1106
1107         ebi->dev = dev;
1108
1109         ebi->regmap = device_node_to_regmap(dev->of_node);
1110         if (IS_ERR(ebi->regmap))
1111                 return PTR_ERR(ebi->regmap);
1112
1113         ebi->clk = devm_clk_get(dev, NULL);
1114         if (IS_ERR(ebi->clk))
1115                 return PTR_ERR(ebi->clk);
1116
1117         rstc = devm_reset_control_get(dev, NULL);
1118         if (PTR_ERR(rstc) == -EPROBE_DEFER)
1119                 return -EPROBE_DEFER;
1120
1121         ret = clk_prepare_enable(ebi->clk);
1122         if (ret)
1123                 return ret;
1124
1125         if (!IS_ERR(rstc)) {
1126                 reset_control_assert(rstc);
1127                 reset_control_deassert(rstc);
1128         }
1129
1130         ret = stm32_fmc2_ebi_parse_dt(ebi);
1131         if (ret)
1132                 goto err_release;
1133
1134         stm32_fmc2_ebi_save_setup(ebi);
1135         platform_set_drvdata(pdev, ebi);
1136
1137         return 0;
1138
1139 err_release:
1140         stm32_fmc2_ebi_disable_banks(ebi);
1141         stm32_fmc2_ebi_disable(ebi);
1142         clk_disable_unprepare(ebi->clk);
1143
1144         return ret;
1145 }
1146
1147 static int stm32_fmc2_ebi_remove(struct platform_device *pdev)
1148 {
1149         struct stm32_fmc2_ebi *ebi = platform_get_drvdata(pdev);
1150
1151         of_platform_depopulate(&pdev->dev);
1152         stm32_fmc2_ebi_disable_banks(ebi);
1153         stm32_fmc2_ebi_disable(ebi);
1154         clk_disable_unprepare(ebi->clk);
1155
1156         return 0;
1157 }
1158
1159 static int __maybe_unused stm32_fmc2_ebi_suspend(struct device *dev)
1160 {
1161         struct stm32_fmc2_ebi *ebi = dev_get_drvdata(dev);
1162
1163         stm32_fmc2_ebi_disable(ebi);
1164         clk_disable_unprepare(ebi->clk);
1165         pinctrl_pm_select_sleep_state(dev);
1166
1167         return 0;
1168 }
1169
1170 static int __maybe_unused stm32_fmc2_ebi_resume(struct device *dev)
1171 {
1172         struct stm32_fmc2_ebi *ebi = dev_get_drvdata(dev);
1173         int ret;
1174
1175         pinctrl_pm_select_default_state(dev);
1176
1177         ret = clk_prepare_enable(ebi->clk);
1178         if (ret)
1179                 return ret;
1180
1181         stm32_fmc2_ebi_set_setup(ebi);
1182         stm32_fmc2_ebi_enable(ebi);
1183
1184         return 0;
1185 }
1186
1187 static SIMPLE_DEV_PM_OPS(stm32_fmc2_ebi_pm_ops, stm32_fmc2_ebi_suspend,
1188                          stm32_fmc2_ebi_resume);
1189
1190 static const struct of_device_id stm32_fmc2_ebi_match[] = {
1191         {.compatible = "st,stm32mp1-fmc2-ebi"},
1192         {}
1193 };
1194 MODULE_DEVICE_TABLE(of, stm32_fmc2_ebi_match);
1195
1196 static struct platform_driver stm32_fmc2_ebi_driver = {
1197         .probe  = stm32_fmc2_ebi_probe,
1198         .remove = stm32_fmc2_ebi_remove,
1199         .driver = {
1200                 .name = "stm32_fmc2_ebi",
1201                 .of_match_table = stm32_fmc2_ebi_match,
1202                 .pm = &stm32_fmc2_ebi_pm_ops,
1203         },
1204 };
1205 module_platform_driver(stm32_fmc2_ebi_driver);
1206
1207 MODULE_ALIAS("platform:stm32_fmc2_ebi");
1208 MODULE_AUTHOR("Christophe Kerello <christophe.kerello@st.com>");
1209 MODULE_DESCRIPTION("STMicroelectronics STM32 FMC2 ebi driver");
1210 MODULE_LICENSE("GPL v2");