1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) STMicroelectronics 2020
6 #define LOG_CATEGORY UCLASS_NOP
12 #include <dm/device_compat.h>
13 #include <linux/bitfield.h>
14 #include <linux/err.h>
15 #include <linux/iopoll.h>
16 #include <linux/ioport.h>
18 /* FMC2 Controller Registers */
21 #define FMC2_BCR(x) ((x) * 0x8 + FMC2_BCR1)
22 #define FMC2_BTR(x) ((x) * 0x8 + FMC2_BTR1)
23 #define FMC2_PCSCNTR 0x20
24 #define FMC2_BWTR1 0x104
25 #define FMC2_BWTR(x) ((x) * 0x8 + FMC2_BWTR1)
27 /* Register: FMC2_BCR1 */
28 #define FMC2_BCR1_CCLKEN BIT(20)
29 #define FMC2_BCR1_FMC2EN BIT(31)
31 /* Register: FMC2_BCRx */
32 #define FMC2_BCR_MBKEN BIT(0)
33 #define FMC2_BCR_MUXEN BIT(1)
34 #define FMC2_BCR_MTYP GENMASK(3, 2)
35 #define FMC2_BCR_MWID GENMASK(5, 4)
36 #define FMC2_BCR_FACCEN BIT(6)
37 #define FMC2_BCR_BURSTEN BIT(8)
38 #define FMC2_BCR_WAITPOL BIT(9)
39 #define FMC2_BCR_WAITCFG BIT(11)
40 #define FMC2_BCR_WREN BIT(12)
41 #define FMC2_BCR_WAITEN BIT(13)
42 #define FMC2_BCR_EXTMOD BIT(14)
43 #define FMC2_BCR_ASYNCWAIT BIT(15)
44 #define FMC2_BCR_CPSIZE GENMASK(18, 16)
45 #define FMC2_BCR_CBURSTRW BIT(19)
46 #define FMC2_BCR_NBLSET GENMASK(23, 22)
48 /* Register: FMC2_BTRx/FMC2_BWTRx */
49 #define FMC2_BXTR_ADDSET GENMASK(3, 0)
50 #define FMC2_BXTR_ADDHLD GENMASK(7, 4)
51 #define FMC2_BXTR_DATAST GENMASK(15, 8)
52 #define FMC2_BXTR_BUSTURN GENMASK(19, 16)
53 #define FMC2_BTR_CLKDIV GENMASK(23, 20)
54 #define FMC2_BTR_DATLAT GENMASK(27, 24)
55 #define FMC2_BXTR_ACCMOD GENMASK(29, 28)
56 #define FMC2_BXTR_DATAHLD GENMASK(31, 30)
58 /* Register: FMC2_PCSCNTR */
59 #define FMC2_PCSCNTR_CSCOUNT GENMASK(15, 0)
60 #define FMC2_PCSCNTR_CNTBEN(x) BIT((x) + 16)
62 #define FMC2_MAX_EBI_CE 4
63 #define FMC2_MAX_BANKS 5
65 #define FMC2_BCR_CPSIZE_0 0x0
66 #define FMC2_BCR_CPSIZE_128 0x1
67 #define FMC2_BCR_CPSIZE_256 0x2
68 #define FMC2_BCR_CPSIZE_512 0x3
69 #define FMC2_BCR_CPSIZE_1024 0x4
71 #define FMC2_BCR_MWID_8 0x0
72 #define FMC2_BCR_MWID_16 0x1
74 #define FMC2_BCR_MTYP_SRAM 0x0
75 #define FMC2_BCR_MTYP_PSRAM 0x1
76 #define FMC2_BCR_MTYP_NOR 0x2
78 #define FMC2_BXTR_EXTMOD_A 0x0
79 #define FMC2_BXTR_EXTMOD_B 0x1
80 #define FMC2_BXTR_EXTMOD_C 0x2
81 #define FMC2_BXTR_EXTMOD_D 0x3
83 #define FMC2_BCR_NBLSET_MAX 0x3
84 #define FMC2_BXTR_ADDSET_MAX 0xf
85 #define FMC2_BXTR_ADDHLD_MAX 0xf
86 #define FMC2_BXTR_DATAST_MAX 0xff
87 #define FMC2_BXTR_BUSTURN_MAX 0xf
88 #define FMC2_BXTR_DATAHLD_MAX 0x3
89 #define FMC2_BTR_CLKDIV_MAX 0xf
90 #define FMC2_BTR_DATLAT_MAX 0xf
91 #define FMC2_PCSCNTR_CSCOUNT_MAX 0xff
93 #define FMC2_NSEC_PER_SEC 1000000000L
95 enum stm32_fmc2_ebi_bank {
103 enum stm32_fmc2_ebi_register_type {
110 enum stm32_fmc2_ebi_transaction_type {
111 FMC2_ASYNC_MODE_1_SRAM = 0,
112 FMC2_ASYNC_MODE_1_PSRAM,
113 FMC2_ASYNC_MODE_A_SRAM,
114 FMC2_ASYNC_MODE_A_PSRAM,
115 FMC2_ASYNC_MODE_2_NOR,
116 FMC2_ASYNC_MODE_B_NOR,
117 FMC2_ASYNC_MODE_C_NOR,
118 FMC2_ASYNC_MODE_D_NOR,
119 FMC2_SYNC_READ_SYNC_WRITE_PSRAM,
120 FMC2_SYNC_READ_ASYNC_WRITE_PSRAM,
121 FMC2_SYNC_READ_SYNC_WRITE_NOR,
122 FMC2_SYNC_READ_ASYNC_WRITE_NOR
125 enum stm32_fmc2_ebi_buswidth {
127 FMC2_BUSWIDTH_16 = 16
130 enum stm32_fmc2_ebi_cpsize {
132 FMC2_CPSIZE_128 = 128,
133 FMC2_CPSIZE_256 = 256,
134 FMC2_CPSIZE_512 = 512,
135 FMC2_CPSIZE_1024 = 1024
138 struct stm32_fmc2_ebi {
145 * struct stm32_fmc2_prop - STM32 FMC2 EBI property
146 * @name: the device tree binding name of the property
147 * @bprop: indicate that it is a boolean property
148 * @mprop: indicate that it is a mandatory property
149 * @reg_type: the register that have to be modified
150 * @reg_mask: the bit that have to be modified in the selected register
151 * in case of it is a boolean property
152 * @reset_val: the default value that have to be set in case the property
153 * has not been defined in the device tree
154 * @check: this callback ckecks that the property is compliant with the
155 * transaction type selected
156 * @calculate: this callback is called to calculate for exemple a timing
157 * set in nanoseconds in the device tree in clock cycles or in
159 * @set: this callback applies the values in the registers
161 struct stm32_fmc2_prop {
168 int (*check)(struct stm32_fmc2_ebi *ebi,
169 const struct stm32_fmc2_prop *prop, int cs);
170 u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
171 int (*set)(struct stm32_fmc2_ebi *ebi,
172 const struct stm32_fmc2_prop *prop,
176 static int stm32_fmc2_ebi_check_mux(struct stm32_fmc2_ebi *ebi,
177 const struct stm32_fmc2_prop *prop,
180 u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
182 if (bcr & FMC2_BCR_MTYP)
188 static int stm32_fmc2_ebi_check_waitcfg(struct stm32_fmc2_ebi *ebi,
189 const struct stm32_fmc2_prop *prop,
192 u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
193 u32 val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
195 if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN)
201 static int stm32_fmc2_ebi_check_sync_trans(struct stm32_fmc2_ebi *ebi,
202 const struct stm32_fmc2_prop *prop,
205 u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
207 if (bcr & FMC2_BCR_BURSTEN)
213 static int stm32_fmc2_ebi_check_async_trans(struct stm32_fmc2_ebi *ebi,
214 const struct stm32_fmc2_prop *prop,
217 u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
219 if (!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW))
225 static int stm32_fmc2_ebi_check_cpsize(struct stm32_fmc2_ebi *ebi,
226 const struct stm32_fmc2_prop *prop,
229 u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
230 u32 val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
232 if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN)
238 static int stm32_fmc2_ebi_check_address_hold(struct stm32_fmc2_ebi *ebi,
239 const struct stm32_fmc2_prop *prop,
242 u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
243 u32 bxtr = prop->reg_type == FMC2_REG_BWTR ?
244 readl(ebi->io_base + FMC2_BWTR(cs)) :
245 readl(ebi->io_base + FMC2_BTR(cs));
246 u32 val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
248 if ((!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW)) &&
249 ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN))
255 static int stm32_fmc2_ebi_check_clk_period(struct stm32_fmc2_ebi *ebi,
256 const struct stm32_fmc2_prop *prop,
259 u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
260 u32 bcr1 = cs ? readl(ebi->io_base + FMC2_BCR1) : bcr;
262 if (bcr & FMC2_BCR_BURSTEN && (!cs || !(bcr1 & FMC2_BCR1_CCLKEN)))
268 static int stm32_fmc2_ebi_check_cclk(struct stm32_fmc2_ebi *ebi,
269 const struct stm32_fmc2_prop *prop,
275 return stm32_fmc2_ebi_check_sync_trans(ebi, prop, cs);
278 static u32 stm32_fmc2_ebi_ns_to_clock_cycles(struct stm32_fmc2_ebi *ebi,
281 unsigned long hclk = clk_get_rate(&ebi->clk);
282 unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000);
284 return DIV_ROUND_UP(setup * 1000, hclkp);
287 static u32 stm32_fmc2_ebi_ns_to_clk_period(struct stm32_fmc2_ebi *ebi,
290 u32 nb_clk_cycles = stm32_fmc2_ebi_ns_to_clock_cycles(ebi, cs, setup);
291 u32 bcr = readl(ebi->io_base + FMC2_BCR1);
292 u32 btr = bcr & FMC2_BCR1_CCLKEN || !cs ?
293 readl(ebi->io_base + FMC2_BTR1) :
294 readl(ebi->io_base + FMC2_BTR(cs));
295 u32 clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1;
297 return DIV_ROUND_UP(nb_clk_cycles, clk_period);
300 static int stm32_fmc2_ebi_get_reg(int reg_type, int cs, u32 *reg)
310 *reg = FMC2_BWTR(cs);
312 case FMC2_REG_PCSCNTR:
322 static int stm32_fmc2_ebi_set_bit_field(struct stm32_fmc2_ebi *ebi,
323 const struct stm32_fmc2_prop *prop,
329 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®);
333 clrsetbits_le32(ebi->io_base + reg, prop->reg_mask,
334 setup ? prop->reg_mask : 0);
339 static int stm32_fmc2_ebi_set_trans_type(struct stm32_fmc2_ebi *ebi,
340 const struct stm32_fmc2_prop *prop,
343 u32 bcr_mask, bcr = FMC2_BCR_WREN;
344 u32 btr_mask, btr = 0;
345 u32 bwtr_mask, bwtr = 0;
347 bwtr_mask = FMC2_BXTR_ACCMOD;
348 btr_mask = FMC2_BXTR_ACCMOD;
349 bcr_mask = FMC2_BCR_MUXEN | FMC2_BCR_MTYP | FMC2_BCR_FACCEN |
350 FMC2_BCR_WREN | FMC2_BCR_WAITEN | FMC2_BCR_BURSTEN |
351 FMC2_BCR_EXTMOD | FMC2_BCR_CBURSTRW;
354 case FMC2_ASYNC_MODE_1_SRAM:
355 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM);
357 * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
358 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
361 case FMC2_ASYNC_MODE_1_PSRAM:
363 * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
364 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
366 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
368 case FMC2_ASYNC_MODE_A_SRAM:
370 * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
371 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0
373 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM);
374 bcr |= FMC2_BCR_EXTMOD;
375 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
376 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
378 case FMC2_ASYNC_MODE_A_PSRAM:
380 * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
381 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0
383 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
384 bcr |= FMC2_BCR_EXTMOD;
385 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
386 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
388 case FMC2_ASYNC_MODE_2_NOR:
390 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
391 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
393 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
394 bcr |= FMC2_BCR_FACCEN;
396 case FMC2_ASYNC_MODE_B_NOR:
398 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
399 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 1
401 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
402 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
403 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B);
404 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B);
406 case FMC2_ASYNC_MODE_C_NOR:
408 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
409 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 2
411 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
412 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
413 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C);
414 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C);
416 case FMC2_ASYNC_MODE_D_NOR:
418 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
419 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 3
421 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
422 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
423 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
424 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
426 case FMC2_SYNC_READ_SYNC_WRITE_PSRAM:
428 * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0,
429 * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0
431 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
432 bcr |= FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW;
434 case FMC2_SYNC_READ_ASYNC_WRITE_PSRAM:
436 * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0,
437 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
439 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
440 bcr |= FMC2_BCR_BURSTEN;
442 case FMC2_SYNC_READ_SYNC_WRITE_NOR:
444 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0,
445 * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0
447 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
448 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW;
450 case FMC2_SYNC_READ_ASYNC_WRITE_NOR:
452 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0,
453 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
455 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
456 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN;
459 /* Type of transaction not supported */
463 if (bcr & FMC2_BCR_EXTMOD)
464 clrsetbits_le32(ebi->io_base + FMC2_BWTR(cs),
466 clrsetbits_le32(ebi->io_base + FMC2_BTR(cs), btr_mask, btr);
467 clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), bcr_mask, bcr);
472 static int stm32_fmc2_ebi_set_buswidth(struct stm32_fmc2_ebi *ebi,
473 const struct stm32_fmc2_prop *prop,
479 case FMC2_BUSWIDTH_8:
480 val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_8);
482 case FMC2_BUSWIDTH_16:
483 val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_16);
486 /* Buswidth not supported */
490 clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_MWID, val);
495 static int stm32_fmc2_ebi_set_cpsize(struct stm32_fmc2_ebi *ebi,
496 const struct stm32_fmc2_prop *prop,
503 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_0);
505 case FMC2_CPSIZE_128:
506 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_128);
508 case FMC2_CPSIZE_256:
509 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_256);
511 case FMC2_CPSIZE_512:
512 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_512);
514 case FMC2_CPSIZE_1024:
515 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_1024);
518 /* Cpsize not supported */
522 clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_CPSIZE, val);
527 static int stm32_fmc2_ebi_set_bl_setup(struct stm32_fmc2_ebi *ebi,
528 const struct stm32_fmc2_prop *prop,
533 val = min_t(u32, setup, FMC2_BCR_NBLSET_MAX);
534 val = FIELD_PREP(FMC2_BCR_NBLSET, val);
535 clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_NBLSET, val);
540 static int stm32_fmc2_ebi_set_address_setup(struct stm32_fmc2_ebi *ebi,
541 const struct stm32_fmc2_prop *prop,
544 u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
545 u32 bxtr = prop->reg_type == FMC2_REG_BWTR ?
546 readl(ebi->io_base + FMC2_BWTR(cs)) :
547 readl(ebi->io_base + FMC2_BTR(cs));
548 u32 reg, val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
551 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®);
555 if ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN)
556 val = clamp_val(setup, 1, FMC2_BXTR_ADDSET_MAX);
558 val = min_t(u32, setup, FMC2_BXTR_ADDSET_MAX);
559 val = FIELD_PREP(FMC2_BXTR_ADDSET, val);
560 clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_ADDSET, val);
565 static int stm32_fmc2_ebi_set_address_hold(struct stm32_fmc2_ebi *ebi,
566 const struct stm32_fmc2_prop *prop,
572 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®);
576 val = clamp_val(setup, 1, FMC2_BXTR_ADDHLD_MAX);
577 val = FIELD_PREP(FMC2_BXTR_ADDHLD, val);
578 clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_ADDHLD, val);
583 static int stm32_fmc2_ebi_set_data_setup(struct stm32_fmc2_ebi *ebi,
584 const struct stm32_fmc2_prop *prop,
590 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®);
594 val = clamp_val(setup, 1, FMC2_BXTR_DATAST_MAX);
595 val = FIELD_PREP(FMC2_BXTR_DATAST, val);
596 clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_DATAST, val);
601 static int stm32_fmc2_ebi_set_bus_turnaround(struct stm32_fmc2_ebi *ebi,
602 const struct stm32_fmc2_prop *prop,
608 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®);
612 val = setup ? min_t(u32, setup - 1, FMC2_BXTR_BUSTURN_MAX) : 0;
613 val = FIELD_PREP(FMC2_BXTR_BUSTURN, val);
614 clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_BUSTURN, val);
619 static int stm32_fmc2_ebi_set_data_hold(struct stm32_fmc2_ebi *ebi,
620 const struct stm32_fmc2_prop *prop,
626 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®);
630 if (prop->reg_type == FMC2_REG_BWTR)
631 val = setup ? min_t(u32, setup - 1, FMC2_BXTR_DATAHLD_MAX) : 0;
633 val = min_t(u32, setup, FMC2_BXTR_DATAHLD_MAX);
634 val = FIELD_PREP(FMC2_BXTR_DATAHLD, val);
635 clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_DATAHLD, val);
640 static int stm32_fmc2_ebi_set_clk_period(struct stm32_fmc2_ebi *ebi,
641 const struct stm32_fmc2_prop *prop,
646 val = setup ? clamp_val(setup - 1, 1, FMC2_BTR_CLKDIV_MAX) : 1;
647 val = FIELD_PREP(FMC2_BTR_CLKDIV, val);
648 clrsetbits_le32(ebi->io_base + FMC2_BTR(cs), FMC2_BTR_CLKDIV, val);
653 static int stm32_fmc2_ebi_set_data_latency(struct stm32_fmc2_ebi *ebi,
654 const struct stm32_fmc2_prop *prop,
659 val = setup > 1 ? min_t(u32, setup - 2, FMC2_BTR_DATLAT_MAX) : 0;
660 val = FIELD_PREP(FMC2_BTR_DATLAT, val);
661 clrsetbits_le32(ebi->io_base + FMC2_BTR(cs), FMC2_BTR_DATLAT, val);
666 static int stm32_fmc2_ebi_set_max_low_pulse(struct stm32_fmc2_ebi *ebi,
667 const struct stm32_fmc2_prop *prop,
670 u32 old_val, new_val, pcscntr;
675 pcscntr = readl(ebi->io_base + FMC2_PCSCNTR);
677 /* Enable counter for the bank */
678 setbits_le32(ebi->io_base + FMC2_PCSCNTR, FMC2_PCSCNTR_CNTBEN(cs));
680 new_val = min_t(u32, setup - 1, FMC2_PCSCNTR_CSCOUNT_MAX);
681 old_val = FIELD_GET(FMC2_PCSCNTR_CSCOUNT, pcscntr);
682 if (old_val && new_val > old_val)
683 /* Keep current counter value */
686 new_val = FIELD_PREP(FMC2_PCSCNTR_CSCOUNT, new_val);
687 clrsetbits_le32(ebi->io_base + FMC2_PCSCNTR,
688 FMC2_PCSCNTR_CSCOUNT, new_val);
693 static const struct stm32_fmc2_prop stm32_fmc2_child_props[] = {
694 /* st,fmc2-ebi-cs-trans-type must be the first property */
696 .name = "st,fmc2-ebi-cs-transaction-type",
698 .set = stm32_fmc2_ebi_set_trans_type,
701 .name = "st,fmc2-ebi-cs-cclk-enable",
703 .reg_type = FMC2_REG_BCR,
704 .reg_mask = FMC2_BCR1_CCLKEN,
705 .check = stm32_fmc2_ebi_check_cclk,
706 .set = stm32_fmc2_ebi_set_bit_field,
709 .name = "st,fmc2-ebi-cs-mux-enable",
711 .reg_type = FMC2_REG_BCR,
712 .reg_mask = FMC2_BCR_MUXEN,
713 .check = stm32_fmc2_ebi_check_mux,
714 .set = stm32_fmc2_ebi_set_bit_field,
717 .name = "st,fmc2-ebi-cs-buswidth",
718 .reset_val = FMC2_BUSWIDTH_16,
719 .set = stm32_fmc2_ebi_set_buswidth,
722 .name = "st,fmc2-ebi-cs-waitpol-high",
724 .reg_type = FMC2_REG_BCR,
725 .reg_mask = FMC2_BCR_WAITPOL,
726 .set = stm32_fmc2_ebi_set_bit_field,
729 .name = "st,fmc2-ebi-cs-waitcfg-enable",
731 .reg_type = FMC2_REG_BCR,
732 .reg_mask = FMC2_BCR_WAITCFG,
733 .check = stm32_fmc2_ebi_check_waitcfg,
734 .set = stm32_fmc2_ebi_set_bit_field,
737 .name = "st,fmc2-ebi-cs-wait-enable",
739 .reg_type = FMC2_REG_BCR,
740 .reg_mask = FMC2_BCR_WAITEN,
741 .check = stm32_fmc2_ebi_check_sync_trans,
742 .set = stm32_fmc2_ebi_set_bit_field,
745 .name = "st,fmc2-ebi-cs-asyncwait-enable",
747 .reg_type = FMC2_REG_BCR,
748 .reg_mask = FMC2_BCR_ASYNCWAIT,
749 .check = stm32_fmc2_ebi_check_async_trans,
750 .set = stm32_fmc2_ebi_set_bit_field,
753 .name = "st,fmc2-ebi-cs-cpsize",
754 .check = stm32_fmc2_ebi_check_cpsize,
755 .set = stm32_fmc2_ebi_set_cpsize,
758 .name = "st,fmc2-ebi-cs-byte-lane-setup-ns",
759 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
760 .set = stm32_fmc2_ebi_set_bl_setup,
763 .name = "st,fmc2-ebi-cs-address-setup-ns",
764 .reg_type = FMC2_REG_BTR,
765 .reset_val = FMC2_BXTR_ADDSET_MAX,
766 .check = stm32_fmc2_ebi_check_async_trans,
767 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
768 .set = stm32_fmc2_ebi_set_address_setup,
771 .name = "st,fmc2-ebi-cs-address-hold-ns",
772 .reg_type = FMC2_REG_BTR,
773 .reset_val = FMC2_BXTR_ADDHLD_MAX,
774 .check = stm32_fmc2_ebi_check_address_hold,
775 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
776 .set = stm32_fmc2_ebi_set_address_hold,
779 .name = "st,fmc2-ebi-cs-data-setup-ns",
780 .reg_type = FMC2_REG_BTR,
781 .reset_val = FMC2_BXTR_DATAST_MAX,
782 .check = stm32_fmc2_ebi_check_async_trans,
783 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
784 .set = stm32_fmc2_ebi_set_data_setup,
787 .name = "st,fmc2-ebi-cs-bus-turnaround-ns",
788 .reg_type = FMC2_REG_BTR,
789 .reset_val = FMC2_BXTR_BUSTURN_MAX + 1,
790 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
791 .set = stm32_fmc2_ebi_set_bus_turnaround,
794 .name = "st,fmc2-ebi-cs-data-hold-ns",
795 .reg_type = FMC2_REG_BTR,
796 .check = stm32_fmc2_ebi_check_async_trans,
797 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
798 .set = stm32_fmc2_ebi_set_data_hold,
801 .name = "st,fmc2-ebi-cs-clk-period-ns",
802 .reset_val = FMC2_BTR_CLKDIV_MAX + 1,
803 .check = stm32_fmc2_ebi_check_clk_period,
804 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
805 .set = stm32_fmc2_ebi_set_clk_period,
808 .name = "st,fmc2-ebi-cs-data-latency-ns",
809 .check = stm32_fmc2_ebi_check_sync_trans,
810 .calculate = stm32_fmc2_ebi_ns_to_clk_period,
811 .set = stm32_fmc2_ebi_set_data_latency,
814 .name = "st,fmc2-ebi-cs-write-address-setup-ns",
815 .reg_type = FMC2_REG_BWTR,
816 .reset_val = FMC2_BXTR_ADDSET_MAX,
817 .check = stm32_fmc2_ebi_check_async_trans,
818 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
819 .set = stm32_fmc2_ebi_set_address_setup,
822 .name = "st,fmc2-ebi-cs-write-address-hold-ns",
823 .reg_type = FMC2_REG_BWTR,
824 .reset_val = FMC2_BXTR_ADDHLD_MAX,
825 .check = stm32_fmc2_ebi_check_address_hold,
826 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
827 .set = stm32_fmc2_ebi_set_address_hold,
830 .name = "st,fmc2-ebi-cs-write-data-setup-ns",
831 .reg_type = FMC2_REG_BWTR,
832 .reset_val = FMC2_BXTR_DATAST_MAX,
833 .check = stm32_fmc2_ebi_check_async_trans,
834 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
835 .set = stm32_fmc2_ebi_set_data_setup,
838 .name = "st,fmc2-ebi-cs-write-bus-turnaround-ns",
839 .reg_type = FMC2_REG_BWTR,
840 .reset_val = FMC2_BXTR_BUSTURN_MAX + 1,
841 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
842 .set = stm32_fmc2_ebi_set_bus_turnaround,
845 .name = "st,fmc2-ebi-cs-write-data-hold-ns",
846 .reg_type = FMC2_REG_BWTR,
847 .check = stm32_fmc2_ebi_check_async_trans,
848 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
849 .set = stm32_fmc2_ebi_set_data_hold,
852 .name = "st,fmc2-ebi-cs-max-low-pulse-ns",
853 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
854 .set = stm32_fmc2_ebi_set_max_low_pulse,
858 static int stm32_fmc2_ebi_parse_prop(struct stm32_fmc2_ebi *ebi,
860 const struct stm32_fmc2_prop *prop,
866 log_err("property %s is not well defined\n", prop->name);
870 if (prop->check && prop->check(ebi, prop, cs))
871 /* Skip this property */
877 bprop = ofnode_read_bool(node, prop->name);
878 if (prop->mprop && !bprop) {
879 log_err("mandatory property %s not defined in the device tree\n",
890 ret = ofnode_read_u32(node, prop->name, &val);
891 if (prop->mprop && ret) {
892 log_err("mandatory property %s not defined in the device tree\n",
898 setup = prop->reset_val;
899 else if (prop->calculate)
900 setup = prop->calculate(ebi, cs, val);
905 return prop->set(ebi, prop, cs, setup);
908 static void stm32_fmc2_ebi_enable_bank(struct stm32_fmc2_ebi *ebi, int cs)
910 setbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_MBKEN);
913 static void stm32_fmc2_ebi_disable_bank(struct stm32_fmc2_ebi *ebi, int cs)
915 clrbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_MBKEN);
918 /* NWAIT signal can not be connected to EBI controller and NAND controller */
919 static bool stm32_fmc2_ebi_nwait_used_by_ctrls(struct stm32_fmc2_ebi *ebi)
924 for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
925 if (!(ebi->bank_assigned & BIT(cs)))
928 bcr = readl(ebi->io_base + FMC2_BCR(cs));
929 if ((bcr & FMC2_BCR_WAITEN || bcr & FMC2_BCR_ASYNCWAIT) &&
930 ebi->bank_assigned & BIT(FMC2_NAND))
937 static void stm32_fmc2_ebi_enable(struct stm32_fmc2_ebi *ebi)
939 setbits_le32(ebi->io_base + FMC2_BCR1, FMC2_BCR1_FMC2EN);
942 static int stm32_fmc2_ebi_setup_cs(struct stm32_fmc2_ebi *ebi,
948 stm32_fmc2_ebi_disable_bank(ebi, cs);
950 for (i = 0; i < ARRAY_SIZE(stm32_fmc2_child_props); i++) {
951 const struct stm32_fmc2_prop *p = &stm32_fmc2_child_props[i];
953 ret = stm32_fmc2_ebi_parse_prop(ebi, node, p, cs);
955 log_err("property %s could not be set: %d\n",
961 stm32_fmc2_ebi_enable_bank(ebi, cs);
966 static int stm32_fmc2_ebi_parse_dt(struct udevice *dev,
967 struct stm32_fmc2_ebi *ebi)
970 bool child_found = false;
974 dev_for_each_subnode(child, dev) {
975 ret = ofnode_read_u32(child, "reg", &bank);
977 dev_err(dev, "could not retrieve reg property: %d\n", ret);
981 if (bank >= FMC2_MAX_BANKS) {
982 dev_err(dev, "invalid reg value: %d\n", bank);
986 if (ebi->bank_assigned & BIT(bank)) {
987 dev_err(dev, "bank already assigned: %d\n", bank);
991 if (bank < FMC2_MAX_EBI_CE) {
992 ret = stm32_fmc2_ebi_setup_cs(ebi, child, bank);
994 dev_err(dev, "setup chip select %d failed: %d\n", bank, ret);
999 ebi->bank_assigned |= BIT(bank);
1004 dev_warn(dev, "no subnodes found, disable the driver.\n");
1008 if (stm32_fmc2_ebi_nwait_used_by_ctrls(ebi)) {
1009 dev_err(dev, "NWAIT signal connected to EBI and NAND controllers\n");
1013 stm32_fmc2_ebi_enable(ebi);
1018 static int stm32_fmc2_ebi_probe(struct udevice *dev)
1020 struct stm32_fmc2_ebi *ebi = dev_get_priv(dev);
1021 struct reset_ctl reset;
1024 ebi->io_base = dev_read_addr(dev);
1025 if (ebi->io_base == FDT_ADDR_T_NONE)
1028 ret = clk_get_by_index(dev, 0, &ebi->clk);
1032 ret = clk_enable(&ebi->clk);
1036 ret = reset_get_by_index(dev, 0, &reset);
1038 reset_assert(&reset);
1040 reset_deassert(&reset);
1043 return stm32_fmc2_ebi_parse_dt(dev, ebi);
1046 static const struct udevice_id stm32_fmc2_ebi_match[] = {
1047 {.compatible = "st,stm32mp1-fmc2-ebi"},
1051 U_BOOT_DRIVER(stm32_fmc2_ebi) = {
1052 .name = "stm32_fmc2_ebi",
1054 .of_match = stm32_fmc2_ebi_match,
1055 .probe = stm32_fmc2_ebi_probe,
1056 .priv_auto = sizeof(struct stm32_fmc2_ebi),
1057 .bind = dm_scan_fdt_dev,