drivers/memory/stm32-fmc2-ebi.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) STMicroelectronics 2020
   4  */
   5
   6 #define LOG_CATEGORY UCLASS_NOP
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <reset.h>
  12 #include <dm/device_compat.h>
  13 #include <linux/bitfield.h>
  14 #include <linux/err.h>
  15 #include <linux/iopoll.h>
  16 #include <linux/ioport.h>
  17
  18 /* FMC2 Controller Registers */
  19 #define FMC2_BCR1                       0x0
  20 #define FMC2_BTR1                       0x4
  21 #define FMC2_BCR(x)                     ((x) * 0x8 + FMC2_BCR1)
  22 #define FMC2_BTR(x)                     ((x) * 0x8 + FMC2_BTR1)
  23 #define FMC2_PCSCNTR                    0x20
  24 #define FMC2_BWTR1                      0x104
  25 #define FMC2_BWTR(x)                    ((x) * 0x8 + FMC2_BWTR1)
  26
  27 /* Register: FMC2_BCR1 */
  28 #define FMC2_BCR1_CCLKEN                BIT(20)
  29 #define FMC2_BCR1_FMC2EN                BIT(31)
  30
  31 /* Register: FMC2_BCRx */
  32 #define FMC2_BCR_MBKEN                  BIT(0)
  33 #define FMC2_BCR_MUXEN                  BIT(1)
  34 #define FMC2_BCR_MTYP                   GENMASK(3, 2)
  35 #define FMC2_BCR_MWID                   GENMASK(5, 4)
  36 #define FMC2_BCR_FACCEN                 BIT(6)
  37 #define FMC2_BCR_BURSTEN                BIT(8)
  38 #define FMC2_BCR_WAITPOL                BIT(9)
  39 #define FMC2_BCR_WAITCFG                BIT(11)
  40 #define FMC2_BCR_WREN                   BIT(12)
  41 #define FMC2_BCR_WAITEN                 BIT(13)
  42 #define FMC2_BCR_EXTMOD                 BIT(14)
  43 #define FMC2_BCR_ASYNCWAIT              BIT(15)
  44 #define FMC2_BCR_CPSIZE                 GENMASK(18, 16)
  45 #define FMC2_BCR_CBURSTRW               BIT(19)
  46 #define FMC2_BCR_NBLSET                 GENMASK(23, 22)
  47
  48 /* Register: FMC2_BTRx/FMC2_BWTRx */
  49 #define FMC2_BXTR_ADDSET                GENMASK(3, 0)
  50 #define FMC2_BXTR_ADDHLD                GENMASK(7, 4)
  51 #define FMC2_BXTR_DATAST                GENMASK(15, 8)
  52 #define FMC2_BXTR_BUSTURN               GENMASK(19, 16)
  53 #define FMC2_BTR_CLKDIV                 GENMASK(23, 20)
  54 #define FMC2_BTR_DATLAT                 GENMASK(27, 24)
  55 #define FMC2_BXTR_ACCMOD                GENMASK(29, 28)
  56 #define FMC2_BXTR_DATAHLD               GENMASK(31, 30)
  57
  58 /* Register: FMC2_PCSCNTR */
  59 #define FMC2_PCSCNTR_CSCOUNT            GENMASK(15, 0)
  60 #define FMC2_PCSCNTR_CNTBEN(x)          BIT((x) + 16)
  61
  62 #define FMC2_MAX_EBI_CE                 4
  63 #define FMC2_MAX_BANKS                  5
  64
  65 #define FMC2_BCR_CPSIZE_0               0x0
  66 #define FMC2_BCR_CPSIZE_128             0x1
  67 #define FMC2_BCR_CPSIZE_256             0x2
  68 #define FMC2_BCR_CPSIZE_512             0x3
  69 #define FMC2_BCR_CPSIZE_1024            0x4
  70
  71 #define FMC2_BCR_MWID_8                 0x0
  72 #define FMC2_BCR_MWID_16                0x1
  73
  74 #define FMC2_BCR_MTYP_SRAM              0x0
  75 #define FMC2_BCR_MTYP_PSRAM             0x1
  76 #define FMC2_BCR_MTYP_NOR               0x2
  77
  78 #define FMC2_BXTR_EXTMOD_A              0x0
  79 #define FMC2_BXTR_EXTMOD_B              0x1
  80 #define FMC2_BXTR_EXTMOD_C              0x2
  81 #define FMC2_BXTR_EXTMOD_D              0x3
  82
  83 #define FMC2_BCR_NBLSET_MAX             0x3
  84 #define FMC2_BXTR_ADDSET_MAX            0xf
  85 #define FMC2_BXTR_ADDHLD_MAX            0xf
  86 #define FMC2_BXTR_DATAST_MAX            0xff
  87 #define FMC2_BXTR_BUSTURN_MAX           0xf
  88 #define FMC2_BXTR_DATAHLD_MAX           0x3
  89 #define FMC2_BTR_CLKDIV_MAX             0xf
  90 #define FMC2_BTR_DATLAT_MAX             0xf
  91 #define FMC2_PCSCNTR_CSCOUNT_MAX        0xff
  92
  93 #define FMC2_NSEC_PER_SEC               1000000000L
  94
  95 enum stm32_fmc2_ebi_bank {
  96         FMC2_EBI1 = 0,
  97         FMC2_EBI2,
  98         FMC2_EBI3,
  99         FMC2_EBI4,
 100         FMC2_NAND
 101 };
 102
 103 enum stm32_fmc2_ebi_register_type {
 104         FMC2_REG_BCR = 1,
 105         FMC2_REG_BTR,
 106         FMC2_REG_BWTR,
 107         FMC2_REG_PCSCNTR
 108 };
 109
 110 enum stm32_fmc2_ebi_transaction_type {
 111         FMC2_ASYNC_MODE_1_SRAM = 0,
 112         FMC2_ASYNC_MODE_1_PSRAM,
 113         FMC2_ASYNC_MODE_A_SRAM,
 114         FMC2_ASYNC_MODE_A_PSRAM,
 115         FMC2_ASYNC_MODE_2_NOR,
 116         FMC2_ASYNC_MODE_B_NOR,
 117         FMC2_ASYNC_MODE_C_NOR,
 118         FMC2_ASYNC_MODE_D_NOR,
 119         FMC2_SYNC_READ_SYNC_WRITE_PSRAM,
 120         FMC2_SYNC_READ_ASYNC_WRITE_PSRAM,
 121         FMC2_SYNC_READ_SYNC_WRITE_NOR,
 122         FMC2_SYNC_READ_ASYNC_WRITE_NOR
 123 };
 124
 125 enum stm32_fmc2_ebi_buswidth {
 126         FMC2_BUSWIDTH_8 = 8,
 127         FMC2_BUSWIDTH_16 = 16
 128 };
 129
 130 enum stm32_fmc2_ebi_cpsize {
 131         FMC2_CPSIZE_0 = 0,
 132         FMC2_CPSIZE_128 = 128,
 133         FMC2_CPSIZE_256 = 256,
 134         FMC2_CPSIZE_512 = 512,
 135         FMC2_CPSIZE_1024 = 1024
 136 };
 137
 138 struct stm32_fmc2_ebi {
 139         struct clk clk;
 140         fdt_addr_t io_base;
 141         u8 bank_assigned;
 142 };
 143
 144 /*
 145  * struct stm32_fmc2_prop - STM32 FMC2 EBI property
 146  * @name: the device tree binding name of the property
 147  * @bprop: indicate that it is a boolean property
 148  * @mprop: indicate that it is a mandatory property
 149  * @reg_type: the register that have to be modified
 150  * @reg_mask: the bit that have to be modified in the selected register
 151  *            in case of it is a boolean property
 152  * @reset_val: the default value that have to be set in case the property
 153  *             has not been defined in the device tree
 154  * @check: this callback ckecks that the property is compliant with the
 155  *         transaction type selected
 156  * @calculate: this callback is called to calculate for exemple a timing
 157  *             set in nanoseconds in the device tree in clock cycles or in
 158  *             clock period
 159  * @set: this callback applies the values in the registers
 160  */
 161 struct stm32_fmc2_prop {
 162         const char *name;
 163         bool bprop;
 164         bool mprop;
 165         int reg_type;
 166         u32 reg_mask;
 167         u32 reset_val;
 168         int (*check)(struct stm32_fmc2_ebi *ebi,
 169                      const struct stm32_fmc2_prop *prop, int cs);
 170         u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
 171         int (*set)(struct stm32_fmc2_ebi *ebi,
 172                    const struct stm32_fmc2_prop *prop,
 173                    int cs, u32 setup);
 174 };
 175
 176 static int stm32_fmc2_ebi_check_mux(struct stm32_fmc2_ebi *ebi,
 177                                     const struct stm32_fmc2_prop *prop,
 178                                     int cs)
 179 {
 180         u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 181
 182         if (bcr & FMC2_BCR_MTYP)
 183                 return 0;
 184
 185         return -EINVAL;
 186 }
 187
 188 static int stm32_fmc2_ebi_check_waitcfg(struct stm32_fmc2_ebi *ebi,
 189                                         const struct stm32_fmc2_prop *prop,
 190                                         int cs)
 191 {
 192         u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 193         u32 val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 194
 195         if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN)
 196                 return 0;
 197
 198         return -EINVAL;
 199 }
 200
 201 static int stm32_fmc2_ebi_check_sync_trans(struct stm32_fmc2_ebi *ebi,
 202                                            const struct stm32_fmc2_prop *prop,
 203                                            int cs)
 204 {
 205         u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 206
 207         if (bcr & FMC2_BCR_BURSTEN)
 208                 return 0;
 209
 210         return -EINVAL;
 211 }
 212
 213 static int stm32_fmc2_ebi_check_async_trans(struct stm32_fmc2_ebi *ebi,
 214                                             const struct stm32_fmc2_prop *prop,
 215                                             int cs)
 216 {
 217         u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 218
 219         if (!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW))
 220                 return 0;
 221
 222         return -EINVAL;
 223 }
 224
 225 static int stm32_fmc2_ebi_check_cpsize(struct stm32_fmc2_ebi *ebi,
 226                                        const struct stm32_fmc2_prop *prop,
 227                                        int cs)
 228 {
 229         u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 230         u32 val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
 231
 232         if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN)
 233                 return 0;
 234
 235         return -EINVAL;
 236 }
 237
 238 static int stm32_fmc2_ebi_check_address_hold(struct stm32_fmc2_ebi *ebi,
 239                                              const struct stm32_fmc2_prop *prop,
 240                                              int cs)
 241 {
 242         u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 243         u32 bxtr = prop->reg_type == FMC2_REG_BWTR ?
 244                    readl(ebi->io_base + FMC2_BWTR(cs)) :
 245                    readl(ebi->io_base + FMC2_BTR(cs));
 246         u32 val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
 247
 248         if ((!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW)) &&
 249             ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN))
 250                 return 0;
 251
 252         return -EINVAL;
 253 }
 254
 255 static int stm32_fmc2_ebi_check_clk_period(struct stm32_fmc2_ebi *ebi,
 256                                            const struct stm32_fmc2_prop *prop,
 257                                            int cs)
 258 {
 259         u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 260         u32 bcr1 = cs ? readl(ebi->io_base + FMC2_BCR1) : bcr;
 261
 262         if (bcr & FMC2_BCR_BURSTEN && (!cs || !(bcr1 & FMC2_BCR1_CCLKEN)))
 263                 return 0;
 264
 265         return -EINVAL;
 266 }
 267
 268 static int stm32_fmc2_ebi_check_cclk(struct stm32_fmc2_ebi *ebi,
 269                                      const struct stm32_fmc2_prop *prop,
 270                                      int cs)
 271 {
 272         if (cs)
 273                 return -EINVAL;
 274
 275         return stm32_fmc2_ebi_check_sync_trans(ebi, prop, cs);
 276 }
 277
 278 static u32 stm32_fmc2_ebi_ns_to_clock_cycles(struct stm32_fmc2_ebi *ebi,
 279                                              int cs, u32 setup)
 280 {
 281         unsigned long hclk = clk_get_rate(&ebi->clk);
 282         unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000);
 283
 284         return DIV_ROUND_UP(setup * 1000, hclkp);
 285 }
 286
 287 static u32 stm32_fmc2_ebi_ns_to_clk_period(struct stm32_fmc2_ebi *ebi,
 288                                            int cs, u32 setup)
 289 {
 290         u32 nb_clk_cycles = stm32_fmc2_ebi_ns_to_clock_cycles(ebi, cs, setup);
 291         u32 bcr = readl(ebi->io_base + FMC2_BCR1);
 292         u32 btr = bcr & FMC2_BCR1_CCLKEN || !cs ?
 293                   readl(ebi->io_base + FMC2_BTR1) :
 294                   readl(ebi->io_base + FMC2_BTR(cs));
 295         u32 clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1;
 296
 297         return DIV_ROUND_UP(nb_clk_cycles, clk_period);
 298 }
 299
 300 static int stm32_fmc2_ebi_get_reg(int reg_type, int cs, u32 *reg)
 301 {
 302         switch (reg_type) {
 303         case FMC2_REG_BCR:
 304                 *reg = FMC2_BCR(cs);
 305                 break;
 306         case FMC2_REG_BTR:
 307                 *reg = FMC2_BTR(cs);
 308                 break;
 309         case FMC2_REG_BWTR:
 310                 *reg = FMC2_BWTR(cs);
 311                 break;
 312         case FMC2_REG_PCSCNTR:
 313                 *reg = FMC2_PCSCNTR;
 314                 break;
 315         default:
 316                 return -EINVAL;
 317         }
 318
 319         return 0;
 320 }
 321
 322 static int stm32_fmc2_ebi_set_bit_field(struct stm32_fmc2_ebi *ebi,
 323                                         const struct stm32_fmc2_prop *prop,
 324                                         int cs, u32 setup)
 325 {
 326         u32 reg;
 327         int ret;
 328
 329         ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
 330         if (ret)
 331                 return ret;
 332
 333         clrsetbits_le32(ebi->io_base + reg, prop->reg_mask,
 334                         setup ? prop->reg_mask : 0);
 335
 336         return 0;
 337 }
 338
 339 static int stm32_fmc2_ebi_set_trans_type(struct stm32_fmc2_ebi *ebi,
 340                                          const struct stm32_fmc2_prop *prop,
 341                                          int cs, u32 setup)
 342 {
 343         u32 bcr_mask, bcr = FMC2_BCR_WREN;
 344         u32 btr_mask, btr = 0;
 345         u32 bwtr_mask, bwtr = 0;
 346
 347         bwtr_mask = FMC2_BXTR_ACCMOD;
 348         btr_mask = FMC2_BXTR_ACCMOD;
 349         bcr_mask = FMC2_BCR_MUXEN | FMC2_BCR_MTYP | FMC2_BCR_FACCEN |
 350                    FMC2_BCR_WREN | FMC2_BCR_WAITEN | FMC2_BCR_BURSTEN |
 351                    FMC2_BCR_EXTMOD | FMC2_BCR_CBURSTRW;
 352
 353         switch (setup) {
 354         case FMC2_ASYNC_MODE_1_SRAM:
 355                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM);
 356                 /*
 357                  * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
 358                  * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
 359                  */
 360                 break;
 361         case FMC2_ASYNC_MODE_1_PSRAM:
 362                 /*
 363                  * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
 364                  * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
 365                  */
 366                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
 367                 break;
 368         case FMC2_ASYNC_MODE_A_SRAM:
 369                 /*
 370                  * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
 371                  * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0
 372                  */
 373                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM);
 374                 bcr |= FMC2_BCR_EXTMOD;
 375                 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
 376                 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
 377                 break;
 378         case FMC2_ASYNC_MODE_A_PSRAM:
 379                 /*
 380                  * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
 381                  * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0
 382                  */
 383                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
 384                 bcr |= FMC2_BCR_EXTMOD;
 385                 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
 386                 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
 387                 break;
 388         case FMC2_ASYNC_MODE_2_NOR:
 389                 /*
 390                  * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
 391                  * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
 392                  */
 393                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 394                 bcr |= FMC2_BCR_FACCEN;
 395                 break;
 396         case FMC2_ASYNC_MODE_B_NOR:
 397                 /*
 398                  * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
 399                  * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 1
 400                  */
 401                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 402                 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
 403                 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B);
 404                 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B);
 405                 break;
 406         case FMC2_ASYNC_MODE_C_NOR:
 407                 /*
 408                  * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
 409                  * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 2
 410                  */
 411                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 412                 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
 413                 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C);
 414                 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C);
 415                 break;
 416         case FMC2_ASYNC_MODE_D_NOR:
 417                 /*
 418                  * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
 419                  * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 3
 420                  */
 421                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 422                 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
 423                 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
 424                 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
 425                 break;
 426         case FMC2_SYNC_READ_SYNC_WRITE_PSRAM:
 427                 /*
 428                  * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0,
 429                  * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0
 430                  */
 431                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
 432                 bcr |= FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW;
 433                 break;
 434         case FMC2_SYNC_READ_ASYNC_WRITE_PSRAM:
 435                 /*
 436                  * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0,
 437                  * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
 438                  */
 439                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
 440                 bcr |= FMC2_BCR_BURSTEN;
 441                 break;
 442         case FMC2_SYNC_READ_SYNC_WRITE_NOR:
 443                 /*
 444                  * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0,
 445                  * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0
 446                  */
 447                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 448                 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW;
 449                 break;
 450         case FMC2_SYNC_READ_ASYNC_WRITE_NOR:
 451                 /*
 452                  * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0,
 453                  * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
 454                  */
 455                 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
 456                 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN;
 457                 break;
 458         default:
 459                 /* Type of transaction not supported */
 460                 return -EINVAL;
 461         }
 462
 463         if (bcr & FMC2_BCR_EXTMOD)
 464                 clrsetbits_le32(ebi->io_base + FMC2_BWTR(cs),
 465                                 bwtr_mask, bwtr);
 466         clrsetbits_le32(ebi->io_base + FMC2_BTR(cs), btr_mask, btr);
 467         clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), bcr_mask, bcr);
 468
 469         return 0;
 470 }
 471
 472 static int stm32_fmc2_ebi_set_buswidth(struct stm32_fmc2_ebi *ebi,
 473                                        const struct stm32_fmc2_prop *prop,
 474                                        int cs, u32 setup)
 475 {
 476         u32 val;
 477
 478         switch (setup) {
 479         case FMC2_BUSWIDTH_8:
 480                 val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_8);
 481                 break;
 482         case FMC2_BUSWIDTH_16:
 483                 val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_16);
 484                 break;
 485         default:
 486                 /* Buswidth not supported */
 487                 return -EINVAL;
 488         }
 489
 490         clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_MWID, val);
 491
 492         return 0;
 493 }
 494
 495 static int stm32_fmc2_ebi_set_cpsize(struct stm32_fmc2_ebi *ebi,
 496                                      const struct stm32_fmc2_prop *prop,
 497                                      int cs, u32 setup)
 498 {
 499         u32 val;
 500
 501         switch (setup) {
 502         case FMC2_CPSIZE_0:
 503                 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_0);
 504                 break;
 505         case FMC2_CPSIZE_128:
 506                 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_128);
 507                 break;
 508         case FMC2_CPSIZE_256:
 509                 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_256);
 510                 break;
 511         case FMC2_CPSIZE_512:
 512                 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_512);
 513                 break;
 514         case FMC2_CPSIZE_1024:
 515                 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_1024);
 516                 break;
 517         default:
 518                 /* Cpsize not supported */
 519                 return -EINVAL;
 520         }
 521
 522         clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_CPSIZE, val);
 523
 524         return 0;
 525 }
 526
 527 static int stm32_fmc2_ebi_set_bl_setup(struct stm32_fmc2_ebi *ebi,
 528                                        const struct stm32_fmc2_prop *prop,
 529                                        int cs, u32 setup)
 530 {
 531         u32 val;
 532
 533         val = min_t(u32, setup, FMC2_BCR_NBLSET_MAX);
 534         val = FIELD_PREP(FMC2_BCR_NBLSET, val);
 535         clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_NBLSET, val);
 536
 537         return 0;
 538 }
 539
 540 static int stm32_fmc2_ebi_set_address_setup(struct stm32_fmc2_ebi *ebi,
 541                                             const struct stm32_fmc2_prop *prop,
 542                                             int cs, u32 setup)
 543 {
 544         u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 545         u32 bxtr = prop->reg_type == FMC2_REG_BWTR ?
 546                    readl(ebi->io_base + FMC2_BWTR(cs)) :
 547                    readl(ebi->io_base + FMC2_BTR(cs));
 548         u32 reg, val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
 549         int ret;
 550
 551         ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
 552         if (ret)
 553                 return ret;
 554
 555         if ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN)
 556                 val = clamp_val(setup, 1, FMC2_BXTR_ADDSET_MAX);
 557         else
 558                 val = min_t(u32, setup, FMC2_BXTR_ADDSET_MAX);
 559         val = FIELD_PREP(FMC2_BXTR_ADDSET, val);
 560         clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_ADDSET, val);
 561
 562         return 0;
 563 }
 564
 565 static int stm32_fmc2_ebi_set_address_hold(struct stm32_fmc2_ebi *ebi,
 566                                            const struct stm32_fmc2_prop *prop,
 567                                            int cs, u32 setup)
 568 {
 569         u32 val, reg;
 570         int ret;
 571
 572         ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
 573         if (ret)
 574                 return ret;
 575
 576         val = clamp_val(setup, 1, FMC2_BXTR_ADDHLD_MAX);
 577         val = FIELD_PREP(FMC2_BXTR_ADDHLD, val);
 578         clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_ADDHLD, val);
 579
 580         return 0;
 581 }
 582
 583 static int stm32_fmc2_ebi_set_data_setup(struct stm32_fmc2_ebi *ebi,
 584                                          const struct stm32_fmc2_prop *prop,
 585                                          int cs, u32 setup)
 586 {
 587         u32 val, reg;
 588         int ret;
 589
 590         ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
 591         if (ret)
 592                 return ret;
 593
 594         val = clamp_val(setup, 1, FMC2_BXTR_DATAST_MAX);
 595         val = FIELD_PREP(FMC2_BXTR_DATAST, val);
 596         clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_DATAST, val);
 597
 598         return 0;
 599 }
 600
 601 static int stm32_fmc2_ebi_set_bus_turnaround(struct stm32_fmc2_ebi *ebi,
 602                                              const struct stm32_fmc2_prop *prop,
 603                                              int cs, u32 setup)
 604 {
 605         u32 val, reg;
 606         int ret;
 607
 608         ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
 609         if (ret)
 610                 return ret;
 611
 612         val = setup ? min_t(u32, setup - 1, FMC2_BXTR_BUSTURN_MAX) : 0;
 613         val = FIELD_PREP(FMC2_BXTR_BUSTURN, val);
 614         clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_BUSTURN, val);
 615
 616         return 0;
 617 }
 618
 619 static int stm32_fmc2_ebi_set_data_hold(struct stm32_fmc2_ebi *ebi,
 620                                         const struct stm32_fmc2_prop *prop,
 621                                         int cs, u32 setup)
 622 {
 623         u32 val, reg;
 624         int ret;
 625
 626         ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
 627         if (ret)
 628                 return ret;
 629
 630         if (prop->reg_type == FMC2_REG_BWTR)
 631                 val = setup ? min_t(u32, setup - 1, FMC2_BXTR_DATAHLD_MAX) : 0;
 632         else
 633                 val = min_t(u32, setup, FMC2_BXTR_DATAHLD_MAX);
 634         val = FIELD_PREP(FMC2_BXTR_DATAHLD, val);
 635         clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_DATAHLD, val);
 636
 637         return 0;
 638 }
 639
 640 static int stm32_fmc2_ebi_set_clk_period(struct stm32_fmc2_ebi *ebi,
 641                                          const struct stm32_fmc2_prop *prop,
 642                                          int cs, u32 setup)
 643 {
 644         u32 val;
 645
 646         val = setup ? clamp_val(setup - 1, 1, FMC2_BTR_CLKDIV_MAX) : 1;
 647         val = FIELD_PREP(FMC2_BTR_CLKDIV, val);
 648         clrsetbits_le32(ebi->io_base + FMC2_BTR(cs), FMC2_BTR_CLKDIV, val);
 649
 650         return 0;
 651 }
 652
 653 static int stm32_fmc2_ebi_set_data_latency(struct stm32_fmc2_ebi *ebi,
 654                                            const struct stm32_fmc2_prop *prop,
 655                                            int cs, u32 setup)
 656 {
 657         u32 val;
 658
 659         val = setup > 1 ? min_t(u32, setup - 2, FMC2_BTR_DATLAT_MAX) : 0;
 660         val = FIELD_PREP(FMC2_BTR_DATLAT, val);
 661         clrsetbits_le32(ebi->io_base + FMC2_BTR(cs), FMC2_BTR_DATLAT, val);
 662
 663         return 0;
 664 }
 665
 666 static int stm32_fmc2_ebi_set_max_low_pulse(struct stm32_fmc2_ebi *ebi,
 667                                             const struct stm32_fmc2_prop *prop,
 668                                             int cs, u32 setup)
 669 {
 670         u32 old_val, new_val, pcscntr;
 671
 672         if (setup < 1)
 673                 return 0;
 674
 675         pcscntr = readl(ebi->io_base + FMC2_PCSCNTR);
 676
 677         /* Enable counter for the bank */
 678         setbits_le32(ebi->io_base + FMC2_PCSCNTR, FMC2_PCSCNTR_CNTBEN(cs));
 679
 680         new_val = min_t(u32, setup - 1, FMC2_PCSCNTR_CSCOUNT_MAX);
 681         old_val = FIELD_GET(FMC2_PCSCNTR_CSCOUNT, pcscntr);
 682         if (old_val && new_val > old_val)
 683                 /* Keep current counter value */
 684                 return 0;
 685
 686         new_val = FIELD_PREP(FMC2_PCSCNTR_CSCOUNT, new_val);
 687         clrsetbits_le32(ebi->io_base + FMC2_PCSCNTR,
 688                         FMC2_PCSCNTR_CSCOUNT, new_val);
 689
 690         return 0;
 691 }
 692
 693 static const struct stm32_fmc2_prop stm32_fmc2_child_props[] = {
 694         /* st,fmc2-ebi-cs-trans-type must be the first property */
 695         {
 696                 .name = "st,fmc2-ebi-cs-transaction-type",
 697                 .mprop = true,
 698                 .set = stm32_fmc2_ebi_set_trans_type,
 699         },
 700         {
 701                 .name = "st,fmc2-ebi-cs-cclk-enable",
 702                 .bprop = true,
 703                 .reg_type = FMC2_REG_BCR,
 704                 .reg_mask = FMC2_BCR1_CCLKEN,
 705                 .check = stm32_fmc2_ebi_check_cclk,
 706                 .set = stm32_fmc2_ebi_set_bit_field,
 707         },
 708         {
 709                 .name = "st,fmc2-ebi-cs-mux-enable",
 710                 .bprop = true,
 711                 .reg_type = FMC2_REG_BCR,
 712                 .reg_mask = FMC2_BCR_MUXEN,
 713                 .check = stm32_fmc2_ebi_check_mux,
 714                 .set = stm32_fmc2_ebi_set_bit_field,
 715         },
 716         {
 717                 .name = "st,fmc2-ebi-cs-buswidth",
 718                 .reset_val = FMC2_BUSWIDTH_16,
 719                 .set = stm32_fmc2_ebi_set_buswidth,
 720         },
 721         {
 722                 .name = "st,fmc2-ebi-cs-waitpol-high",
 723                 .bprop = true,
 724                 .reg_type = FMC2_REG_BCR,
 725                 .reg_mask = FMC2_BCR_WAITPOL,
 726                 .set = stm32_fmc2_ebi_set_bit_field,
 727         },
 728         {
 729                 .name = "st,fmc2-ebi-cs-waitcfg-enable",
 730                 .bprop = true,
 731                 .reg_type = FMC2_REG_BCR,
 732                 .reg_mask = FMC2_BCR_WAITCFG,
 733                 .check = stm32_fmc2_ebi_check_waitcfg,
 734                 .set = stm32_fmc2_ebi_set_bit_field,
 735         },
 736         {
 737                 .name = "st,fmc2-ebi-cs-wait-enable",
 738                 .bprop = true,
 739                 .reg_type = FMC2_REG_BCR,
 740                 .reg_mask = FMC2_BCR_WAITEN,
 741                 .check = stm32_fmc2_ebi_check_sync_trans,
 742                 .set = stm32_fmc2_ebi_set_bit_field,
 743         },
 744         {
 745                 .name = "st,fmc2-ebi-cs-asyncwait-enable",
 746                 .bprop = true,
 747                 .reg_type = FMC2_REG_BCR,
 748                 .reg_mask = FMC2_BCR_ASYNCWAIT,
 749                 .check = stm32_fmc2_ebi_check_async_trans,
 750                 .set = stm32_fmc2_ebi_set_bit_field,
 751         },
 752         {
 753                 .name = "st,fmc2-ebi-cs-cpsize",
 754                 .check = stm32_fmc2_ebi_check_cpsize,
 755                 .set = stm32_fmc2_ebi_set_cpsize,
 756         },
 757         {
 758                 .name = "st,fmc2-ebi-cs-byte-lane-setup-ns",
 759                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 760                 .set = stm32_fmc2_ebi_set_bl_setup,
 761         },
 762         {
 763                 .name = "st,fmc2-ebi-cs-address-setup-ns",
 764                 .reg_type = FMC2_REG_BTR,
 765                 .reset_val = FMC2_BXTR_ADDSET_MAX,
 766                 .check = stm32_fmc2_ebi_check_async_trans,
 767                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 768                 .set = stm32_fmc2_ebi_set_address_setup,
 769         },
 770         {
 771                 .name = "st,fmc2-ebi-cs-address-hold-ns",
 772                 .reg_type = FMC2_REG_BTR,
 773                 .reset_val = FMC2_BXTR_ADDHLD_MAX,
 774                 .check = stm32_fmc2_ebi_check_address_hold,
 775                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 776                 .set = stm32_fmc2_ebi_set_address_hold,
 777         },
 778         {
 779                 .name = "st,fmc2-ebi-cs-data-setup-ns",
 780                 .reg_type = FMC2_REG_BTR,
 781                 .reset_val = FMC2_BXTR_DATAST_MAX,
 782                 .check = stm32_fmc2_ebi_check_async_trans,
 783                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 784                 .set = stm32_fmc2_ebi_set_data_setup,
 785         },
 786         {
 787                 .name = "st,fmc2-ebi-cs-bus-turnaround-ns",
 788                 .reg_type = FMC2_REG_BTR,
 789                 .reset_val = FMC2_BXTR_BUSTURN_MAX + 1,
 790                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 791                 .set = stm32_fmc2_ebi_set_bus_turnaround,
 792         },
 793         {
 794                 .name = "st,fmc2-ebi-cs-data-hold-ns",
 795                 .reg_type = FMC2_REG_BTR,
 796                 .check = stm32_fmc2_ebi_check_async_trans,
 797                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 798                 .set = stm32_fmc2_ebi_set_data_hold,
 799         },
 800         {
 801                 .name = "st,fmc2-ebi-cs-clk-period-ns",
 802                 .reset_val = FMC2_BTR_CLKDIV_MAX + 1,
 803                 .check = stm32_fmc2_ebi_check_clk_period,
 804                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 805                 .set = stm32_fmc2_ebi_set_clk_period,
 806         },
 807         {
 808                 .name = "st,fmc2-ebi-cs-data-latency-ns",
 809                 .check = stm32_fmc2_ebi_check_sync_trans,
 810                 .calculate = stm32_fmc2_ebi_ns_to_clk_period,
 811                 .set = stm32_fmc2_ebi_set_data_latency,
 812         },
 813         {
 814                 .name = "st,fmc2-ebi-cs-write-address-setup-ns",
 815                 .reg_type = FMC2_REG_BWTR,
 816                 .reset_val = FMC2_BXTR_ADDSET_MAX,
 817                 .check = stm32_fmc2_ebi_check_async_trans,
 818                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 819                 .set = stm32_fmc2_ebi_set_address_setup,
 820         },
 821         {
 822                 .name = "st,fmc2-ebi-cs-write-address-hold-ns",
 823                 .reg_type = FMC2_REG_BWTR,
 824                 .reset_val = FMC2_BXTR_ADDHLD_MAX,
 825                 .check = stm32_fmc2_ebi_check_address_hold,
 826                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 827                 .set = stm32_fmc2_ebi_set_address_hold,
 828         },
 829         {
 830                 .name = "st,fmc2-ebi-cs-write-data-setup-ns",
 831                 .reg_type = FMC2_REG_BWTR,
 832                 .reset_val = FMC2_BXTR_DATAST_MAX,
 833                 .check = stm32_fmc2_ebi_check_async_trans,
 834                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 835                 .set = stm32_fmc2_ebi_set_data_setup,
 836         },
 837         {
 838                 .name = "st,fmc2-ebi-cs-write-bus-turnaround-ns",
 839                 .reg_type = FMC2_REG_BWTR,
 840                 .reset_val = FMC2_BXTR_BUSTURN_MAX + 1,
 841                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 842                 .set = stm32_fmc2_ebi_set_bus_turnaround,
 843         },
 844         {
 845                 .name = "st,fmc2-ebi-cs-write-data-hold-ns",
 846                 .reg_type = FMC2_REG_BWTR,
 847                 .check = stm32_fmc2_ebi_check_async_trans,
 848                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 849                 .set = stm32_fmc2_ebi_set_data_hold,
 850         },
 851         {
 852                 .name = "st,fmc2-ebi-cs-max-low-pulse-ns",
 853                 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
 854                 .set = stm32_fmc2_ebi_set_max_low_pulse,
 855         },
 856 };
 857
 858 static int stm32_fmc2_ebi_parse_prop(struct stm32_fmc2_ebi *ebi,
 859                                      ofnode node,
 860                                      const struct stm32_fmc2_prop *prop,
 861                                      int cs)
 862 {
 863         u32 setup = 0;
 864
 865         if (!prop->set) {
 866                 log_err("property %s is not well defined\n", prop->name);
 867                 return -EINVAL;
 868         }
 869
 870         if (prop->check && prop->check(ebi, prop, cs))
 871                 /* Skip this property */
 872                 return 0;
 873
 874         if (prop->bprop) {
 875                 bool bprop;
 876
 877                 bprop = ofnode_read_bool(node, prop->name);
 878                 if (prop->mprop && !bprop) {
 879                         log_err("mandatory property %s not defined in the device tree\n",
 880                                 prop->name);
 881                         return -EINVAL;
 882                 }
 883
 884                 if (bprop)
 885                         setup = 1;
 886         } else {
 887                 u32 val;
 888                 int ret;
 889
 890                 ret = ofnode_read_u32(node, prop->name, &val);
 891                 if (prop->mprop && ret) {
 892                         log_err("mandatory property %s not defined in the device tree\n",
 893                                 prop->name);
 894                         return ret;
 895                 }
 896
 897                 if (ret)
 898                         setup = prop->reset_val;
 899                 else if (prop->calculate)
 900                         setup = prop->calculate(ebi, cs, val);
 901                 else
 902                         setup = val;
 903         }
 904
 905         return prop->set(ebi, prop, cs, setup);
 906 }
 907
 908 static void stm32_fmc2_ebi_enable_bank(struct stm32_fmc2_ebi *ebi, int cs)
 909 {
 910         setbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_MBKEN);
 911 }
 912
 913 static void stm32_fmc2_ebi_disable_bank(struct stm32_fmc2_ebi *ebi, int cs)
 914 {
 915         clrbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_MBKEN);
 916 }
 917
 918 /* NWAIT signal can not be connected to EBI controller and NAND controller */
 919 static bool stm32_fmc2_ebi_nwait_used_by_ctrls(struct stm32_fmc2_ebi *ebi)
 920 {
 921         unsigned int cs;
 922         u32 bcr;
 923
 924         for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
 925                 if (!(ebi->bank_assigned & BIT(cs)))
 926                         continue;
 927
 928                 bcr = readl(ebi->io_base + FMC2_BCR(cs));
 929                 if ((bcr & FMC2_BCR_WAITEN || bcr & FMC2_BCR_ASYNCWAIT) &&
 930                     ebi->bank_assigned & BIT(FMC2_NAND))
 931                         return true;
 932         }
 933
 934         return false;
 935 }
 936
 937 static void stm32_fmc2_ebi_enable(struct stm32_fmc2_ebi *ebi)
 938 {
 939         setbits_le32(ebi->io_base + FMC2_BCR1, FMC2_BCR1_FMC2EN);
 940 }
 941
 942 static int stm32_fmc2_ebi_setup_cs(struct stm32_fmc2_ebi *ebi,
 943                                    ofnode node, u32 cs)
 944 {
 945         unsigned int i;
 946         int ret;
 947
 948         stm32_fmc2_ebi_disable_bank(ebi, cs);
 949
 950         for (i = 0; i < ARRAY_SIZE(stm32_fmc2_child_props); i++) {
 951                 const struct stm32_fmc2_prop *p = &stm32_fmc2_child_props[i];
 952
 953                 ret = stm32_fmc2_ebi_parse_prop(ebi, node, p, cs);
 954                 if (ret) {
 955                         log_err("property %s could not be set: %d\n",
 956                                 p->name, ret);
 957                         return ret;
 958                 }
 959         }
 960
 961         stm32_fmc2_ebi_enable_bank(ebi, cs);
 962
 963         return 0;
 964 }
 965
 966 static int stm32_fmc2_ebi_parse_dt(struct udevice *dev,
 967                                    struct stm32_fmc2_ebi *ebi)
 968 {
 969         ofnode child;
 970         bool child_found = false;
 971         u32 bank;
 972         int ret;
 973
 974         dev_for_each_subnode(child, dev) {
 975                 ret = ofnode_read_u32(child, "reg", &bank);
 976                 if (ret) {
 977                         dev_err(dev, "could not retrieve reg property: %d\n", ret);
 978                         return ret;
 979                 }
 980
 981                 if (bank >= FMC2_MAX_BANKS) {
 982                         dev_err(dev, "invalid reg value: %d\n", bank);
 983                         return -EINVAL;
 984                 }
 985
 986                 if (ebi->bank_assigned & BIT(bank)) {
 987                         dev_err(dev, "bank already assigned: %d\n", bank);
 988                         return -EINVAL;
 989                 }
 990
 991                 if (bank < FMC2_MAX_EBI_CE) {
 992                         ret = stm32_fmc2_ebi_setup_cs(ebi, child, bank);
 993                         if (ret) {
 994                                 dev_err(dev, "setup chip select %d failed: %d\n", bank, ret);
 995                                 return ret;
 996                         }
 997                 }
 998
 999                 ebi->bank_assigned |= BIT(bank);
1000                 child_found = true;
1001         }
1002
1003         if (!child_found) {
1004                 dev_warn(dev, "no subnodes found, disable the driver.\n");
1005                 return -ENODEV;
1006         }
1007
1008         if (stm32_fmc2_ebi_nwait_used_by_ctrls(ebi)) {
1009                 dev_err(dev, "NWAIT signal connected to EBI and NAND controllers\n");
1010                 return -EINVAL;
1011         }
1012
1013         stm32_fmc2_ebi_enable(ebi);
1014
1015         return 0;
1016 }
1017
1018 static int stm32_fmc2_ebi_probe(struct udevice *dev)
1019 {
1020         struct stm32_fmc2_ebi *ebi = dev_get_priv(dev);
1021         struct reset_ctl reset;
1022         int ret;
1023
1024         ebi->io_base = dev_read_addr(dev);
1025         if (ebi->io_base == FDT_ADDR_T_NONE)
1026                 return -EINVAL;
1027
1028         ret = clk_get_by_index(dev, 0, &ebi->clk);
1029         if (ret)
1030                 return ret;
1031
1032         ret = clk_enable(&ebi->clk);
1033         if (ret)
1034                 return ret;
1035
1036         ret = reset_get_by_index(dev, 0, &reset);
1037         if (!ret) {
1038                 reset_assert(&reset);
1039                 udelay(2);
1040                 reset_deassert(&reset);
1041         }
1042
1043         return stm32_fmc2_ebi_parse_dt(dev, ebi);
1044 }
1045
1046 static const struct udevice_id stm32_fmc2_ebi_match[] = {
1047         {.compatible = "st,stm32mp1-fmc2-ebi"},
1048         { /* Sentinel */ }
1049 };
1050
1051 U_BOOT_DRIVER(stm32_fmc2_ebi) = {
1052         .name = "stm32_fmc2_ebi",
1053         .id = UCLASS_NOP,
1054         .of_match = stm32_fmc2_ebi_match,
1055         .probe = stm32_fmc2_ebi_probe,
1056         .priv_auto      = sizeof(struct stm32_fmc2_ebi),
1057         .bind = dm_scan_fdt_dev,
1058 };