drivers/memory/renesas-rpc-if.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Renesas RPC-IF core driver
   4  *
   5  * Copyright (C) 2018-2019 Renesas Solutions Corp.
   6  * Copyright (C) 2019 Macronix International Co., Ltd.
   7  * Copyright (C) 2019-2020 Cogent Embedded, Inc.
   8  */
   9
  10 #include <linux/bitops.h>
  11 #include <linux/clk.h>
  12 #include <linux/io.h>
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <linux/regmap.h>
  18 #include <linux/reset.h>
  19
  20 #include <memory/renesas-rpc-if.h>
  21
  22 #define RPCIF_CMNCR             0x0000  /* R/W */
  23 #define RPCIF_CMNCR_MD          BIT(31)
  24 #define RPCIF_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
  25 #define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
  26 #define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
  27 #define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
  28 #define RPCIF_CMNCR_MOIIO(val)  (RPCIF_CMNCR_MOIIO0(val) | RPCIF_CMNCR_MOIIO1(val) | \
  29                                  RPCIF_CMNCR_MOIIO2(val) | RPCIF_CMNCR_MOIIO3(val))
  30 #define RPCIF_CMNCR_IO3FV(val)  (((val) & 0x3) << 14) /* documented for RZ/G2L */
  31 #define RPCIF_CMNCR_IO2FV(val)  (((val) & 0x3) << 12) /* documented for RZ/G2L */
  32 #define RPCIF_CMNCR_IO0FV(val)  (((val) & 0x3) << 8)
  33 #define RPCIF_CMNCR_IOFV(val)   (RPCIF_CMNCR_IO0FV(val) | RPCIF_CMNCR_IO2FV(val) | \
  34                                  RPCIF_CMNCR_IO3FV(val))
  35 #define RPCIF_CMNCR_BSZ(val)    (((val) & 0x3) << 0)
  36
  37 #define RPCIF_SSLDR             0x0004  /* R/W */
  38 #define RPCIF_SSLDR_SPNDL(d)    (((d) & 0x7) << 16)
  39 #define RPCIF_SSLDR_SLNDL(d)    (((d) & 0x7) << 8)
  40 #define RPCIF_SSLDR_SCKDL(d)    (((d) & 0x7) << 0)
  41
  42 #define RPCIF_DRCR              0x000C  /* R/W */
  43 #define RPCIF_DRCR_SSLN         BIT(24)
  44 #define RPCIF_DRCR_RBURST(v)    ((((v) - 1) & 0x1F) << 16)
  45 #define RPCIF_DRCR_RCF          BIT(9)
  46 #define RPCIF_DRCR_RBE          BIT(8)
  47 #define RPCIF_DRCR_SSLE         BIT(0)
  48
  49 #define RPCIF_DRCMR             0x0010  /* R/W */
  50 #define RPCIF_DRCMR_CMD(c)      (((c) & 0xFF) << 16)
  51 #define RPCIF_DRCMR_OCMD(c)     (((c) & 0xFF) << 0)
  52
  53 #define RPCIF_DREAR             0x0014  /* R/W */
  54 #define RPCIF_DREAR_EAV(c)      (((c) & 0xF) << 16)
  55 #define RPCIF_DREAR_EAC(c)      (((c) & 0x7) << 0)
  56
  57 #define RPCIF_DROPR             0x0018  /* R/W */
  58
  59 #define RPCIF_DRENR             0x001C  /* R/W */
  60 #define RPCIF_DRENR_CDB(o)      (u32)((((o) & 0x3) << 30))
  61 #define RPCIF_DRENR_OCDB(o)     (((o) & 0x3) << 28)
  62 #define RPCIF_DRENR_ADB(o)      (((o) & 0x3) << 24)
  63 #define RPCIF_DRENR_OPDB(o)     (((o) & 0x3) << 20)
  64 #define RPCIF_DRENR_DRDB(o)     (((o) & 0x3) << 16)
  65 #define RPCIF_DRENR_DME         BIT(15)
  66 #define RPCIF_DRENR_CDE         BIT(14)
  67 #define RPCIF_DRENR_OCDE        BIT(12)
  68 #define RPCIF_DRENR_ADE(v)      (((v) & 0xF) << 8)
  69 #define RPCIF_DRENR_OPDE(v)     (((v) & 0xF) << 4)
  70
  71 #define RPCIF_SMCR              0x0020  /* R/W */
  72 #define RPCIF_SMCR_SSLKP        BIT(8)
  73 #define RPCIF_SMCR_SPIRE        BIT(2)
  74 #define RPCIF_SMCR_SPIWE        BIT(1)
  75 #define RPCIF_SMCR_SPIE         BIT(0)
  76
  77 #define RPCIF_SMCMR             0x0024  /* R/W */
  78 #define RPCIF_SMCMR_CMD(c)      (((c) & 0xFF) << 16)
  79 #define RPCIF_SMCMR_OCMD(c)     (((c) & 0xFF) << 0)
  80
  81 #define RPCIF_SMADR             0x0028  /* R/W */
  82
  83 #define RPCIF_SMOPR             0x002C  /* R/W */
  84 #define RPCIF_SMOPR_OPD3(o)     (((o) & 0xFF) << 24)
  85 #define RPCIF_SMOPR_OPD2(o)     (((o) & 0xFF) << 16)
  86 #define RPCIF_SMOPR_OPD1(o)     (((o) & 0xFF) << 8)
  87 #define RPCIF_SMOPR_OPD0(o)     (((o) & 0xFF) << 0)
  88
  89 #define RPCIF_SMENR             0x0030  /* R/W */
  90 #define RPCIF_SMENR_CDB(o)      (((o) & 0x3) << 30)
  91 #define RPCIF_SMENR_OCDB(o)     (((o) & 0x3) << 28)
  92 #define RPCIF_SMENR_ADB(o)      (((o) & 0x3) << 24)
  93 #define RPCIF_SMENR_OPDB(o)     (((o) & 0x3) << 20)
  94 #define RPCIF_SMENR_SPIDB(o)    (((o) & 0x3) << 16)
  95 #define RPCIF_SMENR_DME         BIT(15)
  96 #define RPCIF_SMENR_CDE         BIT(14)
  97 #define RPCIF_SMENR_OCDE        BIT(12)
  98 #define RPCIF_SMENR_ADE(v)      (((v) & 0xF) << 8)
  99 #define RPCIF_SMENR_OPDE(v)     (((v) & 0xF) << 4)
 100 #define RPCIF_SMENR_SPIDE(v)    (((v) & 0xF) << 0)
 101
 102 #define RPCIF_SMRDR0            0x0038  /* R */
 103 #define RPCIF_SMRDR1            0x003C  /* R */
 104 #define RPCIF_SMWDR0            0x0040  /* W */
 105 #define RPCIF_SMWDR1            0x0044  /* W */
 106
 107 #define RPCIF_CMNSR             0x0048  /* R */
 108 #define RPCIF_CMNSR_SSLF        BIT(1)
 109 #define RPCIF_CMNSR_TEND        BIT(0)
 110
 111 #define RPCIF_DRDMCR            0x0058  /* R/W */
 112 #define RPCIF_DMDMCR_DMCYC(v)   ((((v) - 1) & 0x1F) << 0)
 113
 114 #define RPCIF_DRDRENR           0x005C  /* R/W */
 115 #define RPCIF_DRDRENR_HYPE(v)   (((v) & 0x7) << 12)
 116 #define RPCIF_DRDRENR_ADDRE     BIT(8)
 117 #define RPCIF_DRDRENR_OPDRE     BIT(4)
 118 #define RPCIF_DRDRENR_DRDRE     BIT(0)
 119
 120 #define RPCIF_SMDMCR            0x0060  /* R/W */
 121 #define RPCIF_SMDMCR_DMCYC(v)   ((((v) - 1) & 0x1F) << 0)
 122
 123 #define RPCIF_SMDRENR           0x0064  /* R/W */
 124 #define RPCIF_SMDRENR_HYPE(v)   (((v) & 0x7) << 12)
 125 #define RPCIF_SMDRENR_ADDRE     BIT(8)
 126 #define RPCIF_SMDRENR_OPDRE     BIT(4)
 127 #define RPCIF_SMDRENR_SPIDRE    BIT(0)
 128
 129 #define RPCIF_PHYADD            0x0070  /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
 130 #define RPCIF_PHYWR             0x0074  /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
 131
 132 #define RPCIF_PHYCNT            0x007C  /* R/W */
 133 #define RPCIF_PHYCNT_CAL        BIT(31)
 134 #define RPCIF_PHYCNT_OCTA(v)    (((v) & 0x3) << 22)
 135 #define RPCIF_PHYCNT_EXDS       BIT(21)
 136 #define RPCIF_PHYCNT_OCT        BIT(20)
 137 #define RPCIF_PHYCNT_DDRCAL     BIT(19)
 138 #define RPCIF_PHYCNT_HS         BIT(18)
 139 #define RPCIF_PHYCNT_CKSEL(v)   (((v) & 0x3) << 16) /* valid only for RZ/G2L */
 140 #define RPCIF_PHYCNT_STRTIM(v)  (((v) & 0x7) << 15 | ((v) & 0x8) << 24) /* valid for R-Car and RZ/G2{E,H,M,N} */
 141
 142 #define RPCIF_PHYCNT_WBUF2      BIT(4)
 143 #define RPCIF_PHYCNT_WBUF       BIT(2)
 144 #define RPCIF_PHYCNT_PHYMEM(v)  (((v) & 0x3) << 0)
 145 #define RPCIF_PHYCNT_PHYMEM_MASK GENMASK(1, 0)
 146
 147 #define RPCIF_PHYOFFSET1        0x0080  /* R/W */
 148 #define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
 149
 150 #define RPCIF_PHYOFFSET2        0x0084  /* R/W */
 151 #define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
 152
 153 #define RPCIF_PHYINT            0x0088  /* R/W */
 154 #define RPCIF_PHYINT_WPVAL      BIT(1)
 155
 156 static const struct regmap_range rpcif_volatile_ranges[] = {
 157         regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1),
 158         regmap_reg_range(RPCIF_SMWDR0, RPCIF_SMWDR1),
 159         regmap_reg_range(RPCIF_CMNSR, RPCIF_CMNSR),
 160 };
 161
 162 static const struct regmap_access_table rpcif_volatile_table = {
 163         .yes_ranges     = rpcif_volatile_ranges,
 164         .n_yes_ranges   = ARRAY_SIZE(rpcif_volatile_ranges),
 165 };
 166
 167 struct rpcif_info {
 168         enum rpcif_type type;
 169         u8 strtim;
 170 };
 171
 172 struct rpcif_priv {
 173         struct device *dev;
 174         void __iomem *base;
 175         void __iomem *dirmap;
 176         struct regmap *regmap;
 177         struct reset_control *rstc;
 178         struct platform_device *vdev;
 179         size_t size;
 180         const struct rpcif_info *info;
 181         enum rpcif_data_dir dir;
 182         u8 bus_size;
 183         u8 xfer_size;
 184         void *buffer;
 185         u32 xferlen;
 186         u32 smcr;
 187         u32 smadr;
 188         u32 command;            /* DRCMR or SMCMR */
 189         u32 option;             /* DROPR or SMOPR */
 190         u32 enable;             /* DRENR or SMENR */
 191         u32 dummy;              /* DRDMCR or SMDMCR */
 192         u32 ddr;                /* DRDRENR or SMDRENR */
 193 };
 194
 195 static const struct rpcif_info rpcif_info_r8a7796 = {
 196         .type = RPCIF_RCAR_GEN3,
 197         .strtim = 6,
 198 };
 199
 200 static const struct rpcif_info rpcif_info_gen3 = {
 201         .type = RPCIF_RCAR_GEN3,
 202         .strtim = 7,
 203 };
 204
 205 static const struct rpcif_info rpcif_info_rz_g2l = {
 206         .type = RPCIF_RZ_G2L,
 207         .strtim = 7,
 208 };
 209
 210 static const struct rpcif_info rpcif_info_gen4 = {
 211         .type = RPCIF_RCAR_GEN4,
 212         .strtim = 15,
 213 };
 214
 215 /*
 216  * Custom accessor functions to ensure SM[RW]DR[01] are always accessed with
 217  * proper width.  Requires rpcif_priv.xfer_size to be correctly set before!
 218  */
 219 static int rpcif_reg_read(void *context, unsigned int reg, unsigned int *val)
 220 {
 221         struct rpcif_priv *rpc = context;
 222
 223         switch (reg) {
 224         case RPCIF_SMRDR0:
 225         case RPCIF_SMWDR0:
 226                 switch (rpc->xfer_size) {
 227                 case 1:
 228                         *val = readb(rpc->base + reg);
 229                         return 0;
 230
 231                 case 2:
 232                         *val = readw(rpc->base + reg);
 233                         return 0;
 234
 235                 case 4:
 236                 case 8:
 237                         *val = readl(rpc->base + reg);
 238                         return 0;
 239
 240                 default:
 241                         return -EILSEQ;
 242                 }
 243
 244         case RPCIF_SMRDR1:
 245         case RPCIF_SMWDR1:
 246                 if (rpc->xfer_size != 8)
 247                         return -EILSEQ;
 248                 break;
 249         }
 250
 251         *val = readl(rpc->base + reg);
 252         return 0;
 253 }
 254
 255 static int rpcif_reg_write(void *context, unsigned int reg, unsigned int val)
 256 {
 257         struct rpcif_priv *rpc = context;
 258
 259         switch (reg) {
 260         case RPCIF_SMWDR0:
 261                 switch (rpc->xfer_size) {
 262                 case 1:
 263                         writeb(val, rpc->base + reg);
 264                         return 0;
 265
 266                 case 2:
 267                         writew(val, rpc->base + reg);
 268                         return 0;
 269
 270                 case 4:
 271                 case 8:
 272                         writel(val, rpc->base + reg);
 273                         return 0;
 274
 275                 default:
 276                         return -EILSEQ;
 277                 }
 278
 279         case RPCIF_SMWDR1:
 280                 if (rpc->xfer_size != 8)
 281                         return -EILSEQ;
 282                 break;
 283
 284         case RPCIF_SMRDR0:
 285         case RPCIF_SMRDR1:
 286                 return -EPERM;
 287         }
 288
 289         writel(val, rpc->base + reg);
 290         return 0;
 291 }
 292
 293 static const struct regmap_config rpcif_regmap_config = {
 294         .reg_bits       = 32,
 295         .val_bits       = 32,
 296         .reg_stride     = 4,
 297         .reg_read       = rpcif_reg_read,
 298         .reg_write      = rpcif_reg_write,
 299         .fast_io        = true,
 300         .max_register   = RPCIF_PHYINT,
 301         .volatile_table = &rpcif_volatile_table,
 302 };
 303
 304 int rpcif_sw_init(struct rpcif *rpcif, struct device *dev)
 305 {
 306         struct rpcif_priv *rpc = dev_get_drvdata(dev);
 307
 308         rpcif->dev = dev;
 309         rpcif->dirmap = rpc->dirmap;
 310         rpcif->size = rpc->size;
 311         return 0;
 312 }
 313 EXPORT_SYMBOL(rpcif_sw_init);
 314
 315 static void rpcif_rzg2l_timing_adjust_sdr(struct rpcif_priv *rpc)
 316 {
 317         regmap_write(rpc->regmap, RPCIF_PHYWR, 0xa5390000);
 318         regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000000);
 319         regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080);
 320         regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000022);
 321         regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080);
 322         regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000024);
 323         regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_CKSEL(3),
 324                            RPCIF_PHYCNT_CKSEL(3));
 325         regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00000030);
 326         regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000032);
 327 }
 328
 329 int rpcif_hw_init(struct device *dev, bool hyperflash)
 330 {
 331         struct rpcif_priv *rpc = dev_get_drvdata(dev);
 332         u32 dummy;
 333         int ret;
 334
 335         ret = pm_runtime_resume_and_get(dev);
 336         if (ret)
 337                 return ret;
 338
 339         if (rpc->info->type == RPCIF_RZ_G2L) {
 340                 ret = reset_control_reset(rpc->rstc);
 341                 if (ret)
 342                         return ret;
 343                 usleep_range(200, 300);
 344                 rpcif_rzg2l_timing_adjust_sdr(rpc);
 345         }
 346
 347         regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_PHYMEM_MASK,
 348                            RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0));
 349
 350         /* DMA Transfer is not supported */
 351         regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_HS, 0);
 352
 353         regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
 354                            /* create mask with all affected bits set */
 355                            RPCIF_PHYCNT_STRTIM(BIT(fls(rpc->info->strtim)) - 1),
 356                            RPCIF_PHYCNT_STRTIM(rpc->info->strtim));
 357
 358         regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET1, RPCIF_PHYOFFSET1_DDRTMG(3),
 359                            RPCIF_PHYOFFSET1_DDRTMG(3));
 360         regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET2, RPCIF_PHYOFFSET2_OCTTMG(7),
 361                            RPCIF_PHYOFFSET2_OCTTMG(4));
 362
 363         if (hyperflash)
 364                 regmap_update_bits(rpc->regmap, RPCIF_PHYINT,
 365                                    RPCIF_PHYINT_WPVAL, 0);
 366
 367         if (rpc->info->type == RPCIF_RZ_G2L)
 368                 regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
 369                                    RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_IOFV(3) |
 370                                    RPCIF_CMNCR_BSZ(3),
 371                                    RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(2) |
 372                                    RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
 373         else
 374                 regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
 375                                    RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_BSZ(3),
 376                                    RPCIF_CMNCR_MOIIO(3) |
 377                                    RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
 378
 379         /* Set RCF after BSZ update */
 380         regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
 381         /* Dummy read according to spec */
 382         regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
 383         regmap_write(rpc->regmap, RPCIF_SSLDR, RPCIF_SSLDR_SPNDL(7) |
 384                      RPCIF_SSLDR_SLNDL(7) | RPCIF_SSLDR_SCKDL(7));
 385
 386         pm_runtime_put(dev);
 387
 388         rpc->bus_size = hyperflash ? 2 : 1;
 389
 390         return 0;
 391 }
 392 EXPORT_SYMBOL(rpcif_hw_init);
 393
 394 static int wait_msg_xfer_end(struct rpcif_priv *rpc)
 395 {
 396         u32 sts;
 397
 398         return regmap_read_poll_timeout(rpc->regmap, RPCIF_CMNSR, sts,
 399                                         sts & RPCIF_CMNSR_TEND, 0,
 400                                         USEC_PER_SEC);
 401 }
 402
 403 static u8 rpcif_bits_set(struct rpcif_priv *rpc, u32 nbytes)
 404 {
 405         if (rpc->bus_size == 2)
 406                 nbytes /= 2;
 407         nbytes = clamp(nbytes, 1U, 4U);
 408         return GENMASK(3, 4 - nbytes);
 409 }
 410
 411 static u8 rpcif_bit_size(u8 buswidth)
 412 {
 413         return buswidth > 4 ? 2 : ilog2(buswidth);
 414 }
 415
 416 void rpcif_prepare(struct device *dev, const struct rpcif_op *op, u64 *offs,
 417                    size_t *len)
 418 {
 419         struct rpcif_priv *rpc = dev_get_drvdata(dev);
 420
 421         rpc->smcr = 0;
 422         rpc->smadr = 0;
 423         rpc->enable = 0;
 424         rpc->command = 0;
 425         rpc->option = 0;
 426         rpc->dummy = 0;
 427         rpc->ddr = 0;
 428         rpc->xferlen = 0;
 429
 430         if (op->cmd.buswidth) {
 431                 rpc->enable  = RPCIF_SMENR_CDE |
 432                         RPCIF_SMENR_CDB(rpcif_bit_size(op->cmd.buswidth));
 433                 rpc->command = RPCIF_SMCMR_CMD(op->cmd.opcode);
 434                 if (op->cmd.ddr)
 435                         rpc->ddr = RPCIF_SMDRENR_HYPE(0x5);
 436         }
 437         if (op->ocmd.buswidth) {
 438                 rpc->enable  |= RPCIF_SMENR_OCDE |
 439                         RPCIF_SMENR_OCDB(rpcif_bit_size(op->ocmd.buswidth));
 440                 rpc->command |= RPCIF_SMCMR_OCMD(op->ocmd.opcode);
 441         }
 442
 443         if (op->addr.buswidth) {
 444                 rpc->enable |=
 445                         RPCIF_SMENR_ADB(rpcif_bit_size(op->addr.buswidth));
 446                 if (op->addr.nbytes == 4)
 447                         rpc->enable |= RPCIF_SMENR_ADE(0xF);
 448                 else
 449                         rpc->enable |= RPCIF_SMENR_ADE(GENMASK(
 450                                                 2, 3 - op->addr.nbytes));
 451                 if (op->addr.ddr)
 452                         rpc->ddr |= RPCIF_SMDRENR_ADDRE;
 453
 454                 if (offs && len)
 455                         rpc->smadr = *offs;
 456                 else
 457                         rpc->smadr = op->addr.val;
 458         }
 459
 460         if (op->dummy.buswidth) {
 461                 rpc->enable |= RPCIF_SMENR_DME;
 462                 rpc->dummy = RPCIF_SMDMCR_DMCYC(op->dummy.ncycles);
 463         }
 464
 465         if (op->option.buswidth) {
 466                 rpc->enable |= RPCIF_SMENR_OPDE(
 467                         rpcif_bits_set(rpc, op->option.nbytes)) |
 468                         RPCIF_SMENR_OPDB(rpcif_bit_size(op->option.buswidth));
 469                 if (op->option.ddr)
 470                         rpc->ddr |= RPCIF_SMDRENR_OPDRE;
 471                 rpc->option = op->option.val;
 472         }
 473
 474         rpc->dir = op->data.dir;
 475         if (op->data.buswidth) {
 476                 u32 nbytes;
 477
 478                 rpc->buffer = op->data.buf.in;
 479                 switch (op->data.dir) {
 480                 case RPCIF_DATA_IN:
 481                         rpc->smcr = RPCIF_SMCR_SPIRE;
 482                         break;
 483                 case RPCIF_DATA_OUT:
 484                         rpc->smcr = RPCIF_SMCR_SPIWE;
 485                         break;
 486                 default:
 487                         break;
 488                 }
 489                 if (op->data.ddr)
 490                         rpc->ddr |= RPCIF_SMDRENR_SPIDRE;
 491
 492                 if (offs && len)
 493                         nbytes = *len;
 494                 else
 495                         nbytes = op->data.nbytes;
 496                 rpc->xferlen = nbytes;
 497
 498                 rpc->enable |= RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth));
 499         }
 500 }
 501 EXPORT_SYMBOL(rpcif_prepare);
 502
 503 int rpcif_manual_xfer(struct device *dev)
 504 {
 505         struct rpcif_priv *rpc = dev_get_drvdata(dev);
 506         u32 smenr, smcr, pos = 0, max = rpc->bus_size == 2 ? 8 : 4;
 507         int ret = 0;
 508
 509         ret = pm_runtime_resume_and_get(dev);
 510         if (ret < 0)
 511                 return ret;
 512
 513         regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
 514                            RPCIF_PHYCNT_CAL, RPCIF_PHYCNT_CAL);
 515         regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
 516                            RPCIF_CMNCR_MD, RPCIF_CMNCR_MD);
 517         regmap_write(rpc->regmap, RPCIF_SMCMR, rpc->command);
 518         regmap_write(rpc->regmap, RPCIF_SMOPR, rpc->option);
 519         regmap_write(rpc->regmap, RPCIF_SMDMCR, rpc->dummy);
 520         regmap_write(rpc->regmap, RPCIF_SMDRENR, rpc->ddr);
 521         regmap_write(rpc->regmap, RPCIF_SMADR, rpc->smadr);
 522         smenr = rpc->enable;
 523
 524         switch (rpc->dir) {
 525         case RPCIF_DATA_OUT:
 526                 while (pos < rpc->xferlen) {
 527                         u32 bytes_left = rpc->xferlen - pos;
 528                         u32 nbytes, data[2], *p = data;
 529
 530                         smcr = rpc->smcr | RPCIF_SMCR_SPIE;
 531
 532                         /* nbytes may only be 1, 2, 4, or 8 */
 533                         nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
 534                         if (bytes_left > nbytes)
 535                                 smcr |= RPCIF_SMCR_SSLKP;
 536
 537                         smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
 538                         regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
 539                         rpc->xfer_size = nbytes;
 540
 541                         memcpy(data, rpc->buffer + pos, nbytes);
 542                         if (nbytes == 8)
 543                                 regmap_write(rpc->regmap, RPCIF_SMWDR1, *p++);
 544                         regmap_write(rpc->regmap, RPCIF_SMWDR0, *p);
 545
 546                         regmap_write(rpc->regmap, RPCIF_SMCR, smcr);
 547                         ret = wait_msg_xfer_end(rpc);
 548                         if (ret)
 549                                 goto err_out;
 550
 551                         pos += nbytes;
 552                         smenr = rpc->enable &
 553                                 ~RPCIF_SMENR_CDE & ~RPCIF_SMENR_ADE(0xF);
 554                 }
 555                 break;
 556         case RPCIF_DATA_IN:
 557                 /*
 558                  * RPC-IF spoils the data for the commands without an address
 559                  * phase (like RDID) in the manual mode, so we'll have to work
 560                  * around this issue by using the external address space read
 561                  * mode instead.
 562                  */
 563                 if (!(smenr & RPCIF_SMENR_ADE(0xF)) && rpc->dirmap) {
 564                         u32 dummy;
 565
 566                         regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
 567                                            RPCIF_CMNCR_MD, 0);
 568                         regmap_write(rpc->regmap, RPCIF_DRCR,
 569                                      RPCIF_DRCR_RBURST(32) | RPCIF_DRCR_RBE);
 570                         regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
 571                         regmap_write(rpc->regmap, RPCIF_DREAR,
 572                                      RPCIF_DREAR_EAC(1));
 573                         regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
 574                         regmap_write(rpc->regmap, RPCIF_DRENR,
 575                                      smenr & ~RPCIF_SMENR_SPIDE(0xF));
 576                         regmap_write(rpc->regmap, RPCIF_DRDMCR,  rpc->dummy);
 577                         regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
 578                         memcpy_fromio(rpc->buffer, rpc->dirmap, rpc->xferlen);
 579                         regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
 580                         /* Dummy read according to spec */
 581                         regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
 582                         break;
 583                 }
 584                 while (pos < rpc->xferlen) {
 585                         u32 bytes_left = rpc->xferlen - pos;
 586                         u32 nbytes, data[2], *p = data;
 587
 588                         /* nbytes may only be 1, 2, 4, or 8 */
 589                         nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
 590
 591                         regmap_write(rpc->regmap, RPCIF_SMADR,
 592                                      rpc->smadr + pos);
 593                         smenr &= ~RPCIF_SMENR_SPIDE(0xF);
 594                         smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
 595                         regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
 596                         regmap_write(rpc->regmap, RPCIF_SMCR,
 597                                      rpc->smcr | RPCIF_SMCR_SPIE);
 598                         rpc->xfer_size = nbytes;
 599                         ret = wait_msg_xfer_end(rpc);
 600                         if (ret)
 601                                 goto err_out;
 602
 603                         if (nbytes == 8)
 604                                 regmap_read(rpc->regmap, RPCIF_SMRDR1, p++);
 605                         regmap_read(rpc->regmap, RPCIF_SMRDR0, p);
 606                         memcpy(rpc->buffer + pos, data, nbytes);
 607
 608                         pos += nbytes;
 609                 }
 610                 break;
 611         default:
 612                 regmap_write(rpc->regmap, RPCIF_SMENR, rpc->enable);
 613                 regmap_write(rpc->regmap, RPCIF_SMCR,
 614                              rpc->smcr | RPCIF_SMCR_SPIE);
 615                 ret = wait_msg_xfer_end(rpc);
 616                 if (ret)
 617                         goto err_out;
 618         }
 619
 620 exit:
 621         pm_runtime_put(dev);
 622         return ret;
 623
 624 err_out:
 625         if (reset_control_reset(rpc->rstc))
 626                 dev_err(dev, "Failed to reset HW\n");
 627         rpcif_hw_init(dev, rpc->bus_size == 2);
 628         goto exit;
 629 }
 630 EXPORT_SYMBOL(rpcif_manual_xfer);
 631
 632 static void memcpy_fromio_readw(void *to,
 633                                 const void __iomem *from,
 634                                 size_t count)
 635 {
 636         const int maxw = (IS_ENABLED(CONFIG_64BIT)) ? 8 : 4;
 637         u8 buf[2];
 638
 639         if (count && ((unsigned long)from & 1)) {
 640                 *(u16 *)buf = __raw_readw((void __iomem *)((unsigned long)from & ~1));
 641                 *(u8 *)to = buf[1];
 642                 from++;
 643                 to++;
 644                 count--;
 645         }
 646         while (count >= 2 && !IS_ALIGNED((unsigned long)from, maxw)) {
 647                 *(u16 *)to = __raw_readw(from);
 648                 from += 2;
 649                 to += 2;
 650                 count -= 2;
 651         }
 652         while (count >= maxw) {
 653 #ifdef CONFIG_64BIT
 654                 *(u64 *)to = __raw_readq(from);
 655 #else
 656                 *(u32 *)to = __raw_readl(from);
 657 #endif
 658                 from += maxw;
 659                 to += maxw;
 660                 count -= maxw;
 661         }
 662         while (count >= 2) {
 663                 *(u16 *)to = __raw_readw(from);
 664                 from += 2;
 665                 to += 2;
 666                 count -= 2;
 667         }
 668         if (count) {
 669                 *(u16 *)buf = __raw_readw(from);
 670                 *(u8 *)to = buf[0];
 671         }
 672 }
 673
 674 ssize_t rpcif_dirmap_read(struct device *dev, u64 offs, size_t len, void *buf)
 675 {
 676         struct rpcif_priv *rpc = dev_get_drvdata(dev);
 677         loff_t from = offs & (rpc->size - 1);
 678         size_t size = rpc->size - from;
 679         int ret;
 680
 681         if (len > size)
 682                 len = size;
 683
 684         ret = pm_runtime_resume_and_get(dev);
 685         if (ret < 0)
 686                 return ret;
 687
 688         regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MD, 0);
 689         regmap_write(rpc->regmap, RPCIF_DRCR, 0);
 690         regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
 691         regmap_write(rpc->regmap, RPCIF_DREAR,
 692                      RPCIF_DREAR_EAV(offs >> 25) | RPCIF_DREAR_EAC(1));
 693         regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
 694         regmap_write(rpc->regmap, RPCIF_DRENR,
 695                      rpc->enable & ~RPCIF_SMENR_SPIDE(0xF));
 696         regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy);
 697         regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
 698
 699         if (rpc->bus_size == 2)
 700                 memcpy_fromio_readw(buf, rpc->dirmap + from, len);
 701         else
 702                 memcpy_fromio(buf, rpc->dirmap + from, len);
 703
 704         pm_runtime_put(dev);
 705
 706         return len;
 707 }
 708 EXPORT_SYMBOL(rpcif_dirmap_read);
 709
 710 static int rpcif_probe(struct platform_device *pdev)
 711 {
 712         struct device *dev = &pdev->dev;
 713         struct platform_device *vdev;
 714         struct device_node *flash;
 715         struct rpcif_priv *rpc;
 716         struct resource *res;
 717         const char *name;
 718         int ret;
 719
 720         flash = of_get_next_child(dev->of_node, NULL);
 721         if (!flash) {
 722                 dev_warn(dev, "no flash node found\n");
 723                 return -ENODEV;
 724         }
 725
 726         if (of_device_is_compatible(flash, "jedec,spi-nor")) {
 727                 name = "rpc-if-spi";
 728         } else if (of_device_is_compatible(flash, "cfi-flash")) {
 729                 name = "rpc-if-hyperflash";
 730         } else  {
 731                 of_node_put(flash);
 732                 dev_warn(dev, "unknown flash type\n");
 733                 return -ENODEV;
 734         }
 735         of_node_put(flash);
 736
 737         rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
 738         if (!rpc)
 739                 return -ENOMEM;
 740
 741         rpc->base = devm_platform_ioremap_resource_byname(pdev, "regs");
 742         if (IS_ERR(rpc->base))
 743                 return PTR_ERR(rpc->base);
 744
 745         rpc->regmap = devm_regmap_init(dev, NULL, rpc, &rpcif_regmap_config);
 746         if (IS_ERR(rpc->regmap)) {
 747                 dev_err(dev, "failed to init regmap for rpcif, error %ld\n",
 748                         PTR_ERR(rpc->regmap));
 749                 return  PTR_ERR(rpc->regmap);
 750         }
 751
 752         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap");
 753         rpc->dirmap = devm_ioremap_resource(dev, res);
 754         if (IS_ERR(rpc->dirmap))
 755                 return PTR_ERR(rpc->dirmap);
 756
 757         rpc->size = resource_size(res);
 758         rpc->info = of_device_get_match_data(dev);
 759         rpc->rstc = devm_reset_control_get_exclusive(dev, NULL);
 760         if (IS_ERR(rpc->rstc))
 761                 return PTR_ERR(rpc->rstc);
 762
 763         vdev = platform_device_alloc(name, pdev->id);
 764         if (!vdev)
 765                 return -ENOMEM;
 766         vdev->dev.parent = dev;
 767
 768         rpc->dev = dev;
 769         rpc->vdev = vdev;
 770         platform_set_drvdata(pdev, rpc);
 771
 772         ret = platform_device_add(vdev);
 773         if (ret) {
 774                 platform_device_put(vdev);
 775                 return ret;
 776         }
 777
 778         return 0;
 779 }
 780
 781 static int rpcif_remove(struct platform_device *pdev)
 782 {
 783         struct rpcif_priv *rpc = platform_get_drvdata(pdev);
 784
 785         platform_device_unregister(rpc->vdev);
 786
 787         return 0;
 788 }
 789
 790 static const struct of_device_id rpcif_of_match[] = {
 791         { .compatible = "renesas,r8a7796-rpc-if", .data = &rpcif_info_r8a7796 },
 792         { .compatible = "renesas,rcar-gen3-rpc-if", .data = &rpcif_info_gen3 },
 793         { .compatible = "renesas,rcar-gen4-rpc-if", .data = &rpcif_info_gen4 },
 794         { .compatible = "renesas,rzg2l-rpc-if", .data = &rpcif_info_rz_g2l },
 795         {},
 796 };
 797 MODULE_DEVICE_TABLE(of, rpcif_of_match);
 798
 799 static struct platform_driver rpcif_driver = {
 800         .probe  = rpcif_probe,
 801         .remove = rpcif_remove,
 802         .driver = {
 803                 .name = "rpc-if",
 804                 .of_match_table = rpcif_of_match,
 805         },
 806 };
 807 module_platform_driver(rpcif_driver);
 808
 809 MODULE_DESCRIPTION("Renesas RPC-IF core driver");
 810 MODULE_LICENSE("GPL v2");