drivers/memory/renesas-rpc-if.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Renesas RPC-IF core driver
   4  *
   5  * Copyright (C) 2018-2019 Renesas Solutions Corp.
   6  * Copyright (C) 2019 Macronix International Co., Ltd.
   7  * Copyright (C) 2019-2020 Cogent Embedded, Inc.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/io.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/regmap.h>
  17 #include <linux/reset.h>
  18
  19 #include <memory/renesas-rpc-if.h>
  20
  21 #define RPCIF_CMNCR             0x0000  /* R/W */
  22 #define RPCIF_CMNCR_MD          BIT(31)
  23 #define RPCIF_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
  24 #define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
  25 #define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
  26 #define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
  27 #define RPCIF_CMNCR_MOIIO(val)  (RPCIF_CMNCR_MOIIO0(val) | RPCIF_CMNCR_MOIIO1(val) | \
  28                                  RPCIF_CMNCR_MOIIO2(val) | RPCIF_CMNCR_MOIIO3(val))
  29 #define RPCIF_CMNCR_IO3FV(val)  (((val) & 0x3) << 14) /* documented for RZ/G2L */
  30 #define RPCIF_CMNCR_IO2FV(val)  (((val) & 0x3) << 12) /* documented for RZ/G2L */
  31 #define RPCIF_CMNCR_IO0FV(val)  (((val) & 0x3) << 8)
  32 #define RPCIF_CMNCR_IOFV(val)   (RPCIF_CMNCR_IO0FV(val) | RPCIF_CMNCR_IO2FV(val) | \
  33                                  RPCIF_CMNCR_IO3FV(val))
  34 #define RPCIF_CMNCR_BSZ(val)    (((val) & 0x3) << 0)
  35
  36 #define RPCIF_SSLDR             0x0004  /* R/W */
  37 #define RPCIF_SSLDR_SPNDL(d)    (((d) & 0x7) << 16)
  38 #define RPCIF_SSLDR_SLNDL(d)    (((d) & 0x7) << 8)
  39 #define RPCIF_SSLDR_SCKDL(d)    (((d) & 0x7) << 0)
  40
  41 #define RPCIF_DRCR              0x000C  /* R/W */
  42 #define RPCIF_DRCR_SSLN         BIT(24)
  43 #define RPCIF_DRCR_RBURST(v)    ((((v) - 1) & 0x1F) << 16)
  44 #define RPCIF_DRCR_RCF          BIT(9)
  45 #define RPCIF_DRCR_RBE          BIT(8)
  46 #define RPCIF_DRCR_SSLE         BIT(0)
  47
  48 #define RPCIF_DRCMR             0x0010  /* R/W */
  49 #define RPCIF_DRCMR_CMD(c)      (((c) & 0xFF) << 16)
  50 #define RPCIF_DRCMR_OCMD(c)     (((c) & 0xFF) << 0)
  51
  52 #define RPCIF_DREAR             0x0014  /* R/W */
  53 #define RPCIF_DREAR_EAV(c)      (((c) & 0xF) << 16)
  54 #define RPCIF_DREAR_EAC(c)      (((c) & 0x7) << 0)
  55
  56 #define RPCIF_DROPR             0x0018  /* R/W */
  57
  58 #define RPCIF_DRENR             0x001C  /* R/W */
  59 #define RPCIF_DRENR_CDB(o)      (u32)((((o) & 0x3) << 30))
  60 #define RPCIF_DRENR_OCDB(o)     (((o) & 0x3) << 28)
  61 #define RPCIF_DRENR_ADB(o)      (((o) & 0x3) << 24)
  62 #define RPCIF_DRENR_OPDB(o)     (((o) & 0x3) << 20)
  63 #define RPCIF_DRENR_DRDB(o)     (((o) & 0x3) << 16)
  64 #define RPCIF_DRENR_DME         BIT(15)
  65 #define RPCIF_DRENR_CDE         BIT(14)
  66 #define RPCIF_DRENR_OCDE        BIT(12)
  67 #define RPCIF_DRENR_ADE(v)      (((v) & 0xF) << 8)
  68 #define RPCIF_DRENR_OPDE(v)     (((v) & 0xF) << 4)
  69
  70 #define RPCIF_SMCR              0x0020  /* R/W */
  71 #define RPCIF_SMCR_SSLKP        BIT(8)
  72 #define RPCIF_SMCR_SPIRE        BIT(2)
  73 #define RPCIF_SMCR_SPIWE        BIT(1)
  74 #define RPCIF_SMCR_SPIE         BIT(0)
  75
  76 #define RPCIF_SMCMR             0x0024  /* R/W */
  77 #define RPCIF_SMCMR_CMD(c)      (((c) & 0xFF) << 16)
  78 #define RPCIF_SMCMR_OCMD(c)     (((c) & 0xFF) << 0)
  79
  80 #define RPCIF_SMADR             0x0028  /* R/W */
  81
  82 #define RPCIF_SMOPR             0x002C  /* R/W */
  83 #define RPCIF_SMOPR_OPD3(o)     (((o) & 0xFF) << 24)
  84 #define RPCIF_SMOPR_OPD2(o)     (((o) & 0xFF) << 16)
  85 #define RPCIF_SMOPR_OPD1(o)     (((o) & 0xFF) << 8)
  86 #define RPCIF_SMOPR_OPD0(o)     (((o) & 0xFF) << 0)
  87
  88 #define RPCIF_SMENR             0x0030  /* R/W */
  89 #define RPCIF_SMENR_CDB(o)      (((o) & 0x3) << 30)
  90 #define RPCIF_SMENR_OCDB(o)     (((o) & 0x3) << 28)
  91 #define RPCIF_SMENR_ADB(o)      (((o) & 0x3) << 24)
  92 #define RPCIF_SMENR_OPDB(o)     (((o) & 0x3) << 20)
  93 #define RPCIF_SMENR_SPIDB(o)    (((o) & 0x3) << 16)
  94 #define RPCIF_SMENR_DME         BIT(15)
  95 #define RPCIF_SMENR_CDE         BIT(14)
  96 #define RPCIF_SMENR_OCDE        BIT(12)
  97 #define RPCIF_SMENR_ADE(v)      (((v) & 0xF) << 8)
  98 #define RPCIF_SMENR_OPDE(v)     (((v) & 0xF) << 4)
  99 #define RPCIF_SMENR_SPIDE(v)    (((v) & 0xF) << 0)
 100
 101 #define RPCIF_SMRDR0            0x0038  /* R */
 102 #define RPCIF_SMRDR1            0x003C  /* R */
 103 #define RPCIF_SMWDR0            0x0040  /* W */
 104 #define RPCIF_SMWDR1            0x0044  /* W */
 105
 106 #define RPCIF_CMNSR             0x0048  /* R */
 107 #define RPCIF_CMNSR_SSLF        BIT(1)
 108 #define RPCIF_CMNSR_TEND        BIT(0)
 109
 110 #define RPCIF_DRDMCR            0x0058  /* R/W */
 111 #define RPCIF_DMDMCR_DMCYC(v)   ((((v) - 1) & 0x1F) << 0)
 112
 113 #define RPCIF_DRDRENR           0x005C  /* R/W */
 114 #define RPCIF_DRDRENR_HYPE(v)   (((v) & 0x7) << 12)
 115 #define RPCIF_DRDRENR_ADDRE     BIT(8)
 116 #define RPCIF_DRDRENR_OPDRE     BIT(4)
 117 #define RPCIF_DRDRENR_DRDRE     BIT(0)
 118
 119 #define RPCIF_SMDMCR            0x0060  /* R/W */
 120 #define RPCIF_SMDMCR_DMCYC(v)   ((((v) - 1) & 0x1F) << 0)
 121
 122 #define RPCIF_SMDRENR           0x0064  /* R/W */
 123 #define RPCIF_SMDRENR_HYPE(v)   (((v) & 0x7) << 12)
 124 #define RPCIF_SMDRENR_ADDRE     BIT(8)
 125 #define RPCIF_SMDRENR_OPDRE     BIT(4)
 126 #define RPCIF_SMDRENR_SPIDRE    BIT(0)
 127
 128 #define RPCIF_PHYADD            0x0070  /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
 129 #define RPCIF_PHYWR             0x0074  /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
 130
 131 #define RPCIF_PHYCNT            0x007C  /* R/W */
 132 #define RPCIF_PHYCNT_CAL        BIT(31)
 133 #define RPCIF_PHYCNT_OCTA(v)    (((v) & 0x3) << 22)
 134 #define RPCIF_PHYCNT_EXDS       BIT(21)
 135 #define RPCIF_PHYCNT_OCT        BIT(20)
 136 #define RPCIF_PHYCNT_DDRCAL     BIT(19)
 137 #define RPCIF_PHYCNT_HS         BIT(18)
 138 #define RPCIF_PHYCNT_CKSEL(v)   (((v) & 0x3) << 16) /* valid only for RZ/G2L */
 139 #define RPCIF_PHYCNT_STRTIM(v)  (((v) & 0x7) << 15) /* valid for R-Car and RZ/G2{E,H,M,N} */
 140 #define RPCIF_PHYCNT_WBUF2      BIT(4)
 141 #define RPCIF_PHYCNT_WBUF       BIT(2)
 142 #define RPCIF_PHYCNT_PHYMEM(v)  (((v) & 0x3) << 0)
 143 #define RPCIF_PHYCNT_PHYMEM_MASK GENMASK(1, 0)
 144
 145 #define RPCIF_PHYOFFSET1        0x0080  /* R/W */
 146 #define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
 147
 148 #define RPCIF_PHYOFFSET2        0x0084  /* R/W */
 149 #define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
 150
 151 #define RPCIF_PHYINT            0x0088  /* R/W */
 152 #define RPCIF_PHYINT_WPVAL      BIT(1)
 153
 154 static const struct regmap_range rpcif_volatile_ranges[] = {
 155         regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1),
 156         regmap_reg_range(RPCIF_SMWDR0, RPCIF_SMWDR1),
 157         regmap_reg_range(RPCIF_CMNSR, RPCIF_CMNSR),
 158 };
 159
 160 static const struct regmap_access_table rpcif_volatile_table = {
 161         .yes_ranges     = rpcif_volatile_ranges,
 162         .n_yes_ranges   = ARRAY_SIZE(rpcif_volatile_ranges),
 163 };
 164
 165
 166 /*
 167  * Custom accessor functions to ensure SM[RW]DR[01] are always accessed with
 168  * proper width.  Requires rpcif.xfer_size to be correctly set before!
 169  */
 170 static int rpcif_reg_read(void *context, unsigned int reg, unsigned int *val)
 171 {
 172         struct rpcif *rpc = context;
 173
 174         switch (reg) {
 175         case RPCIF_SMRDR0:
 176         case RPCIF_SMWDR0:
 177                 switch (rpc->xfer_size) {
 178                 case 1:
 179                         *val = readb(rpc->base + reg);
 180                         return 0;
 181
 182                 case 2:
 183                         *val = readw(rpc->base + reg);
 184                         return 0;
 185
 186                 case 4:
 187                 case 8:
 188                         *val = readl(rpc->base + reg);
 189                         return 0;
 190
 191                 default:
 192                         return -EILSEQ;
 193                 }
 194
 195         case RPCIF_SMRDR1:
 196         case RPCIF_SMWDR1:
 197                 if (rpc->xfer_size != 8)
 198                         return -EILSEQ;
 199                 break;
 200         }
 201
 202         *val = readl(rpc->base + reg);
 203         return 0;
 204 }
 205
 206 static int rpcif_reg_write(void *context, unsigned int reg, unsigned int val)
 207 {
 208         struct rpcif *rpc = context;
 209
 210         switch (reg) {
 211         case RPCIF_SMWDR0:
 212                 switch (rpc->xfer_size) {
 213                 case 1:
 214                         writeb(val, rpc->base + reg);
 215                         return 0;
 216
 217                 case 2:
 218                         writew(val, rpc->base + reg);
 219                         return 0;
 220
 221                 case 4:
 222                 case 8:
 223                         writel(val, rpc->base + reg);
 224                         return 0;
 225
 226                 default:
 227                         return -EILSEQ;
 228                 }
 229
 230         case RPCIF_SMWDR1:
 231                 if (rpc->xfer_size != 8)
 232                         return -EILSEQ;
 233                 break;
 234
 235         case RPCIF_SMRDR0:
 236         case RPCIF_SMRDR1:
 237                 return -EPERM;
 238         }
 239
 240         writel(val, rpc->base + reg);
 241         return 0;
 242 }
 243
 244 static const struct regmap_config rpcif_regmap_config = {
 245         .reg_bits       = 32,
 246         .val_bits       = 32,
 247         .reg_stride     = 4,
 248         .reg_read       = rpcif_reg_read,
 249         .reg_write      = rpcif_reg_write,
 250         .fast_io        = true,
 251         .max_register   = RPCIF_PHYINT,
 252         .volatile_table = &rpcif_volatile_table,
 253 };
 254
 255 int rpcif_sw_init(struct rpcif *rpc, struct device *dev)
 256 {
 257         struct platform_device *pdev = to_platform_device(dev);
 258         struct resource *res;
 259
 260         rpc->dev = dev;
 261
 262         rpc->base = devm_platform_ioremap_resource_byname(pdev, "regs");
 263         if (IS_ERR(rpc->base))
 264                 return PTR_ERR(rpc->base);
 265
 266         rpc->regmap = devm_regmap_init(&pdev->dev, NULL, rpc, &rpcif_regmap_config);
 267         if (IS_ERR(rpc->regmap)) {
 268                 dev_err(&pdev->dev,
 269                         "failed to init regmap for rpcif, error %ld\n",
 270                         PTR_ERR(rpc->regmap));
 271                 return  PTR_ERR(rpc->regmap);
 272         }
 273
 274         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap");
 275         rpc->dirmap = devm_ioremap_resource(&pdev->dev, res);
 276         if (IS_ERR(rpc->dirmap))
 277                 return PTR_ERR(rpc->dirmap);
 278         rpc->size = resource_size(res);
 279
 280         rpc->type = (uintptr_t)of_device_get_match_data(dev);
 281         rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
 282
 283         return PTR_ERR_OR_ZERO(rpc->rstc);
 284 }
 285 EXPORT_SYMBOL(rpcif_sw_init);
 286
 287 static void rpcif_rzg2l_timing_adjust_sdr(struct rpcif *rpc)
 288 {
 289         regmap_write(rpc->regmap, RPCIF_PHYWR, 0xa5390000);
 290         regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000000);
 291         regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080);
 292         regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000022);
 293         regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080);
 294         regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000024);
 295         regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_CKSEL(3),
 296                            RPCIF_PHYCNT_CKSEL(3));
 297         regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00000030);
 298         regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000032);
 299 }
 300
 301 int rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
 302 {
 303         u32 dummy;
 304
 305         pm_runtime_get_sync(rpc->dev);
 306
 307         if (rpc->type == RPCIF_RZ_G2L) {
 308                 int ret;
 309
 310                 ret = reset_control_reset(rpc->rstc);
 311                 if (ret)
 312                         return ret;
 313                 usleep_range(200, 300);
 314                 rpcif_rzg2l_timing_adjust_sdr(rpc);
 315         }
 316
 317         regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_PHYMEM_MASK,
 318                            RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0));
 319
 320         /* DMA Transfer is not supported */
 321         regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_HS, 0);
 322
 323         if (rpc->type == RPCIF_RCAR_GEN3)
 324                 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
 325                                    RPCIF_PHYCNT_STRTIM(7), RPCIF_PHYCNT_STRTIM(7));
 326
 327         regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET1, RPCIF_PHYOFFSET1_DDRTMG(3),
 328                            RPCIF_PHYOFFSET1_DDRTMG(3));
 329         regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET2, RPCIF_PHYOFFSET2_OCTTMG(7),
 330                            RPCIF_PHYOFFSET2_OCTTMG(4));
 331
 332         if (hyperflash)
 333                 regmap_update_bits(rpc->regmap, RPCIF_PHYINT,
 334                                    RPCIF_PHYINT_WPVAL, 0);
 335
 336         if (rpc->type == RPCIF_RCAR_GEN3)
 337                 regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
 338                                    RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_BSZ(3),
 339                                    RPCIF_CMNCR_MOIIO(3) |
 340                                    RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
 341         else
 342                 regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
 343                                    RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_IOFV(3) |
 344                                    RPCIF_CMNCR_BSZ(3),
 345                                    RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(2) |
 346                                    RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
 347
 348         /* Set RCF after BSZ update */
 349         regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
 350         /* Dummy read according to spec */
 351         regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
 352         regmap_write(rpc->regmap, RPCIF_SSLDR, RPCIF_SSLDR_SPNDL(7) |
 353                      RPCIF_SSLDR_SLNDL(7) | RPCIF_SSLDR_SCKDL(7));
 354
 355         pm_runtime_put(rpc->dev);
 356
 357         rpc->bus_size = hyperflash ? 2 : 1;
 358
 359         return 0;
 360 }
 361 EXPORT_SYMBOL(rpcif_hw_init);
 362
 363 static int wait_msg_xfer_end(struct rpcif *rpc)
 364 {
 365         u32 sts;
 366
 367         return regmap_read_poll_timeout(rpc->regmap, RPCIF_CMNSR, sts,
 368                                         sts & RPCIF_CMNSR_TEND, 0,
 369                                         USEC_PER_SEC);
 370 }
 371
 372 static u8 rpcif_bits_set(struct rpcif *rpc, u32 nbytes)
 373 {
 374         if (rpc->bus_size == 2)
 375                 nbytes /= 2;
 376         nbytes = clamp(nbytes, 1U, 4U);
 377         return GENMASK(3, 4 - nbytes);
 378 }
 379
 380 static u8 rpcif_bit_size(u8 buswidth)
 381 {
 382         return buswidth > 4 ? 2 : ilog2(buswidth);
 383 }
 384
 385 void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs,
 386                    size_t *len)
 387 {
 388         rpc->smcr = 0;
 389         rpc->smadr = 0;
 390         rpc->enable = 0;
 391         rpc->command = 0;
 392         rpc->option = 0;
 393         rpc->dummy = 0;
 394         rpc->ddr = 0;
 395         rpc->xferlen = 0;
 396
 397         if (op->cmd.buswidth) {
 398                 rpc->enable  = RPCIF_SMENR_CDE |
 399                         RPCIF_SMENR_CDB(rpcif_bit_size(op->cmd.buswidth));
 400                 rpc->command = RPCIF_SMCMR_CMD(op->cmd.opcode);
 401                 if (op->cmd.ddr)
 402                         rpc->ddr = RPCIF_SMDRENR_HYPE(0x5);
 403         }
 404         if (op->ocmd.buswidth) {
 405                 rpc->enable  |= RPCIF_SMENR_OCDE |
 406                         RPCIF_SMENR_OCDB(rpcif_bit_size(op->ocmd.buswidth));
 407                 rpc->command |= RPCIF_SMCMR_OCMD(op->ocmd.opcode);
 408         }
 409
 410         if (op->addr.buswidth) {
 411                 rpc->enable |=
 412                         RPCIF_SMENR_ADB(rpcif_bit_size(op->addr.buswidth));
 413                 if (op->addr.nbytes == 4)
 414                         rpc->enable |= RPCIF_SMENR_ADE(0xF);
 415                 else
 416                         rpc->enable |= RPCIF_SMENR_ADE(GENMASK(
 417                                                 2, 3 - op->addr.nbytes));
 418                 if (op->addr.ddr)
 419                         rpc->ddr |= RPCIF_SMDRENR_ADDRE;
 420
 421                 if (offs && len)
 422                         rpc->smadr = *offs;
 423                 else
 424                         rpc->smadr = op->addr.val;
 425         }
 426
 427         if (op->dummy.buswidth) {
 428                 rpc->enable |= RPCIF_SMENR_DME;
 429                 rpc->dummy = RPCIF_SMDMCR_DMCYC(op->dummy.ncycles /
 430                                                 op->dummy.buswidth);
 431         }
 432
 433         if (op->option.buswidth) {
 434                 rpc->enable |= RPCIF_SMENR_OPDE(
 435                         rpcif_bits_set(rpc, op->option.nbytes)) |
 436                         RPCIF_SMENR_OPDB(rpcif_bit_size(op->option.buswidth));
 437                 if (op->option.ddr)
 438                         rpc->ddr |= RPCIF_SMDRENR_OPDRE;
 439                 rpc->option = op->option.val;
 440         }
 441
 442         rpc->dir = op->data.dir;
 443         if (op->data.buswidth) {
 444                 u32 nbytes;
 445
 446                 rpc->buffer = op->data.buf.in;
 447                 switch (op->data.dir) {
 448                 case RPCIF_DATA_IN:
 449                         rpc->smcr = RPCIF_SMCR_SPIRE;
 450                         break;
 451                 case RPCIF_DATA_OUT:
 452                         rpc->smcr = RPCIF_SMCR_SPIWE;
 453                         break;
 454                 default:
 455                         break;
 456                 }
 457                 if (op->data.ddr)
 458                         rpc->ddr |= RPCIF_SMDRENR_SPIDRE;
 459
 460                 if (offs && len)
 461                         nbytes = *len;
 462                 else
 463                         nbytes = op->data.nbytes;
 464                 rpc->xferlen = nbytes;
 465
 466                 rpc->enable |= RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth));
 467         }
 468 }
 469 EXPORT_SYMBOL(rpcif_prepare);
 470
 471 int rpcif_manual_xfer(struct rpcif *rpc)
 472 {
 473         u32 smenr, smcr, pos = 0, max = rpc->bus_size == 2 ? 8 : 4;
 474         int ret = 0;
 475
 476         pm_runtime_get_sync(rpc->dev);
 477
 478         regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
 479                            RPCIF_PHYCNT_CAL, RPCIF_PHYCNT_CAL);
 480         regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
 481                            RPCIF_CMNCR_MD, RPCIF_CMNCR_MD);
 482         regmap_write(rpc->regmap, RPCIF_SMCMR, rpc->command);
 483         regmap_write(rpc->regmap, RPCIF_SMOPR, rpc->option);
 484         regmap_write(rpc->regmap, RPCIF_SMDMCR, rpc->dummy);
 485         regmap_write(rpc->regmap, RPCIF_SMDRENR, rpc->ddr);
 486         regmap_write(rpc->regmap, RPCIF_SMADR, rpc->smadr);
 487         smenr = rpc->enable;
 488
 489         switch (rpc->dir) {
 490         case RPCIF_DATA_OUT:
 491                 while (pos < rpc->xferlen) {
 492                         u32 bytes_left = rpc->xferlen - pos;
 493                         u32 nbytes, data[2], *p = data;
 494
 495                         smcr = rpc->smcr | RPCIF_SMCR_SPIE;
 496
 497                         /* nbytes may only be 1, 2, 4, or 8 */
 498                         nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
 499                         if (bytes_left > nbytes)
 500                                 smcr |= RPCIF_SMCR_SSLKP;
 501
 502                         smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
 503                         regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
 504                         rpc->xfer_size = nbytes;
 505
 506                         memcpy(data, rpc->buffer + pos, nbytes);
 507                         if (nbytes == 8)
 508                                 regmap_write(rpc->regmap, RPCIF_SMWDR1, *p++);
 509                         regmap_write(rpc->regmap, RPCIF_SMWDR0, *p);
 510
 511                         regmap_write(rpc->regmap, RPCIF_SMCR, smcr);
 512                         ret = wait_msg_xfer_end(rpc);
 513                         if (ret)
 514                                 goto err_out;
 515
 516                         pos += nbytes;
 517                         smenr = rpc->enable &
 518                                 ~RPCIF_SMENR_CDE & ~RPCIF_SMENR_ADE(0xF);
 519                 }
 520                 break;
 521         case RPCIF_DATA_IN:
 522                 /*
 523                  * RPC-IF spoils the data for the commands without an address
 524                  * phase (like RDID) in the manual mode, so we'll have to work
 525                  * around this issue by using the external address space read
 526                  * mode instead.
 527                  */
 528                 if (!(smenr & RPCIF_SMENR_ADE(0xF)) && rpc->dirmap) {
 529                         u32 dummy;
 530
 531                         regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
 532                                            RPCIF_CMNCR_MD, 0);
 533                         regmap_write(rpc->regmap, RPCIF_DRCR,
 534                                      RPCIF_DRCR_RBURST(32) | RPCIF_DRCR_RBE);
 535                         regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
 536                         regmap_write(rpc->regmap, RPCIF_DREAR,
 537                                      RPCIF_DREAR_EAC(1));
 538                         regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
 539                         regmap_write(rpc->regmap, RPCIF_DRENR,
 540                                      smenr & ~RPCIF_SMENR_SPIDE(0xF));
 541                         regmap_write(rpc->regmap, RPCIF_DRDMCR,  rpc->dummy);
 542                         regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
 543                         memcpy_fromio(rpc->buffer, rpc->dirmap, rpc->xferlen);
 544                         regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
 545                         /* Dummy read according to spec */
 546                         regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
 547                         break;
 548                 }
 549                 while (pos < rpc->xferlen) {
 550                         u32 bytes_left = rpc->xferlen - pos;
 551                         u32 nbytes, data[2], *p = data;
 552
 553                         /* nbytes may only be 1, 2, 4, or 8 */
 554                         nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
 555
 556                         regmap_write(rpc->regmap, RPCIF_SMADR,
 557                                      rpc->smadr + pos);
 558                         smenr &= ~RPCIF_SMENR_SPIDE(0xF);
 559                         smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
 560                         regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
 561                         regmap_write(rpc->regmap, RPCIF_SMCR,
 562                                      rpc->smcr | RPCIF_SMCR_SPIE);
 563                         rpc->xfer_size = nbytes;
 564                         ret = wait_msg_xfer_end(rpc);
 565                         if (ret)
 566                                 goto err_out;
 567
 568                         if (nbytes == 8)
 569                                 regmap_read(rpc->regmap, RPCIF_SMRDR1, p++);
 570                         regmap_read(rpc->regmap, RPCIF_SMRDR0, p);
 571                         memcpy(rpc->buffer + pos, data, nbytes);
 572
 573                         pos += nbytes;
 574                 }
 575                 break;
 576         default:
 577                 regmap_write(rpc->regmap, RPCIF_SMENR, rpc->enable);
 578                 regmap_write(rpc->regmap, RPCIF_SMCR,
 579                              rpc->smcr | RPCIF_SMCR_SPIE);
 580                 ret = wait_msg_xfer_end(rpc);
 581                 if (ret)
 582                         goto err_out;
 583         }
 584
 585 exit:
 586         pm_runtime_put(rpc->dev);
 587         return ret;
 588
 589 err_out:
 590         if (reset_control_reset(rpc->rstc))
 591                 dev_err(rpc->dev, "Failed to reset HW\n");
 592         rpcif_hw_init(rpc, rpc->bus_size == 2);
 593         goto exit;
 594 }
 595 EXPORT_SYMBOL(rpcif_manual_xfer);
 596
 597 static void memcpy_fromio_readw(void *to,
 598                                 const void __iomem *from,
 599                                 size_t count)
 600 {
 601         const int maxw = (IS_ENABLED(CONFIG_64BIT)) ? 8 : 4;
 602         u8 buf[2];
 603
 604         if (count && ((unsigned long)from & 1)) {
 605                 *(u16 *)buf = __raw_readw((void __iomem *)((unsigned long)from & ~1));
 606                 *(u8 *)to = buf[1];
 607                 from++;
 608                 to++;
 609                 count--;
 610         }
 611         while (count >= 2 && !IS_ALIGNED((unsigned long)from, maxw)) {
 612                 *(u16 *)to = __raw_readw(from);
 613                 from += 2;
 614                 to += 2;
 615                 count -= 2;
 616         }
 617         while (count >= maxw) {
 618 #ifdef CONFIG_64BIT
 619                 *(u64 *)to = __raw_readq(from);
 620 #else
 621                 *(u32 *)to = __raw_readl(from);
 622 #endif
 623                 from += maxw;
 624                 to += maxw;
 625                 count -= maxw;
 626         }
 627         while (count >= 2) {
 628                 *(u16 *)to = __raw_readw(from);
 629                 from += 2;
 630                 to += 2;
 631                 count -= 2;
 632         }
 633         if (count) {
 634                 *(u16 *)buf = __raw_readw(from);
 635                 *(u8 *)to = buf[0];
 636         }
 637 }
 638
 639 ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf)
 640 {
 641         loff_t from = offs & (rpc->size - 1);
 642         size_t size = rpc->size - from;
 643
 644         if (len > size)
 645                 len = size;
 646
 647         pm_runtime_get_sync(rpc->dev);
 648
 649         regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MD, 0);
 650         regmap_write(rpc->regmap, RPCIF_DRCR, 0);
 651         regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
 652         regmap_write(rpc->regmap, RPCIF_DREAR,
 653                      RPCIF_DREAR_EAV(offs >> 25) | RPCIF_DREAR_EAC(1));
 654         regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
 655         regmap_write(rpc->regmap, RPCIF_DRENR,
 656                      rpc->enable & ~RPCIF_SMENR_SPIDE(0xF));
 657         regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy);
 658         regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
 659
 660         if (rpc->bus_size == 2)
 661                 memcpy_fromio_readw(buf, rpc->dirmap + from, len);
 662         else
 663                 memcpy_fromio(buf, rpc->dirmap + from, len);
 664
 665         pm_runtime_put(rpc->dev);
 666
 667         return len;
 668 }
 669 EXPORT_SYMBOL(rpcif_dirmap_read);
 670
 671 static int rpcif_probe(struct platform_device *pdev)
 672 {
 673         struct platform_device *vdev;
 674         struct device_node *flash;
 675         const char *name;
 676         int ret;
 677
 678         flash = of_get_next_child(pdev->dev.of_node, NULL);
 679         if (!flash) {
 680                 dev_warn(&pdev->dev, "no flash node found\n");
 681                 return -ENODEV;
 682         }
 683
 684         if (of_device_is_compatible(flash, "jedec,spi-nor")) {
 685                 name = "rpc-if-spi";
 686         } else if (of_device_is_compatible(flash, "cfi-flash")) {
 687                 name = "rpc-if-hyperflash";
 688         } else  {
 689                 of_node_put(flash);
 690                 dev_warn(&pdev->dev, "unknown flash type\n");
 691                 return -ENODEV;
 692         }
 693         of_node_put(flash);
 694
 695         vdev = platform_device_alloc(name, pdev->id);
 696         if (!vdev)
 697                 return -ENOMEM;
 698         vdev->dev.parent = &pdev->dev;
 699         platform_set_drvdata(pdev, vdev);
 700
 701         ret = platform_device_add(vdev);
 702         if (ret) {
 703                 platform_device_put(vdev);
 704                 return ret;
 705         }
 706
 707         return 0;
 708 }
 709
 710 static int rpcif_remove(struct platform_device *pdev)
 711 {
 712         struct platform_device *vdev = platform_get_drvdata(pdev);
 713
 714         platform_device_unregister(vdev);
 715
 716         return 0;
 717 }
 718
 719 static const struct of_device_id rpcif_of_match[] = {
 720         { .compatible = "renesas,rcar-gen3-rpc-if", .data = (void *)RPCIF_RCAR_GEN3 },
 721         { .compatible = "renesas,rzg2l-rpc-if", .data = (void *)RPCIF_RZ_G2L },
 722         {},
 723 };
 724 MODULE_DEVICE_TABLE(of, rpcif_of_match);
 725
 726 static struct platform_driver rpcif_driver = {
 727         .probe  = rpcif_probe,
 728         .remove = rpcif_remove,
 729         .driver = {
 730                 .name = "rpc-if",
 731                 .of_match_table = rpcif_of_match,
 732         },
 733 };
 734 module_platform_driver(rpcif_driver);
 735
 736 MODULE_DESCRIPTION("Renesas RPC-IF core driver");
 737 MODULE_LICENSE("GPL v2");