drivers/memory/emif.c

   1 /*
   2  * EMIF driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments, Inc.
   5  *
   6  * Aneesh V <aneesh@ti.com>
   7  * Santosh Shilimkar <santosh.shilimkar@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13 #include <linux/kernel.h>
  14 #include <linux/reboot.h>
  15 #include <linux/platform_data/emif_plat.h>
  16 #include <linux/io.h>
  17 #include <linux/device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/slab.h>
  21 #include <linux/of.h>
  22 #include <linux/debugfs.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/module.h>
  25 #include <linux/list.h>
  26 #include <linux/spinlock.h>
  27 #include <memory/jedec_ddr.h>
  28 #include "emif.h"
  29 #include "of_memory.h"
  30
  31 /**
  32  * struct emif_data - Per device static data for driver's use
  33  * @duplicate:                  Whether the DDR devices attached to this EMIF
  34  *                              instance are exactly same as that on EMIF1. In
  35  *                              this case we can save some memory and processing
  36  * @temperature_level:          Maximum temperature of LPDDR2 devices attached
  37  *                              to this EMIF - read from MR4 register. If there
  38  *                              are two devices attached to this EMIF, this
  39  *                              value is the maximum of the two temperature
  40  *                              levels.
  41  * @node:                       node in the device list
  42  * @base:                       base address of memory-mapped IO registers.
  43  * @dev:                        device pointer.
  44  * @addressing                  table with addressing information from the spec
  45  * @regs_cache:                 An array of 'struct emif_regs' that stores
  46  *                              calculated register values for different
  47  *                              frequencies, to avoid re-calculating them on
  48  *                              each DVFS transition.
  49  * @curr_regs:                  The set of register values used in the last
  50  *                              frequency change (i.e. corresponding to the
  51  *                              frequency in effect at the moment)
  52  * @plat_data:                  Pointer to saved platform data.
  53  * @debugfs_root:               dentry to the root folder for EMIF in debugfs
  54  * @np_ddr:                     Pointer to ddr device tree node
  55  */
  56 struct emif_data {
  57         u8                              duplicate;
  58         u8                              temperature_level;
  59         u8                              lpmode;
  60         struct list_head                node;
  61         unsigned long                   irq_state;
  62         void __iomem                    *base;
  63         struct device                   *dev;
  64         const struct lpddr2_addressing  *addressing;
  65         struct emif_regs                *regs_cache[EMIF_MAX_NUM_FREQUENCIES];
  66         struct emif_regs                *curr_regs;
  67         struct emif_platform_data       *plat_data;
  68         struct dentry                   *debugfs_root;
  69         struct device_node              *np_ddr;
  70 };
  71
  72 static struct emif_data *emif1;
  73 static spinlock_t       emif_lock;
  74 static unsigned long    irq_state;
  75 static u32              t_ck; /* DDR clock period in ps */
  76 static LIST_HEAD(device_list);
  77
  78 static void do_emif_regdump_show(struct seq_file *s, struct emif_data *emif,
  79         struct emif_regs *regs)
  80 {
  81         u32 type = emif->plat_data->device_info->type;
  82         u32 ip_rev = emif->plat_data->ip_rev;
  83
  84         seq_printf(s, "EMIF register cache dump for %dMHz\n",
  85                 regs->freq/1000000);
  86
  87         seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw);
  88         seq_printf(s, "sdram_tim1_shdw\t: 0x%08x\n", regs->sdram_tim1_shdw);
  89         seq_printf(s, "sdram_tim2_shdw\t: 0x%08x\n", regs->sdram_tim2_shdw);
  90         seq_printf(s, "sdram_tim3_shdw\t: 0x%08x\n", regs->sdram_tim3_shdw);
  91
  92         if (ip_rev == EMIF_4D) {
  93                 seq_printf(s, "read_idle_ctrl_shdw_normal\t: 0x%08x\n",
  94                         regs->read_idle_ctrl_shdw_normal);
  95                 seq_printf(s, "read_idle_ctrl_shdw_volt_ramp\t: 0x%08x\n",
  96                         regs->read_idle_ctrl_shdw_volt_ramp);
  97         } else if (ip_rev == EMIF_4D5) {
  98                 seq_printf(s, "dll_calib_ctrl_shdw_normal\t: 0x%08x\n",
  99                         regs->dll_calib_ctrl_shdw_normal);
 100                 seq_printf(s, "dll_calib_ctrl_shdw_volt_ramp\t: 0x%08x\n",
 101                         regs->dll_calib_ctrl_shdw_volt_ramp);
 102         }
 103
 104         if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
 105                 seq_printf(s, "ref_ctrl_shdw_derated\t: 0x%08x\n",
 106                         regs->ref_ctrl_shdw_derated);
 107                 seq_printf(s, "sdram_tim1_shdw_derated\t: 0x%08x\n",
 108                         regs->sdram_tim1_shdw_derated);
 109                 seq_printf(s, "sdram_tim3_shdw_derated\t: 0x%08x\n",
 110                         regs->sdram_tim3_shdw_derated);
 111         }
 112 }
 113
 114 static int emif_regdump_show(struct seq_file *s, void *unused)
 115 {
 116         struct emif_data        *emif   = s->private;
 117         struct emif_regs        **regs_cache;
 118         int                     i;
 119
 120         if (emif->duplicate)
 121                 regs_cache = emif1->regs_cache;
 122         else
 123                 regs_cache = emif->regs_cache;
 124
 125         for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
 126                 do_emif_regdump_show(s, emif, regs_cache[i]);
 127                 seq_printf(s, "\n");
 128         }
 129
 130         return 0;
 131 }
 132
 133 static int emif_regdump_open(struct inode *inode, struct file *file)
 134 {
 135         return single_open(file, emif_regdump_show, inode->i_private);
 136 }
 137
 138 static const struct file_operations emif_regdump_fops = {
 139         .open                   = emif_regdump_open,
 140         .read                   = seq_read,
 141         .release                = single_release,
 142 };
 143
 144 static int emif_mr4_show(struct seq_file *s, void *unused)
 145 {
 146         struct emif_data *emif = s->private;
 147
 148         seq_printf(s, "MR4=%d\n", emif->temperature_level);
 149         return 0;
 150 }
 151
 152 static int emif_mr4_open(struct inode *inode, struct file *file)
 153 {
 154         return single_open(file, emif_mr4_show, inode->i_private);
 155 }
 156
 157 static const struct file_operations emif_mr4_fops = {
 158         .open                   = emif_mr4_open,
 159         .read                   = seq_read,
 160         .release                = single_release,
 161 };
 162
 163 static int __init_or_module emif_debugfs_init(struct emif_data *emif)
 164 {
 165         struct dentry   *dentry;
 166         int             ret;
 167
 168         dentry = debugfs_create_dir(dev_name(emif->dev), NULL);
 169         if (IS_ERR(dentry)) {
 170                 ret = PTR_ERR(dentry);
 171                 goto err0;
 172         }
 173         emif->debugfs_root = dentry;
 174
 175         dentry = debugfs_create_file("regcache_dump", S_IRUGO,
 176                         emif->debugfs_root, emif, &emif_regdump_fops);
 177         if (IS_ERR(dentry)) {
 178                 ret = PTR_ERR(dentry);
 179                 goto err1;
 180         }
 181
 182         dentry = debugfs_create_file("mr4", S_IRUGO,
 183                         emif->debugfs_root, emif, &emif_mr4_fops);
 184         if (IS_ERR(dentry)) {
 185                 ret = PTR_ERR(dentry);
 186                 goto err1;
 187         }
 188
 189         return 0;
 190 err1:
 191         debugfs_remove_recursive(emif->debugfs_root);
 192 err0:
 193         return ret;
 194 }
 195
 196 static void __exit emif_debugfs_exit(struct emif_data *emif)
 197 {
 198         debugfs_remove_recursive(emif->debugfs_root);
 199         emif->debugfs_root = NULL;
 200 }
 201
 202 /*
 203  * Calculate the period of DDR clock from frequency value
 204  */
 205 static void set_ddr_clk_period(u32 freq)
 206 {
 207         /* Divide 10^12 by frequency to get period in ps */
 208         t_ck = (u32)DIV_ROUND_UP_ULL(1000000000000ull, freq);
 209 }
 210
 211 /*
 212  * Get bus width used by EMIF. Note that this may be different from the
 213  * bus width of the DDR devices used. For instance two 16-bit DDR devices
 214  * may be connected to a given CS of EMIF. In this case bus width as far
 215  * as EMIF is concerned is 32, where as the DDR bus width is 16 bits.
 216  */
 217 static u32 get_emif_bus_width(struct emif_data *emif)
 218 {
 219         u32             width;
 220         void __iomem    *base = emif->base;
 221
 222         width = (readl(base + EMIF_SDRAM_CONFIG) & NARROW_MODE_MASK)
 223                         >> NARROW_MODE_SHIFT;
 224         width = width == 0 ? 32 : 16;
 225
 226         return width;
 227 }
 228
 229 /*
 230  * Get the CL from SDRAM_CONFIG register
 231  */
 232 static u32 get_cl(struct emif_data *emif)
 233 {
 234         u32             cl;
 235         void __iomem    *base = emif->base;
 236
 237         cl = (readl(base + EMIF_SDRAM_CONFIG) & CL_MASK) >> CL_SHIFT;
 238
 239         return cl;
 240 }
 241
 242 static void set_lpmode(struct emif_data *emif, u8 lpmode)
 243 {
 244         u32 temp;
 245         void __iomem *base = emif->base;
 246
 247         temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL);
 248         temp &= ~LP_MODE_MASK;
 249         temp |= (lpmode << LP_MODE_SHIFT);
 250         writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL);
 251 }
 252
 253 static void do_freq_update(void)
 254 {
 255         struct emif_data *emif;
 256
 257         /*
 258          * Workaround for errata i728: Disable LPMODE during FREQ_UPDATE
 259          *
 260          * i728 DESCRIPTION:
 261          * The EMIF automatically puts the SDRAM into self-refresh mode
 262          * after the EMIF has not performed accesses during
 263          * EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM number of DDR clock cycles
 264          * and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set
 265          * to 0x2. If during a small window the following three events
 266          * occur:
 267          * - The SR_TIMING counter expires
 268          * - And frequency change is requested
 269          * - And OCP access is requested
 270          * Then it causes instable clock on the DDR interface.
 271          *
 272          * WORKAROUND
 273          * To avoid the occurrence of the three events, the workaround
 274          * is to disable the self-refresh when requesting a frequency
 275          * change. Before requesting a frequency change the software must
 276          * program EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x0. When the
 277          * frequency change has been done, the software can reprogram
 278          * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2
 279          */
 280         list_for_each_entry(emif, &device_list, node) {
 281                 if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
 282                         set_lpmode(emif, EMIF_LP_MODE_DISABLE);
 283         }
 284
 285         /*
 286          * TODO: Do FREQ_UPDATE here when an API
 287          * is available for this as part of the new
 288          * clock framework
 289          */
 290
 291         list_for_each_entry(emif, &device_list, node) {
 292                 if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
 293                         set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
 294         }
 295 }
 296
 297 /* Find addressing table entry based on the device's type and density */
 298 static const struct lpddr2_addressing *get_addressing_table(
 299         const struct ddr_device_info *device_info)
 300 {
 301         u32             index, type, density;
 302
 303         type = device_info->type;
 304         density = device_info->density;
 305
 306         switch (type) {
 307         case DDR_TYPE_LPDDR2_S4:
 308                 index = density - 1;
 309                 break;
 310         case DDR_TYPE_LPDDR2_S2:
 311                 switch (density) {
 312                 case DDR_DENSITY_1Gb:
 313                 case DDR_DENSITY_2Gb:
 314                         index = density + 3;
 315                         break;
 316                 default:
 317                         index = density - 1;
 318                 }
 319                 break;
 320         default:
 321                 return NULL;
 322         }
 323
 324         return &lpddr2_jedec_addressing_table[index];
 325 }
 326
 327 /*
 328  * Find the the right timing table from the array of timing
 329  * tables of the device using DDR clock frequency
 330  */
 331 static const struct lpddr2_timings *get_timings_table(struct emif_data *emif,
 332                 u32 freq)
 333 {
 334         u32                             i, min, max, freq_nearest;
 335         const struct lpddr2_timings     *timings = NULL;
 336         const struct lpddr2_timings     *timings_arr = emif->plat_data->timings;
 337         struct                          device *dev = emif->dev;
 338
 339         /* Start with a very high frequency - 1GHz */
 340         freq_nearest = 1000000000;
 341
 342         /*
 343          * Find the timings table such that:
 344          *  1. the frequency range covers the required frequency(safe) AND
 345          *  2. the max_freq is closest to the required frequency(optimal)
 346          */
 347         for (i = 0; i < emif->plat_data->timings_arr_size; i++) {
 348                 max = timings_arr[i].max_freq;
 349                 min = timings_arr[i].min_freq;
 350                 if ((freq >= min) && (freq <= max) && (max < freq_nearest)) {
 351                         freq_nearest = max;
 352                         timings = &timings_arr[i];
 353                 }
 354         }
 355
 356         if (!timings)
 357                 dev_err(dev, "%s: couldn't find timings for - %dHz\n",
 358                         __func__, freq);
 359
 360         dev_dbg(dev, "%s: timings table: freq %d, speed bin freq %d\n",
 361                 __func__, freq, freq_nearest);
 362
 363         return timings;
 364 }
 365
 366 static u32 get_sdram_ref_ctrl_shdw(u32 freq,
 367                 const struct lpddr2_addressing *addressing)
 368 {
 369         u32 ref_ctrl_shdw = 0, val = 0, freq_khz, t_refi;
 370
 371         /* Scale down frequency and t_refi to avoid overflow */
 372         freq_khz = freq / 1000;
 373         t_refi = addressing->tREFI_ns / 100;
 374
 375         /*
 376          * refresh rate to be set is 'tREFI(in us) * freq in MHz
 377          * division by 10000 to account for change in units
 378          */
 379         val = t_refi * freq_khz / 10000;
 380         ref_ctrl_shdw |= val << REFRESH_RATE_SHIFT;
 381
 382         return ref_ctrl_shdw;
 383 }
 384
 385 static u32 get_sdram_tim_1_shdw(const struct lpddr2_timings *timings,
 386                 const struct lpddr2_min_tck *min_tck,
 387                 const struct lpddr2_addressing *addressing)
 388 {
 389         u32 tim1 = 0, val = 0;
 390
 391         val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
 392         tim1 |= val << T_WTR_SHIFT;
 393
 394         if (addressing->num_banks == B8)
 395                 val = DIV_ROUND_UP(timings->tFAW, t_ck*4);
 396         else
 397                 val = max(min_tck->tRRD, DIV_ROUND_UP(timings->tRRD, t_ck));
 398         tim1 |= (val - 1) << T_RRD_SHIFT;
 399
 400         val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab, t_ck) - 1;
 401         tim1 |= val << T_RC_SHIFT;
 402
 403         val = max(min_tck->tRASmin, DIV_ROUND_UP(timings->tRAS_min, t_ck));
 404         tim1 |= (val - 1) << T_RAS_SHIFT;
 405
 406         val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
 407         tim1 |= val << T_WR_SHIFT;
 408
 409         val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD, t_ck)) - 1;
 410         tim1 |= val << T_RCD_SHIFT;
 411
 412         val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab, t_ck)) - 1;
 413         tim1 |= val << T_RP_SHIFT;
 414
 415         return tim1;
 416 }
 417
 418 static u32 get_sdram_tim_1_shdw_derated(const struct lpddr2_timings *timings,
 419                 const struct lpddr2_min_tck *min_tck,
 420                 const struct lpddr2_addressing *addressing)
 421 {
 422         u32 tim1 = 0, val = 0;
 423
 424         val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
 425         tim1 = val << T_WTR_SHIFT;
 426
 427         /*
 428          * tFAW is approximately 4 times tRRD. So add 1875*4 = 7500ps
 429          * to tFAW for de-rating
 430          */
 431         if (addressing->num_banks == B8) {
 432                 val = DIV_ROUND_UP(timings->tFAW + 7500, 4 * t_ck) - 1;
 433         } else {
 434                 val = DIV_ROUND_UP(timings->tRRD + 1875, t_ck);
 435                 val = max(min_tck->tRRD, val) - 1;
 436         }
 437         tim1 |= val << T_RRD_SHIFT;
 438
 439         val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab + 1875, t_ck);
 440         tim1 |= (val - 1) << T_RC_SHIFT;
 441
 442         val = DIV_ROUND_UP(timings->tRAS_min + 1875, t_ck);
 443         val = max(min_tck->tRASmin, val) - 1;
 444         tim1 |= val << T_RAS_SHIFT;
 445
 446         val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
 447         tim1 |= val << T_WR_SHIFT;
 448
 449         val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD + 1875, t_ck));
 450         tim1 |= (val - 1) << T_RCD_SHIFT;
 451
 452         val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab + 1875, t_ck));
 453         tim1 |= (val - 1) << T_RP_SHIFT;
 454
 455         return tim1;
 456 }
 457
 458 static u32 get_sdram_tim_2_shdw(const struct lpddr2_timings *timings,
 459                 const struct lpddr2_min_tck *min_tck,
 460                 const struct lpddr2_addressing *addressing,
 461                 u32 type)
 462 {
 463         u32 tim2 = 0, val = 0;
 464
 465         val = min_tck->tCKE - 1;
 466         tim2 |= val << T_CKE_SHIFT;
 467
 468         val = max(min_tck->tRTP, DIV_ROUND_UP(timings->tRTP, t_ck)) - 1;
 469         tim2 |= val << T_RTP_SHIFT;
 470
 471         /* tXSNR = tRFCab_ps + 10 ns(tRFCab_ps for LPDDR2). */
 472         val = DIV_ROUND_UP(addressing->tRFCab_ps + 10000, t_ck) - 1;
 473         tim2 |= val << T_XSNR_SHIFT;
 474
 475         /* XSRD same as XSNR for LPDDR2 */
 476         tim2 |= val << T_XSRD_SHIFT;
 477
 478         val = max(min_tck->tXP, DIV_ROUND_UP(timings->tXP, t_ck)) - 1;
 479         tim2 |= val << T_XP_SHIFT;
 480
 481         return tim2;
 482 }
 483
 484 static u32 get_sdram_tim_3_shdw(const struct lpddr2_timings *timings,
 485                 const struct lpddr2_min_tck *min_tck,
 486                 const struct lpddr2_addressing *addressing,
 487                 u32 type, u32 ip_rev, u32 derated)
 488 {
 489         u32 tim3 = 0, val = 0, t_dqsck;
 490
 491         val = timings->tRAS_max_ns / addressing->tREFI_ns - 1;
 492         val = val > 0xF ? 0xF : val;
 493         tim3 |= val << T_RAS_MAX_SHIFT;
 494
 495         val = DIV_ROUND_UP(addressing->tRFCab_ps, t_ck) - 1;
 496         tim3 |= val << T_RFC_SHIFT;
 497
 498         t_dqsck = (derated == EMIF_DERATED_TIMINGS) ?
 499                 timings->tDQSCK_max_derated : timings->tDQSCK_max;
 500         if (ip_rev == EMIF_4D5)
 501                 val = DIV_ROUND_UP(t_dqsck + 1000, t_ck) - 1;
 502         else
 503                 val = DIV_ROUND_UP(t_dqsck, t_ck) - 1;
 504
 505         tim3 |= val << T_TDQSCKMAX_SHIFT;
 506
 507         val = DIV_ROUND_UP(timings->tZQCS, t_ck) - 1;
 508         tim3 |= val << ZQ_ZQCS_SHIFT;
 509
 510         val = DIV_ROUND_UP(timings->tCKESR, t_ck);
 511         val = max(min_tck->tCKESR, val) - 1;
 512         tim3 |= val << T_CKESR_SHIFT;
 513
 514         if (ip_rev == EMIF_4D5) {
 515                 tim3 |= (EMIF_T_CSTA - 1) << T_CSTA_SHIFT;
 516
 517                 val = DIV_ROUND_UP(EMIF_T_PDLL_UL, 128) - 1;
 518                 tim3 |= val << T_PDLL_UL_SHIFT;
 519         }
 520
 521         return tim3;
 522 }
 523
 524 static u32 get_zq_config_reg(const struct lpddr2_addressing *addressing,
 525                 bool cs1_used, bool cal_resistors_per_cs)
 526 {
 527         u32 zq = 0, val = 0;
 528
 529         val = EMIF_ZQCS_INTERVAL_US * 1000 / addressing->tREFI_ns;
 530         zq |= val << ZQ_REFINTERVAL_SHIFT;
 531
 532         val = DIV_ROUND_UP(T_ZQCL_DEFAULT_NS, T_ZQCS_DEFAULT_NS) - 1;
 533         zq |= val << ZQ_ZQCL_MULT_SHIFT;
 534
 535         val = DIV_ROUND_UP(T_ZQINIT_DEFAULT_NS, T_ZQCL_DEFAULT_NS) - 1;
 536         zq |= val << ZQ_ZQINIT_MULT_SHIFT;
 537
 538         zq |= ZQ_SFEXITEN_ENABLE << ZQ_SFEXITEN_SHIFT;
 539
 540         if (cal_resistors_per_cs)
 541                 zq |= ZQ_DUALCALEN_ENABLE << ZQ_DUALCALEN_SHIFT;
 542         else
 543                 zq |= ZQ_DUALCALEN_DISABLE << ZQ_DUALCALEN_SHIFT;
 544
 545         zq |= ZQ_CS0EN_MASK; /* CS0 is used for sure */
 546
 547         val = cs1_used ? 1 : 0;
 548         zq |= val << ZQ_CS1EN_SHIFT;
 549
 550         return zq;
 551 }
 552
 553 static u32 get_temp_alert_config(const struct lpddr2_addressing *addressing,
 554                 const struct emif_custom_configs *custom_configs, bool cs1_used,
 555                 u32 sdram_io_width, u32 emif_bus_width)
 556 {
 557         u32 alert = 0, interval, devcnt;
 558
 559         if (custom_configs && (custom_configs->mask &
 560                                 EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL))
 561                 interval = custom_configs->temp_alert_poll_interval_ms;
 562         else
 563                 interval = TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS;
 564
 565         interval *= 1000000;                    /* Convert to ns */
 566         interval /= addressing->tREFI_ns;       /* Convert to refresh cycles */
 567         alert |= (interval << TA_REFINTERVAL_SHIFT);
 568
 569         /*
 570          * sdram_io_width is in 'log2(x) - 1' form. Convert emif_bus_width
 571          * also to this form and subtract to get TA_DEVCNT, which is
 572          * in log2(x) form.
 573          */
 574         emif_bus_width = __fls(emif_bus_width) - 1;
 575         devcnt = emif_bus_width - sdram_io_width;
 576         alert |= devcnt << TA_DEVCNT_SHIFT;
 577
 578         /* DEVWDT is in 'log2(x) - 3' form */
 579         alert |= (sdram_io_width - 2) << TA_DEVWDT_SHIFT;
 580
 581         alert |= 1 << TA_SFEXITEN_SHIFT;
 582         alert |= 1 << TA_CS0EN_SHIFT;
 583         alert |= (cs1_used ? 1 : 0) << TA_CS1EN_SHIFT;
 584
 585         return alert;
 586 }
 587
 588 static u32 get_read_idle_ctrl_shdw(u8 volt_ramp)
 589 {
 590         u32 idle = 0, val = 0;
 591
 592         /*
 593          * Maximum value in normal conditions and increased frequency
 594          * when voltage is ramping
 595          */
 596         if (volt_ramp)
 597                 val = READ_IDLE_INTERVAL_DVFS / t_ck / 64 - 1;
 598         else
 599                 val = 0x1FF;
 600
 601         /*
 602          * READ_IDLE_CTRL register in EMIF4D has same offset and fields
 603          * as DLL_CALIB_CTRL in EMIF4D5, so use the same shifts
 604          */
 605         idle |= val << DLL_CALIB_INTERVAL_SHIFT;
 606         idle |= EMIF_READ_IDLE_LEN_VAL << ACK_WAIT_SHIFT;
 607
 608         return idle;
 609 }
 610
 611 static u32 get_dll_calib_ctrl_shdw(u8 volt_ramp)
 612 {
 613         u32 calib = 0, val = 0;
 614
 615         if (volt_ramp == DDR_VOLTAGE_RAMPING)
 616                 val = DLL_CALIB_INTERVAL_DVFS / t_ck / 16 - 1;
 617         else
 618                 val = 0; /* Disabled when voltage is stable */
 619
 620         calib |= val << DLL_CALIB_INTERVAL_SHIFT;
 621         calib |= DLL_CALIB_ACK_WAIT_VAL << ACK_WAIT_SHIFT;
 622
 623         return calib;
 624 }
 625
 626 static u32 get_ddr_phy_ctrl_1_attilaphy_4d(const struct lpddr2_timings *timings,
 627         u32 freq, u8 RL)
 628 {
 629         u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY, val = 0;
 630
 631         val = RL + DIV_ROUND_UP(timings->tDQSCK_max, t_ck) - 1;
 632         phy |= val << READ_LATENCY_SHIFT_4D;
 633
 634         if (freq <= 100000000)
 635                 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY;
 636         else if (freq <= 200000000)
 637                 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY;
 638         else
 639                 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY;
 640
 641         phy |= val << DLL_SLAVE_DLY_CTRL_SHIFT_4D;
 642
 643         return phy;
 644 }
 645
 646 static u32 get_phy_ctrl_1_intelliphy_4d5(u32 freq, u8 cl)
 647 {
 648         u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY, half_delay;
 649
 650         /*
 651          * DLL operates at 266 MHz. If DDR frequency is near 266 MHz,
 652          * half-delay is not needed else set half-delay
 653          */
 654         if (freq >= 265000000 && freq < 267000000)
 655                 half_delay = 0;
 656         else
 657                 half_delay = 1;
 658
 659         phy |= half_delay << DLL_HALF_DELAY_SHIFT_4D5;
 660         phy |= ((cl + DIV_ROUND_UP(EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS,
 661                         t_ck) - 1) << READ_LATENCY_SHIFT_4D5);
 662
 663         return phy;
 664 }
 665
 666 static u32 get_ext_phy_ctrl_2_intelliphy_4d5(void)
 667 {
 668         u32 fifo_we_slave_ratio;
 669
 670         fifo_we_slave_ratio =  DIV_ROUND_CLOSEST(
 671                 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
 672
 673         return fifo_we_slave_ratio | fifo_we_slave_ratio << 11 |
 674                 fifo_we_slave_ratio << 22;
 675 }
 676
 677 static u32 get_ext_phy_ctrl_3_intelliphy_4d5(void)
 678 {
 679         u32 fifo_we_slave_ratio;
 680
 681         fifo_we_slave_ratio =  DIV_ROUND_CLOSEST(
 682                 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
 683
 684         return fifo_we_slave_ratio >> 10 | fifo_we_slave_ratio << 1 |
 685                 fifo_we_slave_ratio << 12 | fifo_we_slave_ratio << 23;
 686 }
 687
 688 static u32 get_ext_phy_ctrl_4_intelliphy_4d5(void)
 689 {
 690         u32 fifo_we_slave_ratio;
 691
 692         fifo_we_slave_ratio =  DIV_ROUND_CLOSEST(
 693                 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
 694
 695         return fifo_we_slave_ratio >> 9 | fifo_we_slave_ratio << 2 |
 696                 fifo_we_slave_ratio << 13;
 697 }
 698
 699 static u32 get_pwr_mgmt_ctrl(u32 freq, struct emif_data *emif, u32 ip_rev)
 700 {
 701         u32 pwr_mgmt_ctrl       = 0, timeout;
 702         u32 lpmode              = EMIF_LP_MODE_SELF_REFRESH;
 703         u32 timeout_perf        = EMIF_LP_MODE_TIMEOUT_PERFORMANCE;
 704         u32 timeout_pwr         = EMIF_LP_MODE_TIMEOUT_POWER;
 705         u32 freq_threshold      = EMIF_LP_MODE_FREQ_THRESHOLD;
 706
 707         struct emif_custom_configs *cust_cfgs = emif->plat_data->custom_configs;
 708
 709         if (cust_cfgs && (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE)) {
 710                 lpmode          = cust_cfgs->lpmode;
 711                 timeout_perf    = cust_cfgs->lpmode_timeout_performance;
 712                 timeout_pwr     = cust_cfgs->lpmode_timeout_power;
 713                 freq_threshold  = cust_cfgs->lpmode_freq_threshold;
 714         }
 715
 716         /* Timeout based on DDR frequency */
 717         timeout = freq >= freq_threshold ? timeout_perf : timeout_pwr;
 718
 719         /* The value to be set in register is "log2(timeout) - 3" */
 720         if (timeout < 16) {
 721                 timeout = 0;
 722         } else {
 723                 timeout = __fls(timeout) - 3;
 724                 if (timeout & (timeout - 1))
 725                         timeout++;
 726         }
 727
 728         switch (lpmode) {
 729         case EMIF_LP_MODE_CLOCK_STOP:
 730                 pwr_mgmt_ctrl = (timeout << CS_TIM_SHIFT) |
 731                                         SR_TIM_MASK | PD_TIM_MASK;
 732                 break;
 733         case EMIF_LP_MODE_SELF_REFRESH:
 734                 /* Workaround for errata i735 */
 735                 if (timeout < 6)
 736                         timeout = 6;
 737
 738                 pwr_mgmt_ctrl = (timeout << SR_TIM_SHIFT) |
 739                                         CS_TIM_MASK | PD_TIM_MASK;
 740                 break;
 741         case EMIF_LP_MODE_PWR_DN:
 742                 pwr_mgmt_ctrl = (timeout << PD_TIM_SHIFT) |
 743                                         CS_TIM_MASK | SR_TIM_MASK;
 744                 break;
 745         case EMIF_LP_MODE_DISABLE:
 746         default:
 747                 pwr_mgmt_ctrl = CS_TIM_MASK |
 748                                         PD_TIM_MASK | SR_TIM_MASK;
 749         }
 750
 751         /* No CS_TIM in EMIF_4D5 */
 752         if (ip_rev == EMIF_4D5)
 753                 pwr_mgmt_ctrl &= ~CS_TIM_MASK;
 754
 755         pwr_mgmt_ctrl |= lpmode << LP_MODE_SHIFT;
 756
 757         return pwr_mgmt_ctrl;
 758 }
 759
 760 /*
 761  * Get the temperature level of the EMIF instance:
 762  * Reads the MR4 register of attached SDRAM parts to find out the temperature
 763  * level. If there are two parts attached(one on each CS), then the temperature
 764  * level for the EMIF instance is the higher of the two temperatures.
 765  */
 766 static void get_temperature_level(struct emif_data *emif)
 767 {
 768         u32             temp, temperature_level;
 769         void __iomem    *base;
 770
 771         base = emif->base;
 772
 773         /* Read mode register 4 */
 774         writel(DDR_MR4, base + EMIF_LPDDR2_MODE_REG_CONFIG);
 775         temperature_level = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
 776         temperature_level = (temperature_level & MR4_SDRAM_REF_RATE_MASK) >>
 777                                 MR4_SDRAM_REF_RATE_SHIFT;
 778
 779         if (emif->plat_data->device_info->cs1_used) {
 780                 writel(DDR_MR4 | CS_MASK, base + EMIF_LPDDR2_MODE_REG_CONFIG);
 781                 temp = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
 782                 temp = (temp & MR4_SDRAM_REF_RATE_MASK)
 783                                 >> MR4_SDRAM_REF_RATE_SHIFT;
 784                 temperature_level = max(temp, temperature_level);
 785         }
 786
 787         /* treat everything less than nominal(3) in MR4 as nominal */
 788         if (unlikely(temperature_level < SDRAM_TEMP_NOMINAL))
 789                 temperature_level = SDRAM_TEMP_NOMINAL;
 790
 791         /* if we get reserved value in MR4 persist with the existing value */
 792         if (likely(temperature_level != SDRAM_TEMP_RESERVED_4))
 793                 emif->temperature_level = temperature_level;
 794 }
 795
 796 /*
 797  * Program EMIF shadow registers that are not dependent on temperature
 798  * or voltage
 799  */
 800 static void setup_registers(struct emif_data *emif, struct emif_regs *regs)
 801 {
 802         void __iomem    *base = emif->base;
 803
 804         writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW);
 805         writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW);
 806
 807         /* Settings specific for EMIF4D5 */
 808         if (emif->plat_data->ip_rev != EMIF_4D5)
 809                 return;
 810         writel(regs->ext_phy_ctrl_2_shdw, base + EMIF_EXT_PHY_CTRL_2_SHDW);
 811         writel(regs->ext_phy_ctrl_3_shdw, base + EMIF_EXT_PHY_CTRL_3_SHDW);
 812         writel(regs->ext_phy_ctrl_4_shdw, base + EMIF_EXT_PHY_CTRL_4_SHDW);
 813 }
 814
 815 /*
 816  * When voltage ramps dll calibration and forced read idle should
 817  * happen more often
 818  */
 819 static void setup_volt_sensitive_regs(struct emif_data *emif,
 820                 struct emif_regs *regs, u32 volt_state)
 821 {
 822         u32             calib_ctrl;
 823         void __iomem    *base = emif->base;
 824
 825         /*
 826          * EMIF_READ_IDLE_CTRL in EMIF4D refers to the same register as
 827          * EMIF_DLL_CALIB_CTRL in EMIF4D5 and dll_calib_ctrl_shadow_*
 828          * is an alias of the respective read_idle_ctrl_shdw_* (members of
 829          * a union). So, the below code takes care of both cases
 830          */
 831         if (volt_state == DDR_VOLTAGE_RAMPING)
 832                 calib_ctrl = regs->dll_calib_ctrl_shdw_volt_ramp;
 833         else
 834                 calib_ctrl = regs->dll_calib_ctrl_shdw_normal;
 835
 836         writel(calib_ctrl, base + EMIF_DLL_CALIB_CTRL_SHDW);
 837 }
 838
 839 /*
 840  * setup_temperature_sensitive_regs() - set the timings for temperature
 841  * sensitive registers. This happens once at initialisation time based
 842  * on the temperature at boot time and subsequently based on the temperature
 843  * alert interrupt. Temperature alert can happen when the temperature
 844  * increases or drops. So this function can have the effect of either
 845  * derating the timings or going back to nominal values.
 846  */
 847 static void setup_temperature_sensitive_regs(struct emif_data *emif,
 848                 struct emif_regs *regs)
 849 {
 850         u32             tim1, tim3, ref_ctrl, type;
 851         void __iomem    *base = emif->base;
 852         u32             temperature;
 853
 854         type = emif->plat_data->device_info->type;
 855
 856         tim1 = regs->sdram_tim1_shdw;
 857         tim3 = regs->sdram_tim3_shdw;
 858         ref_ctrl = regs->ref_ctrl_shdw;
 859
 860         /* No de-rating for non-lpddr2 devices */
 861         if (type != DDR_TYPE_LPDDR2_S2 && type != DDR_TYPE_LPDDR2_S4)
 862                 goto out;
 863
 864         temperature = emif->temperature_level;
 865         if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH) {
 866                 ref_ctrl = regs->ref_ctrl_shdw_derated;
 867         } else if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS) {
 868                 tim1 = regs->sdram_tim1_shdw_derated;
 869                 tim3 = regs->sdram_tim3_shdw_derated;
 870                 ref_ctrl = regs->ref_ctrl_shdw_derated;
 871         }
 872
 873 out:
 874         writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW);
 875         writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW);
 876         writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW);
 877 }
 878
 879 static irqreturn_t handle_temp_alert(void __iomem *base, struct emif_data *emif)
 880 {
 881         u32             old_temp_level;
 882         irqreturn_t     ret = IRQ_HANDLED;
 883
 884         spin_lock_irqsave(&emif_lock, irq_state);
 885         old_temp_level = emif->temperature_level;
 886         get_temperature_level(emif);
 887
 888         if (unlikely(emif->temperature_level == old_temp_level)) {
 889                 goto out;
 890         } else if (!emif->curr_regs) {
 891                 dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
 892                 goto out;
 893         }
 894
 895         if (emif->temperature_level < old_temp_level ||
 896                 emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
 897                 /*
 898                  * Temperature coming down - defer handling to thread OR
 899                  * Temperature far too high - do kernel_power_off() from
 900                  * thread context
 901                  */
 902                 ret = IRQ_WAKE_THREAD;
 903         } else {
 904                 /* Temperature is going up - handle immediately */
 905                 setup_temperature_sensitive_regs(emif, emif->curr_regs);
 906                 do_freq_update();
 907         }
 908
 909 out:
 910         spin_unlock_irqrestore(&emif_lock, irq_state);
 911         return ret;
 912 }
 913
 914 static irqreturn_t emif_interrupt_handler(int irq, void *dev_id)
 915 {
 916         u32                     interrupts;
 917         struct emif_data        *emif = dev_id;
 918         void __iomem            *base = emif->base;
 919         struct device           *dev = emif->dev;
 920         irqreturn_t             ret = IRQ_HANDLED;
 921
 922         /* Save the status and clear it */
 923         interrupts = readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
 924         writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
 925
 926         /*
 927          * Handle temperature alert
 928          * Temperature alert should be same for all ports
 929          * So, it's enough to process it only for one of the ports
 930          */
 931         if (interrupts & TA_SYS_MASK)
 932                 ret = handle_temp_alert(base, emif);
 933
 934         if (interrupts & ERR_SYS_MASK)
 935                 dev_err(dev, "Access error from SYS port - %x\n", interrupts);
 936
 937         if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
 938                 /* Save the status and clear it */
 939                 interrupts = readl(base + EMIF_LL_OCP_INTERRUPT_STATUS);
 940                 writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_STATUS);
 941
 942                 if (interrupts & ERR_LL_MASK)
 943                         dev_err(dev, "Access error from LL port - %x\n",
 944                                 interrupts);
 945         }
 946
 947         return ret;
 948 }
 949
 950 static irqreturn_t emif_threaded_isr(int irq, void *dev_id)
 951 {
 952         struct emif_data        *emif = dev_id;
 953
 954         if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
 955                 dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
 956                 kernel_power_off();
 957                 return IRQ_HANDLED;
 958         }
 959
 960         spin_lock_irqsave(&emif_lock, irq_state);
 961
 962         if (emif->curr_regs) {
 963                 setup_temperature_sensitive_regs(emif, emif->curr_regs);
 964                 do_freq_update();
 965         } else {
 966                 dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
 967         }
 968
 969         spin_unlock_irqrestore(&emif_lock, irq_state);
 970
 971         return IRQ_HANDLED;
 972 }
 973
 974 static void clear_all_interrupts(struct emif_data *emif)
 975 {
 976         void __iomem    *base = emif->base;
 977
 978         writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS),
 979                 base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
 980         if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
 981                 writel(readl(base + EMIF_LL_OCP_INTERRUPT_STATUS),
 982                         base + EMIF_LL_OCP_INTERRUPT_STATUS);
 983 }
 984
 985 static void disable_and_clear_all_interrupts(struct emif_data *emif)
 986 {
 987         void __iomem            *base = emif->base;
 988
 989         /* Disable all interrupts */
 990         writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET),
 991                 base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR);
 992         if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
 993                 writel(readl(base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET),
 994                         base + EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR);
 995
 996         /* Clear all interrupts */
 997         clear_all_interrupts(emif);
 998 }
 999
1000 static int __init_or_module setup_interrupts(struct emif_data *emif, u32 irq)
1001 {
1002         u32             interrupts, type;
1003         void __iomem    *base = emif->base;
1004
1005         type = emif->plat_data->device_info->type;
1006
1007         clear_all_interrupts(emif);
1008
1009         /* Enable interrupts for SYS interface */
1010         interrupts = EN_ERR_SYS_MASK;
1011         if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4)
1012                 interrupts |= EN_TA_SYS_MASK;
1013         writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET);
1014
1015         /* Enable interrupts for LL interface */
1016         if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
1017                 /* TA need not be enabled for LL */
1018                 interrupts = EN_ERR_LL_MASK;
1019                 writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET);
1020         }
1021
1022         /* setup IRQ handlers */
1023         return devm_request_threaded_irq(emif->dev, irq,
1024                                     emif_interrupt_handler,
1025                                     emif_threaded_isr,
1026                                     0, dev_name(emif->dev),
1027                                     emif);
1028
1029 }
1030
1031 static void __init_or_module emif_onetime_settings(struct emif_data *emif)
1032 {
1033         u32                             pwr_mgmt_ctrl, zq, temp_alert_cfg;
1034         void __iomem                    *base = emif->base;
1035         const struct lpddr2_addressing  *addressing;
1036         const struct ddr_device_info    *device_info;
1037
1038         device_info = emif->plat_data->device_info;
1039         addressing = get_addressing_table(device_info);
1040
1041         /*
1042          * Init power management settings
1043          * We don't know the frequency yet. Use a high frequency
1044          * value for a conservative timeout setting
1045          */
1046         pwr_mgmt_ctrl = get_pwr_mgmt_ctrl(1000000000, emif,
1047                         emif->plat_data->ip_rev);
1048         emif->lpmode = (pwr_mgmt_ctrl & LP_MODE_MASK) >> LP_MODE_SHIFT;
1049         writel(pwr_mgmt_ctrl, base + EMIF_POWER_MANAGEMENT_CONTROL);
1050
1051         /* Init ZQ calibration settings */
1052         zq = get_zq_config_reg(addressing, device_info->cs1_used,
1053                 device_info->cal_resistors_per_cs);
1054         writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG);
1055
1056         /* Check temperature level temperature level*/
1057         get_temperature_level(emif);
1058         if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN)
1059                 dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
1060
1061         /* Init temperature polling */
1062         temp_alert_cfg = get_temp_alert_config(addressing,
1063                 emif->plat_data->custom_configs, device_info->cs1_used,
1064                 device_info->io_width, get_emif_bus_width(emif));
1065         writel(temp_alert_cfg, base + EMIF_TEMPERATURE_ALERT_CONFIG);
1066
1067         /*
1068          * Program external PHY control registers that are not frequency
1069          * dependent
1070          */
1071         if (emif->plat_data->phy_type != EMIF_PHY_TYPE_INTELLIPHY)
1072                 return;
1073         writel(EMIF_EXT_PHY_CTRL_1_VAL, base + EMIF_EXT_PHY_CTRL_1_SHDW);
1074         writel(EMIF_EXT_PHY_CTRL_5_VAL, base + EMIF_EXT_PHY_CTRL_5_SHDW);
1075         writel(EMIF_EXT_PHY_CTRL_6_VAL, base + EMIF_EXT_PHY_CTRL_6_SHDW);
1076         writel(EMIF_EXT_PHY_CTRL_7_VAL, base + EMIF_EXT_PHY_CTRL_7_SHDW);
1077         writel(EMIF_EXT_PHY_CTRL_8_VAL, base + EMIF_EXT_PHY_CTRL_8_SHDW);
1078         writel(EMIF_EXT_PHY_CTRL_9_VAL, base + EMIF_EXT_PHY_CTRL_9_SHDW);
1079         writel(EMIF_EXT_PHY_CTRL_10_VAL, base + EMIF_EXT_PHY_CTRL_10_SHDW);
1080         writel(EMIF_EXT_PHY_CTRL_11_VAL, base + EMIF_EXT_PHY_CTRL_11_SHDW);
1081         writel(EMIF_EXT_PHY_CTRL_12_VAL, base + EMIF_EXT_PHY_CTRL_12_SHDW);
1082         writel(EMIF_EXT_PHY_CTRL_13_VAL, base + EMIF_EXT_PHY_CTRL_13_SHDW);
1083         writel(EMIF_EXT_PHY_CTRL_14_VAL, base + EMIF_EXT_PHY_CTRL_14_SHDW);
1084         writel(EMIF_EXT_PHY_CTRL_15_VAL, base + EMIF_EXT_PHY_CTRL_15_SHDW);
1085         writel(EMIF_EXT_PHY_CTRL_16_VAL, base + EMIF_EXT_PHY_CTRL_16_SHDW);
1086         writel(EMIF_EXT_PHY_CTRL_17_VAL, base + EMIF_EXT_PHY_CTRL_17_SHDW);
1087         writel(EMIF_EXT_PHY_CTRL_18_VAL, base + EMIF_EXT_PHY_CTRL_18_SHDW);
1088         writel(EMIF_EXT_PHY_CTRL_19_VAL, base + EMIF_EXT_PHY_CTRL_19_SHDW);
1089         writel(EMIF_EXT_PHY_CTRL_20_VAL, base + EMIF_EXT_PHY_CTRL_20_SHDW);
1090         writel(EMIF_EXT_PHY_CTRL_21_VAL, base + EMIF_EXT_PHY_CTRL_21_SHDW);
1091         writel(EMIF_EXT_PHY_CTRL_22_VAL, base + EMIF_EXT_PHY_CTRL_22_SHDW);
1092         writel(EMIF_EXT_PHY_CTRL_23_VAL, base + EMIF_EXT_PHY_CTRL_23_SHDW);
1093         writel(EMIF_EXT_PHY_CTRL_24_VAL, base + EMIF_EXT_PHY_CTRL_24_SHDW);
1094 }
1095
1096 static void get_default_timings(struct emif_data *emif)
1097 {
1098         struct emif_platform_data *pd = emif->plat_data;
1099
1100         pd->timings             = lpddr2_jedec_timings;
1101         pd->timings_arr_size    = ARRAY_SIZE(lpddr2_jedec_timings);
1102
1103         dev_warn(emif->dev, "%s: using default timings\n", __func__);
1104 }
1105
1106 static int is_dev_data_valid(u32 type, u32 density, u32 io_width, u32 phy_type,
1107                 u32 ip_rev, struct device *dev)
1108 {
1109         int valid;
1110
1111         valid = (type == DDR_TYPE_LPDDR2_S4 ||
1112                         type == DDR_TYPE_LPDDR2_S2)
1113                 && (density >= DDR_DENSITY_64Mb
1114                         && density <= DDR_DENSITY_8Gb)
1115                 && (io_width >= DDR_IO_WIDTH_8
1116                         && io_width <= DDR_IO_WIDTH_32);
1117
1118         /* Combinations of EMIF and PHY revisions that we support today */
1119         switch (ip_rev) {
1120         case EMIF_4D:
1121                 valid = valid && (phy_type == EMIF_PHY_TYPE_ATTILAPHY);
1122                 break;
1123         case EMIF_4D5:
1124                 valid = valid && (phy_type == EMIF_PHY_TYPE_INTELLIPHY);
1125                 break;
1126         default:
1127                 valid = 0;
1128         }
1129
1130         if (!valid)
1131                 dev_err(dev, "%s: invalid DDR details\n", __func__);
1132         return valid;
1133 }
1134
1135 static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs,
1136                 struct device *dev)
1137 {
1138         int valid = 1;
1139
1140         if ((cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE) &&
1141                 (cust_cfgs->lpmode != EMIF_LP_MODE_DISABLE))
1142                 valid = cust_cfgs->lpmode_freq_threshold &&
1143                         cust_cfgs->lpmode_timeout_performance &&
1144                         cust_cfgs->lpmode_timeout_power;
1145
1146         if (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL)
1147                 valid = valid && cust_cfgs->temp_alert_poll_interval_ms;
1148
1149         if (!valid)
1150                 dev_warn(dev, "%s: invalid custom configs\n", __func__);
1151
1152         return valid;
1153 }
1154
1155 #if defined(CONFIG_OF)
1156 static void __init_or_module of_get_custom_configs(struct device_node *np_emif,
1157                 struct emif_data *emif)
1158 {
1159         struct emif_custom_configs      *cust_cfgs = NULL;
1160         int                             len;
1161         const int                       *lpmode, *poll_intvl;
1162
1163         lpmode = of_get_property(np_emif, "low-power-mode", &len);
1164         poll_intvl = of_get_property(np_emif, "temp-alert-poll-interval", &len);
1165
1166         if (lpmode || poll_intvl)
1167                 cust_cfgs = devm_kzalloc(emif->dev, sizeof(*cust_cfgs),
1168                         GFP_KERNEL);
1169
1170         if (!cust_cfgs)
1171                 return;
1172
1173         if (lpmode) {
1174                 cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_LPMODE;
1175                 cust_cfgs->lpmode = *lpmode;
1176                 of_property_read_u32(np_emif,
1177                                 "low-power-mode-timeout-performance",
1178                                 &cust_cfgs->lpmode_timeout_performance);
1179                 of_property_read_u32(np_emif,
1180                                 "low-power-mode-timeout-power",
1181                                 &cust_cfgs->lpmode_timeout_power);
1182                 of_property_read_u32(np_emif,
1183                                 "low-power-mode-freq-threshold",
1184                                 &cust_cfgs->lpmode_freq_threshold);
1185         }
1186
1187         if (poll_intvl) {
1188                 cust_cfgs->mask |=
1189                                 EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL;
1190                 cust_cfgs->temp_alert_poll_interval_ms = *poll_intvl;
1191         }
1192
1193         if (!is_custom_config_valid(cust_cfgs, emif->dev)) {
1194                 devm_kfree(emif->dev, cust_cfgs);
1195                 return;
1196         }
1197
1198         emif->plat_data->custom_configs = cust_cfgs;
1199 }
1200
1201 static void __init_or_module of_get_ddr_info(struct device_node *np_emif,
1202                 struct device_node *np_ddr,
1203                 struct ddr_device_info *dev_info)
1204 {
1205         u32 density = 0, io_width = 0;
1206         int len;
1207
1208         if (of_find_property(np_emif, "cs1-used", &len))
1209                 dev_info->cs1_used = true;
1210
1211         if (of_find_property(np_emif, "cal-resistor-per-cs", &len))
1212                 dev_info->cal_resistors_per_cs = true;
1213
1214         if (of_device_is_compatible(np_ddr , "jedec,lpddr2-s4"))
1215                 dev_info->type = DDR_TYPE_LPDDR2_S4;
1216         else if (of_device_is_compatible(np_ddr , "jedec,lpddr2-s2"))
1217                 dev_info->type = DDR_TYPE_LPDDR2_S2;
1218
1219         of_property_read_u32(np_ddr, "density", &density);
1220         of_property_read_u32(np_ddr, "io-width", &io_width);
1221
1222         /* Convert from density in Mb to the density encoding in jedc_ddr.h */
1223         if (density & (density - 1))
1224                 dev_info->density = 0;
1225         else
1226                 dev_info->density = __fls(density) - 5;
1227
1228         /* Convert from io_width in bits to io_width encoding in jedc_ddr.h */
1229         if (io_width & (io_width - 1))
1230                 dev_info->io_width = 0;
1231         else
1232                 dev_info->io_width = __fls(io_width) - 1;
1233 }
1234
1235 static struct emif_data * __init_or_module of_get_memory_device_details(
1236                 struct device_node *np_emif, struct device *dev)
1237 {
1238         struct emif_data                *emif = NULL;
1239         struct ddr_device_info          *dev_info = NULL;
1240         struct emif_platform_data       *pd = NULL;
1241         struct device_node              *np_ddr;
1242         int                             len;
1243
1244         np_ddr = of_parse_phandle(np_emif, "device-handle", 0);
1245         if (!np_ddr)
1246                 goto error;
1247         emif    = devm_kzalloc(dev, sizeof(struct emif_data), GFP_KERNEL);
1248         pd      = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
1249         dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
1250
1251         if (!emif || !pd || !dev_info) {
1252                 dev_err(dev, "%s: Out of memory!!\n",
1253                         __func__);
1254                 goto error;
1255         }
1256
1257         emif->plat_data         = pd;
1258         pd->device_info         = dev_info;
1259         emif->dev               = dev;
1260         emif->np_ddr            = np_ddr;
1261         emif->temperature_level = SDRAM_TEMP_NOMINAL;
1262
1263         if (of_device_is_compatible(np_emif, "ti,emif-4d"))
1264                 emif->plat_data->ip_rev = EMIF_4D;
1265         else if (of_device_is_compatible(np_emif, "ti,emif-4d5"))
1266                 emif->plat_data->ip_rev = EMIF_4D5;
1267
1268         of_property_read_u32(np_emif, "phy-type", &pd->phy_type);
1269
1270         if (of_find_property(np_emif, "hw-caps-ll-interface", &len))
1271                 pd->hw_caps |= EMIF_HW_CAPS_LL_INTERFACE;
1272
1273         of_get_ddr_info(np_emif, np_ddr, dev_info);
1274         if (!is_dev_data_valid(pd->device_info->type, pd->device_info->density,
1275                         pd->device_info->io_width, pd->phy_type, pd->ip_rev,
1276                         emif->dev)) {
1277                 dev_err(dev, "%s: invalid device data!!\n", __func__);
1278                 goto error;
1279         }
1280         /*
1281          * For EMIF instances other than EMIF1 see if the devices connected
1282          * are exactly same as on EMIF1(which is typically the case). If so,
1283          * mark it as a duplicate of EMIF1. This will save some memory and
1284          * computation.
1285          */
1286         if (emif1 && emif1->np_ddr == np_ddr) {
1287                 emif->duplicate = true;
1288                 goto out;
1289         } else if (emif1) {
1290                 dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
1291                         __func__);
1292         }
1293
1294         of_get_custom_configs(np_emif, emif);
1295         emif->plat_data->timings = of_get_ddr_timings(np_ddr, emif->dev,
1296                                         emif->plat_data->device_info->type,
1297                                         &emif->plat_data->timings_arr_size);
1298
1299         emif->plat_data->min_tck = of_get_min_tck(np_ddr, emif->dev);
1300         goto out;
1301
1302 error:
1303         return NULL;
1304 out:
1305         return emif;
1306 }
1307
1308 #else
1309
1310 static struct emif_data * __init_or_module of_get_memory_device_details(
1311                 struct device_node *np_emif, struct device *dev)
1312 {
1313         return NULL;
1314 }
1315 #endif
1316
1317 static struct emif_data *__init_or_module get_device_details(
1318                 struct platform_device *pdev)
1319 {
1320         u32                             size;
1321         struct emif_data                *emif = NULL;
1322         struct ddr_device_info          *dev_info;
1323         struct emif_custom_configs      *cust_cfgs;
1324         struct emif_platform_data       *pd;
1325         struct device                   *dev;
1326         void                            *temp;
1327
1328         pd = pdev->dev.platform_data;
1329         dev = &pdev->dev;
1330
1331         if (!(pd && pd->device_info && is_dev_data_valid(pd->device_info->type,
1332                         pd->device_info->density, pd->device_info->io_width,
1333                         pd->phy_type, pd->ip_rev, dev))) {
1334                 dev_err(dev, "%s: invalid device data\n", __func__);
1335                 goto error;
1336         }
1337
1338         emif    = devm_kzalloc(dev, sizeof(*emif), GFP_KERNEL);
1339         temp    = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
1340         dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
1341
1342         if (!emif || !pd || !dev_info) {
1343                 dev_err(dev, "%s:%d: allocation error\n", __func__, __LINE__);
1344                 goto error;
1345         }
1346
1347         memcpy(temp, pd, sizeof(*pd));
1348         pd = temp;
1349         memcpy(dev_info, pd->device_info, sizeof(*dev_info));
1350
1351         pd->device_info         = dev_info;
1352         emif->plat_data         = pd;
1353         emif->dev               = dev;
1354         emif->temperature_level = SDRAM_TEMP_NOMINAL;
1355
1356         /*
1357          * For EMIF instances other than EMIF1 see if the devices connected
1358          * are exactly same as on EMIF1(which is typically the case). If so,
1359          * mark it as a duplicate of EMIF1 and skip copying timings data.
1360          * This will save some memory and some computation later.
1361          */
1362         emif->duplicate = emif1 && (memcmp(dev_info,
1363                 emif1->plat_data->device_info,
1364                 sizeof(struct ddr_device_info)) == 0);
1365
1366         if (emif->duplicate) {
1367                 pd->timings = NULL;
1368                 pd->min_tck = NULL;
1369                 goto out;
1370         } else if (emif1) {
1371                 dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
1372                         __func__);
1373         }
1374
1375         /*
1376          * Copy custom configs - ignore allocation error, if any, as
1377          * custom_configs is not very critical
1378          */
1379         cust_cfgs = pd->custom_configs;
1380         if (cust_cfgs && is_custom_config_valid(cust_cfgs, dev)) {
1381                 temp = devm_kzalloc(dev, sizeof(*cust_cfgs), GFP_KERNEL);
1382                 if (temp)
1383                         memcpy(temp, cust_cfgs, sizeof(*cust_cfgs));
1384                 else
1385                         dev_warn(dev, "%s:%d: allocation error\n", __func__,
1386                                 __LINE__);
1387                 pd->custom_configs = temp;
1388         }
1389
1390         /*
1391          * Copy timings and min-tck values from platform data. If it is not
1392          * available or if memory allocation fails, use JEDEC defaults
1393          */
1394         size = sizeof(struct lpddr2_timings) * pd->timings_arr_size;
1395         if (pd->timings) {
1396                 temp = devm_kzalloc(dev, size, GFP_KERNEL);
1397                 if (temp) {
1398                         memcpy(temp, pd->timings, sizeof(*pd->timings));
1399                         pd->timings = temp;
1400                 } else {
1401                         dev_warn(dev, "%s:%d: allocation error\n", __func__,
1402                                 __LINE__);
1403                         get_default_timings(emif);
1404                 }
1405         } else {
1406                 get_default_timings(emif);
1407         }
1408
1409         if (pd->min_tck) {
1410                 temp = devm_kzalloc(dev, sizeof(*pd->min_tck), GFP_KERNEL);
1411                 if (temp) {
1412                         memcpy(temp, pd->min_tck, sizeof(*pd->min_tck));
1413                         pd->min_tck = temp;
1414                 } else {
1415                         dev_warn(dev, "%s:%d: allocation error\n", __func__,
1416                                 __LINE__);
1417                         pd->min_tck = &lpddr2_jedec_min_tck;
1418                 }
1419         } else {
1420                 pd->min_tck = &lpddr2_jedec_min_tck;
1421         }
1422
1423 out:
1424         return emif;
1425
1426 error:
1427         return NULL;
1428 }
1429
1430 static int __init_or_module emif_probe(struct platform_device *pdev)
1431 {
1432         struct emif_data        *emif;
1433         struct resource         *res;
1434         int                     irq;
1435
1436         if (pdev->dev.of_node)
1437                 emif = of_get_memory_device_details(pdev->dev.of_node, &pdev->dev);
1438         else
1439                 emif = get_device_details(pdev);
1440
1441         if (!emif) {
1442                 pr_err("%s: error getting device data\n", __func__);
1443                 goto error;
1444         }
1445
1446         list_add(&emif->node, &device_list);
1447         emif->addressing = get_addressing_table(emif->plat_data->device_info);
1448
1449         /* Save pointers to each other in emif and device structures */
1450         emif->dev = &pdev->dev;
1451         platform_set_drvdata(pdev, emif);
1452
1453         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1454         if (!res) {
1455                 dev_err(emif->dev, "%s: error getting memory resource\n",
1456                         __func__);
1457                 goto error;
1458         }
1459
1460         emif->base = devm_request_and_ioremap(emif->dev, res);
1461         if (!emif->base) {
1462                 dev_err(emif->dev, "%s: devm_request_and_ioremap() failed\n",
1463                         __func__);
1464                 goto error;
1465         }
1466
1467         irq = platform_get_irq(pdev, 0);
1468         if (irq < 0) {
1469                 dev_err(emif->dev, "%s: error getting IRQ resource - %d\n",
1470                         __func__, irq);
1471                 goto error;
1472         }
1473
1474         emif_onetime_settings(emif);
1475         emif_debugfs_init(emif);
1476         disable_and_clear_all_interrupts(emif);
1477         setup_interrupts(emif, irq);
1478
1479         /* One-time actions taken on probing the first device */
1480         if (!emif1) {
1481                 emif1 = emif;
1482                 spin_lock_init(&emif_lock);
1483
1484                 /*
1485                  * TODO: register notifiers for frequency and voltage
1486                  * change here once the respective frameworks are
1487                  * available
1488                  */
1489         }
1490
1491         dev_info(&pdev->dev, "%s: device configured with addr = %p and IRQ%d\n",
1492                 __func__, emif->base, irq);
1493
1494         return 0;
1495 error:
1496         return -ENODEV;
1497 }
1498
1499 static int __exit emif_remove(struct platform_device *pdev)
1500 {
1501         struct emif_data *emif = platform_get_drvdata(pdev);
1502
1503         emif_debugfs_exit(emif);
1504
1505         return 0;
1506 }
1507
1508 static void emif_shutdown(struct platform_device *pdev)
1509 {
1510         struct emif_data        *emif = platform_get_drvdata(pdev);
1511
1512         disable_and_clear_all_interrupts(emif);
1513 }
1514
1515 static int get_emif_reg_values(struct emif_data *emif, u32 freq,
1516                 struct emif_regs *regs)
1517 {
1518         u32                             cs1_used, ip_rev, phy_type;
1519         u32                             cl, type;
1520         const struct lpddr2_timings     *timings;
1521         const struct lpddr2_min_tck     *min_tck;
1522         const struct ddr_device_info    *device_info;
1523         const struct lpddr2_addressing  *addressing;
1524         struct emif_data                *emif_for_calc;
1525         struct device                   *dev;
1526         const struct emif_custom_configs *custom_configs;
1527
1528         dev = emif->dev;
1529         /*
1530          * If the devices on this EMIF instance is duplicate of EMIF1,
1531          * use EMIF1 details for the calculation
1532          */
1533         emif_for_calc   = emif->duplicate ? emif1 : emif;
1534         timings         = get_timings_table(emif_for_calc, freq);
1535         addressing      = emif_for_calc->addressing;
1536         if (!timings || !addressing) {
1537                 dev_err(dev, "%s: not enough data available for %dHz",
1538                         __func__, freq);
1539                 return -1;
1540         }
1541
1542         device_info     = emif_for_calc->plat_data->device_info;
1543         type            = device_info->type;
1544         cs1_used        = device_info->cs1_used;
1545         ip_rev          = emif_for_calc->plat_data->ip_rev;
1546         phy_type        = emif_for_calc->plat_data->phy_type;
1547
1548         min_tck         = emif_for_calc->plat_data->min_tck;
1549         custom_configs  = emif_for_calc->plat_data->custom_configs;
1550
1551         set_ddr_clk_period(freq);
1552
1553         regs->ref_ctrl_shdw = get_sdram_ref_ctrl_shdw(freq, addressing);
1554         regs->sdram_tim1_shdw = get_sdram_tim_1_shdw(timings, min_tck,
1555                         addressing);
1556         regs->sdram_tim2_shdw = get_sdram_tim_2_shdw(timings, min_tck,
1557                         addressing, type);
1558         regs->sdram_tim3_shdw = get_sdram_tim_3_shdw(timings, min_tck,
1559                 addressing, type, ip_rev, EMIF_NORMAL_TIMINGS);
1560
1561         cl = get_cl(emif);
1562
1563         if (phy_type == EMIF_PHY_TYPE_ATTILAPHY && ip_rev == EMIF_4D) {
1564                 regs->phy_ctrl_1_shdw = get_ddr_phy_ctrl_1_attilaphy_4d(
1565                         timings, freq, cl);
1566         } else if (phy_type == EMIF_PHY_TYPE_INTELLIPHY && ip_rev == EMIF_4D5) {
1567                 regs->phy_ctrl_1_shdw = get_phy_ctrl_1_intelliphy_4d5(freq, cl);
1568                 regs->ext_phy_ctrl_2_shdw = get_ext_phy_ctrl_2_intelliphy_4d5();
1569                 regs->ext_phy_ctrl_3_shdw = get_ext_phy_ctrl_3_intelliphy_4d5();
1570                 regs->ext_phy_ctrl_4_shdw = get_ext_phy_ctrl_4_intelliphy_4d5();
1571         } else {
1572                 return -1;
1573         }
1574
1575         /* Only timeout values in pwr_mgmt_ctrl_shdw register */
1576         regs->pwr_mgmt_ctrl_shdw =
1577                 get_pwr_mgmt_ctrl(freq, emif_for_calc, ip_rev) &
1578                 (CS_TIM_MASK | SR_TIM_MASK | PD_TIM_MASK);
1579
1580         if (ip_rev & EMIF_4D) {
1581                 regs->read_idle_ctrl_shdw_normal =
1582                         get_read_idle_ctrl_shdw(DDR_VOLTAGE_STABLE);
1583
1584                 regs->read_idle_ctrl_shdw_volt_ramp =
1585                         get_read_idle_ctrl_shdw(DDR_VOLTAGE_RAMPING);
1586         } else if (ip_rev & EMIF_4D5) {
1587                 regs->dll_calib_ctrl_shdw_normal =
1588                         get_dll_calib_ctrl_shdw(DDR_VOLTAGE_STABLE);
1589
1590                 regs->dll_calib_ctrl_shdw_volt_ramp =
1591                         get_dll_calib_ctrl_shdw(DDR_VOLTAGE_RAMPING);
1592         }
1593
1594         if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
1595                 regs->ref_ctrl_shdw_derated = get_sdram_ref_ctrl_shdw(freq / 4,
1596                         addressing);
1597
1598                 regs->sdram_tim1_shdw_derated =
1599                         get_sdram_tim_1_shdw_derated(timings, min_tck,
1600                                 addressing);
1601
1602                 regs->sdram_tim3_shdw_derated = get_sdram_tim_3_shdw(timings,
1603                         min_tck, addressing, type, ip_rev,
1604                         EMIF_DERATED_TIMINGS);
1605         }
1606
1607         regs->freq = freq;
1608
1609         return 0;
1610 }
1611
1612 /*
1613  * get_regs() - gets the cached emif_regs structure for a given EMIF instance
1614  * given frequency(freq):
1615  *
1616  * As an optimisation, every EMIF instance other than EMIF1 shares the
1617  * register cache with EMIF1 if the devices connected on this instance
1618  * are same as that on EMIF1(indicated by the duplicate flag)
1619  *
1620  * If we do not have an entry corresponding to the frequency given, we
1621  * allocate a new entry and calculate the values
1622  *
1623  * Upon finding the right reg dump, save it in curr_regs. It can be
1624  * directly used for thermal de-rating and voltage ramping changes.
1625  */
1626 static struct emif_regs *get_regs(struct emif_data *emif, u32 freq)
1627 {
1628         int                     i;
1629         struct emif_regs        **regs_cache;
1630         struct emif_regs        *regs = NULL;
1631         struct device           *dev;
1632
1633         dev = emif->dev;
1634         if (emif->curr_regs && emif->curr_regs->freq == freq) {
1635                 dev_dbg(dev, "%s: using curr_regs - %u Hz", __func__, freq);
1636                 return emif->curr_regs;
1637         }
1638
1639         if (emif->duplicate)
1640                 regs_cache = emif1->regs_cache;
1641         else
1642                 regs_cache = emif->regs_cache;
1643
1644         for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
1645                 if (regs_cache[i]->freq == freq) {
1646                         regs = regs_cache[i];
1647                         dev_dbg(dev,
1648                                 "%s: reg dump found in reg cache for %u Hz\n",
1649                                 __func__, freq);
1650                         break;
1651                 }
1652         }
1653
1654         /*
1655          * If we don't have an entry for this frequency in the cache create one
1656          * and calculate the values
1657          */
1658         if (!regs) {
1659                 regs = devm_kzalloc(emif->dev, sizeof(*regs), GFP_ATOMIC);
1660                 if (!regs)
1661                         return NULL;
1662
1663                 if (get_emif_reg_values(emif, freq, regs)) {
1664                         devm_kfree(emif->dev, regs);
1665                         return NULL;
1666                 }
1667
1668                 /*
1669                  * Now look for an un-used entry in the cache and save the
1670                  * newly created struct. If there are no free entries
1671                  * over-write the last entry
1672                  */
1673                 for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++)
1674                         ;
1675
1676                 if (i >= EMIF_MAX_NUM_FREQUENCIES) {
1677                         dev_warn(dev, "%s: regs_cache full - reusing a slot!!\n",
1678                                 __func__);
1679                         i = EMIF_MAX_NUM_FREQUENCIES - 1;
1680                         devm_kfree(emif->dev, regs_cache[i]);
1681                 }
1682                 regs_cache[i] = regs;
1683         }
1684
1685         return regs;
1686 }
1687
1688 static void do_volt_notify_handling(struct emif_data *emif, u32 volt_state)
1689 {
1690         dev_dbg(emif->dev, "%s: voltage notification : %d", __func__,
1691                 volt_state);
1692
1693         if (!emif->curr_regs) {
1694                 dev_err(emif->dev,
1695                         "%s: volt-notify before registers are ready: %d\n",
1696                         __func__, volt_state);
1697                 return;
1698         }
1699
1700         setup_volt_sensitive_regs(emif, emif->curr_regs, volt_state);
1701 }
1702
1703 /*
1704  * TODO: voltage notify handling should be hooked up to
1705  * regulator framework as soon as the necessary support
1706  * is available in mainline kernel. This function is un-used
1707  * right now.
1708  */
1709 static void __attribute__((unused)) volt_notify_handling(u32 volt_state)
1710 {
1711         struct emif_data *emif;
1712
1713         spin_lock_irqsave(&emif_lock, irq_state);
1714
1715         list_for_each_entry(emif, &device_list, node)
1716                 do_volt_notify_handling(emif, volt_state);
1717         do_freq_update();
1718
1719         spin_unlock_irqrestore(&emif_lock, irq_state);
1720 }
1721
1722 static void do_freq_pre_notify_handling(struct emif_data *emif, u32 new_freq)
1723 {
1724         struct emif_regs *regs;
1725
1726         regs = get_regs(emif, new_freq);
1727         if (!regs)
1728                 return;
1729
1730         emif->curr_regs = regs;
1731
1732         /*
1733          * Update the shadow registers:
1734          * Temperature and voltage-ramp sensitive settings are also configured
1735          * in terms of DDR cycles. So, we need to update them too when there
1736          * is a freq change
1737          */
1738         dev_dbg(emif->dev, "%s: setting up shadow registers for %uHz",
1739                 __func__, new_freq);
1740         setup_registers(emif, regs);
1741         setup_temperature_sensitive_regs(emif, regs);
1742         setup_volt_sensitive_regs(emif, regs, DDR_VOLTAGE_STABLE);
1743
1744         /*
1745          * Part of workaround for errata i728. See do_freq_update()
1746          * for more details
1747          */
1748         if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
1749                 set_lpmode(emif, EMIF_LP_MODE_DISABLE);
1750 }
1751
1752 /*
1753  * TODO: frequency notify handling should be hooked up to
1754  * clock framework as soon as the necessary support is
1755  * available in mainline kernel. This function is un-used
1756  * right now.
1757  */
1758 static void __attribute__((unused)) freq_pre_notify_handling(u32 new_freq)
1759 {
1760         struct emif_data *emif;
1761
1762         /*
1763          * NOTE: we are taking the spin-lock here and releases it
1764          * only in post-notifier. This doesn't look good and
1765          * Sparse complains about it, but this seems to be
1766          * un-avoidable. We need to lock a sequence of events
1767          * that is split between EMIF and clock framework.
1768          *
1769          * 1. EMIF driver updates EMIF timings in shadow registers in the
1770          *    frequency pre-notify callback from clock framework
1771          * 2. clock framework sets up the registers for the new frequency
1772          * 3. clock framework initiates a hw-sequence that updates
1773          *    the frequency EMIF timings synchronously.
1774          *
1775          * All these 3 steps should be performed as an atomic operation
1776          * vis-a-vis similar sequence in the EMIF interrupt handler
1777          * for temperature events. Otherwise, there could be race
1778          * conditions that could result in incorrect EMIF timings for
1779          * a given frequency
1780          */
1781         spin_lock_irqsave(&emif_lock, irq_state);
1782
1783         list_for_each_entry(emif, &device_list, node)
1784                 do_freq_pre_notify_handling(emif, new_freq);
1785 }
1786
1787 static void do_freq_post_notify_handling(struct emif_data *emif)
1788 {
1789         /*
1790          * Part of workaround for errata i728. See do_freq_update()
1791          * for more details
1792          */
1793         if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
1794                 set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
1795 }
1796
1797 /*
1798  * TODO: frequency notify handling should be hooked up to
1799  * clock framework as soon as the necessary support is
1800  * available in mainline kernel. This function is un-used
1801  * right now.
1802  */
1803 static void __attribute__((unused)) freq_post_notify_handling(void)
1804 {
1805         struct emif_data *emif;
1806
1807         list_for_each_entry(emif, &device_list, node)
1808                 do_freq_post_notify_handling(emif);
1809
1810         /*
1811          * Lock is done in pre-notify handler. See freq_pre_notify_handling()
1812          * for more details
1813          */
1814         spin_unlock_irqrestore(&emif_lock, irq_state);
1815 }
1816
1817 #if defined(CONFIG_OF)
1818 static const struct of_device_id emif_of_match[] = {
1819                 { .compatible = "ti,emif-4d" },
1820                 { .compatible = "ti,emif-4d5" },
1821                 {},
1822 };
1823 MODULE_DEVICE_TABLE(of, emif_of_match);
1824 #endif
1825
1826 static struct platform_driver emif_driver = {
1827         .remove         = __exit_p(emif_remove),
1828         .shutdown       = emif_shutdown,
1829         .driver = {
1830                 .name = "emif",
1831                 .of_match_table = of_match_ptr(emif_of_match),
1832         },
1833 };
1834
1835 static int __init_or_module emif_register(void)
1836 {
1837         return platform_driver_probe(&emif_driver, emif_probe);
1838 }
1839
1840 static void __exit emif_unregister(void)
1841 {
1842         platform_driver_unregister(&emif_driver);
1843 }
1844
1845 module_init(emif_register);
1846 module_exit(emif_unregister);
1847 MODULE_DESCRIPTION("TI EMIF SDRAM Controller Driver");
1848 MODULE_LICENSE("GPL");
1849 MODULE_ALIAS("platform:emif");
1850 MODULE_AUTHOR("Texas Instruments Inc");