4 * Copyright (C) 2012 Texas Instruments, Inc.
6 * Aneesh V <aneesh@ti.com>
7 * Santosh Shilimkar <santosh.shilimkar@ti.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/err.h>
14 #include <linux/kernel.h>
15 #include <linux/reboot.h>
16 #include <linux/platform_data/emif_plat.h>
18 #include <linux/device.h>
19 #include <linux/platform_device.h>
20 #include <linux/interrupt.h>
21 #include <linux/slab.h>
23 #include <linux/debugfs.h>
24 #include <linux/seq_file.h>
25 #include <linux/module.h>
26 #include <linux/list.h>
27 #include <linux/spinlock.h>
28 #include <memory/jedec_ddr.h>
30 #include "of_memory.h"
33 * struct emif_data - Per device static data for driver's use
34 * @duplicate: Whether the DDR devices attached to this EMIF
35 * instance are exactly same as that on EMIF1. In
36 * this case we can save some memory and processing
37 * @temperature_level: Maximum temperature of LPDDR2 devices attached
38 * to this EMIF - read from MR4 register. If there
39 * are two devices attached to this EMIF, this
40 * value is the maximum of the two temperature
42 * @node: node in the device list
43 * @base: base address of memory-mapped IO registers.
44 * @dev: device pointer.
45 * @addressing table with addressing information from the spec
46 * @regs_cache: An array of 'struct emif_regs' that stores
47 * calculated register values for different
48 * frequencies, to avoid re-calculating them on
49 * each DVFS transition.
50 * @curr_regs: The set of register values used in the last
51 * frequency change (i.e. corresponding to the
52 * frequency in effect at the moment)
53 * @plat_data: Pointer to saved platform data.
54 * @debugfs_root: dentry to the root folder for EMIF in debugfs
55 * @np_ddr: Pointer to ddr device tree node
61 struct list_head node;
62 unsigned long irq_state;
65 const struct lpddr2_addressing *addressing;
66 struct emif_regs *regs_cache[EMIF_MAX_NUM_FREQUENCIES];
67 struct emif_regs *curr_regs;
68 struct emif_platform_data *plat_data;
69 struct dentry *debugfs_root;
70 struct device_node *np_ddr;
73 static struct emif_data *emif1;
74 static spinlock_t emif_lock;
75 static unsigned long irq_state;
76 static u32 t_ck; /* DDR clock period in ps */
77 static LIST_HEAD(device_list);
79 #ifdef CONFIG_DEBUG_FS
80 static void do_emif_regdump_show(struct seq_file *s, struct emif_data *emif,
81 struct emif_regs *regs)
83 u32 type = emif->plat_data->device_info->type;
84 u32 ip_rev = emif->plat_data->ip_rev;
86 seq_printf(s, "EMIF register cache dump for %dMHz\n",
89 seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw);
90 seq_printf(s, "sdram_tim1_shdw\t: 0x%08x\n", regs->sdram_tim1_shdw);
91 seq_printf(s, "sdram_tim2_shdw\t: 0x%08x\n", regs->sdram_tim2_shdw);
92 seq_printf(s, "sdram_tim3_shdw\t: 0x%08x\n", regs->sdram_tim3_shdw);
94 if (ip_rev == EMIF_4D) {
95 seq_printf(s, "read_idle_ctrl_shdw_normal\t: 0x%08x\n",
96 regs->read_idle_ctrl_shdw_normal);
97 seq_printf(s, "read_idle_ctrl_shdw_volt_ramp\t: 0x%08x\n",
98 regs->read_idle_ctrl_shdw_volt_ramp);
99 } else if (ip_rev == EMIF_4D5) {
100 seq_printf(s, "dll_calib_ctrl_shdw_normal\t: 0x%08x\n",
101 regs->dll_calib_ctrl_shdw_normal);
102 seq_printf(s, "dll_calib_ctrl_shdw_volt_ramp\t: 0x%08x\n",
103 regs->dll_calib_ctrl_shdw_volt_ramp);
106 if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
107 seq_printf(s, "ref_ctrl_shdw_derated\t: 0x%08x\n",
108 regs->ref_ctrl_shdw_derated);
109 seq_printf(s, "sdram_tim1_shdw_derated\t: 0x%08x\n",
110 regs->sdram_tim1_shdw_derated);
111 seq_printf(s, "sdram_tim3_shdw_derated\t: 0x%08x\n",
112 regs->sdram_tim3_shdw_derated);
116 static int emif_regdump_show(struct seq_file *s, void *unused)
118 struct emif_data *emif = s->private;
119 struct emif_regs **regs_cache;
123 regs_cache = emif1->regs_cache;
125 regs_cache = emif->regs_cache;
127 for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
128 do_emif_regdump_show(s, emif, regs_cache[i]);
135 static int emif_regdump_open(struct inode *inode, struct file *file)
137 return single_open(file, emif_regdump_show, inode->i_private);
140 static const struct file_operations emif_regdump_fops = {
141 .open = emif_regdump_open,
143 .release = single_release,
146 static int emif_mr4_show(struct seq_file *s, void *unused)
148 struct emif_data *emif = s->private;
150 seq_printf(s, "MR4=%d\n", emif->temperature_level);
154 static int emif_mr4_open(struct inode *inode, struct file *file)
156 return single_open(file, emif_mr4_show, inode->i_private);
159 static const struct file_operations emif_mr4_fops = {
160 .open = emif_mr4_open,
162 .release = single_release,
165 static int __init_or_module emif_debugfs_init(struct emif_data *emif)
167 struct dentry *dentry;
170 dentry = debugfs_create_dir(dev_name(emif->dev), NULL);
175 emif->debugfs_root = dentry;
177 dentry = debugfs_create_file("regcache_dump", S_IRUGO,
178 emif->debugfs_root, emif, &emif_regdump_fops);
184 dentry = debugfs_create_file("mr4", S_IRUGO,
185 emif->debugfs_root, emif, &emif_mr4_fops);
193 debugfs_remove_recursive(emif->debugfs_root);
198 static void __exit emif_debugfs_exit(struct emif_data *emif)
200 debugfs_remove_recursive(emif->debugfs_root);
201 emif->debugfs_root = NULL;
204 static inline int __init_or_module emif_debugfs_init(struct emif_data *emif)
209 static inline void __exit emif_debugfs_exit(struct emif_data *emif)
215 * Calculate the period of DDR clock from frequency value
217 static void set_ddr_clk_period(u32 freq)
219 /* Divide 10^12 by frequency to get period in ps */
220 t_ck = (u32)DIV_ROUND_UP_ULL(1000000000000ull, freq);
224 * Get bus width used by EMIF. Note that this may be different from the
225 * bus width of the DDR devices used. For instance two 16-bit DDR devices
226 * may be connected to a given CS of EMIF. In this case bus width as far
227 * as EMIF is concerned is 32, where as the DDR bus width is 16 bits.
229 static u32 get_emif_bus_width(struct emif_data *emif)
232 void __iomem *base = emif->base;
234 width = (readl(base + EMIF_SDRAM_CONFIG) & NARROW_MODE_MASK)
235 >> NARROW_MODE_SHIFT;
236 width = width == 0 ? 32 : 16;
242 * Get the CL from SDRAM_CONFIG register
244 static u32 get_cl(struct emif_data *emif)
247 void __iomem *base = emif->base;
249 cl = (readl(base + EMIF_SDRAM_CONFIG) & CL_MASK) >> CL_SHIFT;
254 static void set_lpmode(struct emif_data *emif, u8 lpmode)
257 void __iomem *base = emif->base;
259 temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL);
260 temp &= ~LP_MODE_MASK;
261 temp |= (lpmode << LP_MODE_SHIFT);
262 writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL);
265 static void do_freq_update(void)
267 struct emif_data *emif;
270 * Workaround for errata i728: Disable LPMODE during FREQ_UPDATE
273 * The EMIF automatically puts the SDRAM into self-refresh mode
274 * after the EMIF has not performed accesses during
275 * EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM number of DDR clock cycles
276 * and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set
277 * to 0x2. If during a small window the following three events
279 * - The SR_TIMING counter expires
280 * - And frequency change is requested
281 * - And OCP access is requested
282 * Then it causes instable clock on the DDR interface.
285 * To avoid the occurrence of the three events, the workaround
286 * is to disable the self-refresh when requesting a frequency
287 * change. Before requesting a frequency change the software must
288 * program EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x0. When the
289 * frequency change has been done, the software can reprogram
290 * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2
292 list_for_each_entry(emif, &device_list, node) {
293 if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
294 set_lpmode(emif, EMIF_LP_MODE_DISABLE);
298 * TODO: Do FREQ_UPDATE here when an API
299 * is available for this as part of the new
303 list_for_each_entry(emif, &device_list, node) {
304 if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
305 set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
309 /* Find addressing table entry based on the device's type and density */
310 static const struct lpddr2_addressing *get_addressing_table(
311 const struct ddr_device_info *device_info)
313 u32 index, type, density;
315 type = device_info->type;
316 density = device_info->density;
319 case DDR_TYPE_LPDDR2_S4:
322 case DDR_TYPE_LPDDR2_S2:
324 case DDR_DENSITY_1Gb:
325 case DDR_DENSITY_2Gb:
336 return &lpddr2_jedec_addressing_table[index];
340 * Find the the right timing table from the array of timing
341 * tables of the device using DDR clock frequency
343 static const struct lpddr2_timings *get_timings_table(struct emif_data *emif,
346 u32 i, min, max, freq_nearest;
347 const struct lpddr2_timings *timings = NULL;
348 const struct lpddr2_timings *timings_arr = emif->plat_data->timings;
349 struct device *dev = emif->dev;
351 /* Start with a very high frequency - 1GHz */
352 freq_nearest = 1000000000;
355 * Find the timings table such that:
356 * 1. the frequency range covers the required frequency(safe) AND
357 * 2. the max_freq is closest to the required frequency(optimal)
359 for (i = 0; i < emif->plat_data->timings_arr_size; i++) {
360 max = timings_arr[i].max_freq;
361 min = timings_arr[i].min_freq;
362 if ((freq >= min) && (freq <= max) && (max < freq_nearest)) {
364 timings = &timings_arr[i];
369 dev_err(dev, "%s: couldn't find timings for - %dHz\n",
372 dev_dbg(dev, "%s: timings table: freq %d, speed bin freq %d\n",
373 __func__, freq, freq_nearest);
378 static u32 get_sdram_ref_ctrl_shdw(u32 freq,
379 const struct lpddr2_addressing *addressing)
381 u32 ref_ctrl_shdw = 0, val = 0, freq_khz, t_refi;
383 /* Scale down frequency and t_refi to avoid overflow */
384 freq_khz = freq / 1000;
385 t_refi = addressing->tREFI_ns / 100;
388 * refresh rate to be set is 'tREFI(in us) * freq in MHz
389 * division by 10000 to account for change in units
391 val = t_refi * freq_khz / 10000;
392 ref_ctrl_shdw |= val << REFRESH_RATE_SHIFT;
394 return ref_ctrl_shdw;
397 static u32 get_sdram_tim_1_shdw(const struct lpddr2_timings *timings,
398 const struct lpddr2_min_tck *min_tck,
399 const struct lpddr2_addressing *addressing)
401 u32 tim1 = 0, val = 0;
403 val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
404 tim1 |= val << T_WTR_SHIFT;
406 if (addressing->num_banks == B8)
407 val = DIV_ROUND_UP(timings->tFAW, t_ck*4);
409 val = max(min_tck->tRRD, DIV_ROUND_UP(timings->tRRD, t_ck));
410 tim1 |= (val - 1) << T_RRD_SHIFT;
412 val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab, t_ck) - 1;
413 tim1 |= val << T_RC_SHIFT;
415 val = max(min_tck->tRASmin, DIV_ROUND_UP(timings->tRAS_min, t_ck));
416 tim1 |= (val - 1) << T_RAS_SHIFT;
418 val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
419 tim1 |= val << T_WR_SHIFT;
421 val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD, t_ck)) - 1;
422 tim1 |= val << T_RCD_SHIFT;
424 val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab, t_ck)) - 1;
425 tim1 |= val << T_RP_SHIFT;
430 static u32 get_sdram_tim_1_shdw_derated(const struct lpddr2_timings *timings,
431 const struct lpddr2_min_tck *min_tck,
432 const struct lpddr2_addressing *addressing)
434 u32 tim1 = 0, val = 0;
436 val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
437 tim1 = val << T_WTR_SHIFT;
440 * tFAW is approximately 4 times tRRD. So add 1875*4 = 7500ps
441 * to tFAW for de-rating
443 if (addressing->num_banks == B8) {
444 val = DIV_ROUND_UP(timings->tFAW + 7500, 4 * t_ck) - 1;
446 val = DIV_ROUND_UP(timings->tRRD + 1875, t_ck);
447 val = max(min_tck->tRRD, val) - 1;
449 tim1 |= val << T_RRD_SHIFT;
451 val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab + 1875, t_ck);
452 tim1 |= (val - 1) << T_RC_SHIFT;
454 val = DIV_ROUND_UP(timings->tRAS_min + 1875, t_ck);
455 val = max(min_tck->tRASmin, val) - 1;
456 tim1 |= val << T_RAS_SHIFT;
458 val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
459 tim1 |= val << T_WR_SHIFT;
461 val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD + 1875, t_ck));
462 tim1 |= (val - 1) << T_RCD_SHIFT;
464 val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab + 1875, t_ck));
465 tim1 |= (val - 1) << T_RP_SHIFT;
470 static u32 get_sdram_tim_2_shdw(const struct lpddr2_timings *timings,
471 const struct lpddr2_min_tck *min_tck,
472 const struct lpddr2_addressing *addressing,
475 u32 tim2 = 0, val = 0;
477 val = min_tck->tCKE - 1;
478 tim2 |= val << T_CKE_SHIFT;
480 val = max(min_tck->tRTP, DIV_ROUND_UP(timings->tRTP, t_ck)) - 1;
481 tim2 |= val << T_RTP_SHIFT;
483 /* tXSNR = tRFCab_ps + 10 ns(tRFCab_ps for LPDDR2). */
484 val = DIV_ROUND_UP(addressing->tRFCab_ps + 10000, t_ck) - 1;
485 tim2 |= val << T_XSNR_SHIFT;
487 /* XSRD same as XSNR for LPDDR2 */
488 tim2 |= val << T_XSRD_SHIFT;
490 val = max(min_tck->tXP, DIV_ROUND_UP(timings->tXP, t_ck)) - 1;
491 tim2 |= val << T_XP_SHIFT;
496 static u32 get_sdram_tim_3_shdw(const struct lpddr2_timings *timings,
497 const struct lpddr2_min_tck *min_tck,
498 const struct lpddr2_addressing *addressing,
499 u32 type, u32 ip_rev, u32 derated)
501 u32 tim3 = 0, val = 0, t_dqsck;
503 val = timings->tRAS_max_ns / addressing->tREFI_ns - 1;
504 val = val > 0xF ? 0xF : val;
505 tim3 |= val << T_RAS_MAX_SHIFT;
507 val = DIV_ROUND_UP(addressing->tRFCab_ps, t_ck) - 1;
508 tim3 |= val << T_RFC_SHIFT;
510 t_dqsck = (derated == EMIF_DERATED_TIMINGS) ?
511 timings->tDQSCK_max_derated : timings->tDQSCK_max;
512 if (ip_rev == EMIF_4D5)
513 val = DIV_ROUND_UP(t_dqsck + 1000, t_ck) - 1;
515 val = DIV_ROUND_UP(t_dqsck, t_ck) - 1;
517 tim3 |= val << T_TDQSCKMAX_SHIFT;
519 val = DIV_ROUND_UP(timings->tZQCS, t_ck) - 1;
520 tim3 |= val << ZQ_ZQCS_SHIFT;
522 val = DIV_ROUND_UP(timings->tCKESR, t_ck);
523 val = max(min_tck->tCKESR, val) - 1;
524 tim3 |= val << T_CKESR_SHIFT;
526 if (ip_rev == EMIF_4D5) {
527 tim3 |= (EMIF_T_CSTA - 1) << T_CSTA_SHIFT;
529 val = DIV_ROUND_UP(EMIF_T_PDLL_UL, 128) - 1;
530 tim3 |= val << T_PDLL_UL_SHIFT;
536 static u32 get_zq_config_reg(const struct lpddr2_addressing *addressing,
537 bool cs1_used, bool cal_resistors_per_cs)
541 val = EMIF_ZQCS_INTERVAL_US * 1000 / addressing->tREFI_ns;
542 zq |= val << ZQ_REFINTERVAL_SHIFT;
544 val = DIV_ROUND_UP(T_ZQCL_DEFAULT_NS, T_ZQCS_DEFAULT_NS) - 1;
545 zq |= val << ZQ_ZQCL_MULT_SHIFT;
547 val = DIV_ROUND_UP(T_ZQINIT_DEFAULT_NS, T_ZQCL_DEFAULT_NS) - 1;
548 zq |= val << ZQ_ZQINIT_MULT_SHIFT;
550 zq |= ZQ_SFEXITEN_ENABLE << ZQ_SFEXITEN_SHIFT;
552 if (cal_resistors_per_cs)
553 zq |= ZQ_DUALCALEN_ENABLE << ZQ_DUALCALEN_SHIFT;
555 zq |= ZQ_DUALCALEN_DISABLE << ZQ_DUALCALEN_SHIFT;
557 zq |= ZQ_CS0EN_MASK; /* CS0 is used for sure */
559 val = cs1_used ? 1 : 0;
560 zq |= val << ZQ_CS1EN_SHIFT;
565 static u32 get_temp_alert_config(const struct lpddr2_addressing *addressing,
566 const struct emif_custom_configs *custom_configs, bool cs1_used,
567 u32 sdram_io_width, u32 emif_bus_width)
569 u32 alert = 0, interval, devcnt;
571 if (custom_configs && (custom_configs->mask &
572 EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL))
573 interval = custom_configs->temp_alert_poll_interval_ms;
575 interval = TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS;
577 interval *= 1000000; /* Convert to ns */
578 interval /= addressing->tREFI_ns; /* Convert to refresh cycles */
579 alert |= (interval << TA_REFINTERVAL_SHIFT);
582 * sdram_io_width is in 'log2(x) - 1' form. Convert emif_bus_width
583 * also to this form and subtract to get TA_DEVCNT, which is
586 emif_bus_width = __fls(emif_bus_width) - 1;
587 devcnt = emif_bus_width - sdram_io_width;
588 alert |= devcnt << TA_DEVCNT_SHIFT;
590 /* DEVWDT is in 'log2(x) - 3' form */
591 alert |= (sdram_io_width - 2) << TA_DEVWDT_SHIFT;
593 alert |= 1 << TA_SFEXITEN_SHIFT;
594 alert |= 1 << TA_CS0EN_SHIFT;
595 alert |= (cs1_used ? 1 : 0) << TA_CS1EN_SHIFT;
600 static u32 get_read_idle_ctrl_shdw(u8 volt_ramp)
602 u32 idle = 0, val = 0;
605 * Maximum value in normal conditions and increased frequency
606 * when voltage is ramping
609 val = READ_IDLE_INTERVAL_DVFS / t_ck / 64 - 1;
614 * READ_IDLE_CTRL register in EMIF4D has same offset and fields
615 * as DLL_CALIB_CTRL in EMIF4D5, so use the same shifts
617 idle |= val << DLL_CALIB_INTERVAL_SHIFT;
618 idle |= EMIF_READ_IDLE_LEN_VAL << ACK_WAIT_SHIFT;
623 static u32 get_dll_calib_ctrl_shdw(u8 volt_ramp)
625 u32 calib = 0, val = 0;
627 if (volt_ramp == DDR_VOLTAGE_RAMPING)
628 val = DLL_CALIB_INTERVAL_DVFS / t_ck / 16 - 1;
630 val = 0; /* Disabled when voltage is stable */
632 calib |= val << DLL_CALIB_INTERVAL_SHIFT;
633 calib |= DLL_CALIB_ACK_WAIT_VAL << ACK_WAIT_SHIFT;
638 static u32 get_ddr_phy_ctrl_1_attilaphy_4d(const struct lpddr2_timings *timings,
641 u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY, val = 0;
643 val = RL + DIV_ROUND_UP(timings->tDQSCK_max, t_ck) - 1;
644 phy |= val << READ_LATENCY_SHIFT_4D;
646 if (freq <= 100000000)
647 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY;
648 else if (freq <= 200000000)
649 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY;
651 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY;
653 phy |= val << DLL_SLAVE_DLY_CTRL_SHIFT_4D;
658 static u32 get_phy_ctrl_1_intelliphy_4d5(u32 freq, u8 cl)
660 u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY, half_delay;
663 * DLL operates at 266 MHz. If DDR frequency is near 266 MHz,
664 * half-delay is not needed else set half-delay
666 if (freq >= 265000000 && freq < 267000000)
671 phy |= half_delay << DLL_HALF_DELAY_SHIFT_4D5;
672 phy |= ((cl + DIV_ROUND_UP(EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS,
673 t_ck) - 1) << READ_LATENCY_SHIFT_4D5);
678 static u32 get_ext_phy_ctrl_2_intelliphy_4d5(void)
680 u32 fifo_we_slave_ratio;
682 fifo_we_slave_ratio = DIV_ROUND_CLOSEST(
683 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
685 return fifo_we_slave_ratio | fifo_we_slave_ratio << 11 |
686 fifo_we_slave_ratio << 22;
689 static u32 get_ext_phy_ctrl_3_intelliphy_4d5(void)
691 u32 fifo_we_slave_ratio;
693 fifo_we_slave_ratio = DIV_ROUND_CLOSEST(
694 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
696 return fifo_we_slave_ratio >> 10 | fifo_we_slave_ratio << 1 |
697 fifo_we_slave_ratio << 12 | fifo_we_slave_ratio << 23;
700 static u32 get_ext_phy_ctrl_4_intelliphy_4d5(void)
702 u32 fifo_we_slave_ratio;
704 fifo_we_slave_ratio = DIV_ROUND_CLOSEST(
705 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
707 return fifo_we_slave_ratio >> 9 | fifo_we_slave_ratio << 2 |
708 fifo_we_slave_ratio << 13;
711 static u32 get_pwr_mgmt_ctrl(u32 freq, struct emif_data *emif, u32 ip_rev)
713 u32 pwr_mgmt_ctrl = 0, timeout;
714 u32 lpmode = EMIF_LP_MODE_SELF_REFRESH;
715 u32 timeout_perf = EMIF_LP_MODE_TIMEOUT_PERFORMANCE;
716 u32 timeout_pwr = EMIF_LP_MODE_TIMEOUT_POWER;
717 u32 freq_threshold = EMIF_LP_MODE_FREQ_THRESHOLD;
721 struct emif_custom_configs *cust_cfgs = emif->plat_data->custom_configs;
723 if (cust_cfgs && (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE)) {
724 lpmode = cust_cfgs->lpmode;
725 timeout_perf = cust_cfgs->lpmode_timeout_performance;
726 timeout_pwr = cust_cfgs->lpmode_timeout_power;
727 freq_threshold = cust_cfgs->lpmode_freq_threshold;
730 /* Timeout based on DDR frequency */
731 timeout = freq >= freq_threshold ? timeout_perf : timeout_pwr;
734 * The value to be set in register is "log2(timeout) - 3"
735 * if timeout < 16 load 0 in register
736 * if timeout is not a power of 2, round to next highest power of 2
741 if (timeout & (timeout - 1))
743 timeout = __fls(timeout) - 3;
747 case EMIF_LP_MODE_CLOCK_STOP:
748 shift = CS_TIM_SHIFT;
751 case EMIF_LP_MODE_SELF_REFRESH:
752 /* Workaround for errata i735 */
756 shift = SR_TIM_SHIFT;
759 case EMIF_LP_MODE_PWR_DN:
760 shift = PD_TIM_SHIFT;
763 case EMIF_LP_MODE_DISABLE:
769 /* Round to maximum in case of overflow, BUT warn! */
770 if (lpmode != EMIF_LP_MODE_DISABLE && timeout > mask >> shift) {
771 pr_err("TIMEOUT Overflow - lpmode=%d perf=%d pwr=%d freq=%d\n",
776 WARN(1, "timeout=0x%02x greater than 0x%02x. Using max\n",
777 timeout, mask >> shift);
778 timeout = mask >> shift;
781 /* Setup required timing */
782 pwr_mgmt_ctrl = (timeout << shift) & mask;
783 /* setup a default mask for rest of the modes */
784 pwr_mgmt_ctrl |= (SR_TIM_MASK | CS_TIM_MASK | PD_TIM_MASK) &
787 /* No CS_TIM in EMIF_4D5 */
788 if (ip_rev == EMIF_4D5)
789 pwr_mgmt_ctrl &= ~CS_TIM_MASK;
791 pwr_mgmt_ctrl |= lpmode << LP_MODE_SHIFT;
793 return pwr_mgmt_ctrl;
797 * Get the temperature level of the EMIF instance:
798 * Reads the MR4 register of attached SDRAM parts to find out the temperature
799 * level. If there are two parts attached(one on each CS), then the temperature
800 * level for the EMIF instance is the higher of the two temperatures.
802 static void get_temperature_level(struct emif_data *emif)
804 u32 temp, temperature_level;
809 /* Read mode register 4 */
810 writel(DDR_MR4, base + EMIF_LPDDR2_MODE_REG_CONFIG);
811 temperature_level = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
812 temperature_level = (temperature_level & MR4_SDRAM_REF_RATE_MASK) >>
813 MR4_SDRAM_REF_RATE_SHIFT;
815 if (emif->plat_data->device_info->cs1_used) {
816 writel(DDR_MR4 | CS_MASK, base + EMIF_LPDDR2_MODE_REG_CONFIG);
817 temp = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
818 temp = (temp & MR4_SDRAM_REF_RATE_MASK)
819 >> MR4_SDRAM_REF_RATE_SHIFT;
820 temperature_level = max(temp, temperature_level);
823 /* treat everything less than nominal(3) in MR4 as nominal */
824 if (unlikely(temperature_level < SDRAM_TEMP_NOMINAL))
825 temperature_level = SDRAM_TEMP_NOMINAL;
827 /* if we get reserved value in MR4 persist with the existing value */
828 if (likely(temperature_level != SDRAM_TEMP_RESERVED_4))
829 emif->temperature_level = temperature_level;
833 * Program EMIF shadow registers that are not dependent on temperature
836 static void setup_registers(struct emif_data *emif, struct emif_regs *regs)
838 void __iomem *base = emif->base;
840 writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW);
841 writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW);
842 writel(regs->pwr_mgmt_ctrl_shdw,
843 base + EMIF_POWER_MANAGEMENT_CTRL_SHDW);
845 /* Settings specific for EMIF4D5 */
846 if (emif->plat_data->ip_rev != EMIF_4D5)
848 writel(regs->ext_phy_ctrl_2_shdw, base + EMIF_EXT_PHY_CTRL_2_SHDW);
849 writel(regs->ext_phy_ctrl_3_shdw, base + EMIF_EXT_PHY_CTRL_3_SHDW);
850 writel(regs->ext_phy_ctrl_4_shdw, base + EMIF_EXT_PHY_CTRL_4_SHDW);
854 * When voltage ramps dll calibration and forced read idle should
857 static void setup_volt_sensitive_regs(struct emif_data *emif,
858 struct emif_regs *regs, u32 volt_state)
861 void __iomem *base = emif->base;
864 * EMIF_READ_IDLE_CTRL in EMIF4D refers to the same register as
865 * EMIF_DLL_CALIB_CTRL in EMIF4D5 and dll_calib_ctrl_shadow_*
866 * is an alias of the respective read_idle_ctrl_shdw_* (members of
867 * a union). So, the below code takes care of both cases
869 if (volt_state == DDR_VOLTAGE_RAMPING)
870 calib_ctrl = regs->dll_calib_ctrl_shdw_volt_ramp;
872 calib_ctrl = regs->dll_calib_ctrl_shdw_normal;
874 writel(calib_ctrl, base + EMIF_DLL_CALIB_CTRL_SHDW);
878 * setup_temperature_sensitive_regs() - set the timings for temperature
879 * sensitive registers. This happens once at initialisation time based
880 * on the temperature at boot time and subsequently based on the temperature
881 * alert interrupt. Temperature alert can happen when the temperature
882 * increases or drops. So this function can have the effect of either
883 * derating the timings or going back to nominal values.
885 static void setup_temperature_sensitive_regs(struct emif_data *emif,
886 struct emif_regs *regs)
888 u32 tim1, tim3, ref_ctrl, type;
889 void __iomem *base = emif->base;
892 type = emif->plat_data->device_info->type;
894 tim1 = regs->sdram_tim1_shdw;
895 tim3 = regs->sdram_tim3_shdw;
896 ref_ctrl = regs->ref_ctrl_shdw;
898 /* No de-rating for non-lpddr2 devices */
899 if (type != DDR_TYPE_LPDDR2_S2 && type != DDR_TYPE_LPDDR2_S4)
902 temperature = emif->temperature_level;
903 if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH) {
904 ref_ctrl = regs->ref_ctrl_shdw_derated;
905 } else if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS) {
906 tim1 = regs->sdram_tim1_shdw_derated;
907 tim3 = regs->sdram_tim3_shdw_derated;
908 ref_ctrl = regs->ref_ctrl_shdw_derated;
912 writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW);
913 writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW);
914 writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW);
917 static irqreturn_t handle_temp_alert(void __iomem *base, struct emif_data *emif)
920 irqreturn_t ret = IRQ_HANDLED;
921 struct emif_custom_configs *custom_configs;
923 spin_lock_irqsave(&emif_lock, irq_state);
924 old_temp_level = emif->temperature_level;
925 get_temperature_level(emif);
927 if (unlikely(emif->temperature_level == old_temp_level)) {
929 } else if (!emif->curr_regs) {
930 dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
934 custom_configs = emif->plat_data->custom_configs;
937 * IF we detect higher than "nominal rating" from DDR sensor
938 * on an unsupported DDR part, shutdown system
940 if (custom_configs && !(custom_configs->mask &
941 EMIF_CUSTOM_CONFIG_EXTENDED_TEMP_PART)) {
942 if (emif->temperature_level >= SDRAM_TEMP_HIGH_DERATE_REFRESH) {
944 "%s:NOT Extended temperature capable memory."
945 "Converting MR4=0x%02x as shutdown event\n",
946 __func__, emif->temperature_level);
948 * Temperature far too high - do kernel_power_off()
949 * from thread context
951 emif->temperature_level = SDRAM_TEMP_VERY_HIGH_SHUTDOWN;
952 ret = IRQ_WAKE_THREAD;
957 if (emif->temperature_level < old_temp_level ||
958 emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
960 * Temperature coming down - defer handling to thread OR
961 * Temperature far too high - do kernel_power_off() from
964 ret = IRQ_WAKE_THREAD;
966 /* Temperature is going up - handle immediately */
967 setup_temperature_sensitive_regs(emif, emif->curr_regs);
972 spin_unlock_irqrestore(&emif_lock, irq_state);
976 static irqreturn_t emif_interrupt_handler(int irq, void *dev_id)
979 struct emif_data *emif = dev_id;
980 void __iomem *base = emif->base;
981 struct device *dev = emif->dev;
982 irqreturn_t ret = IRQ_HANDLED;
984 /* Save the status and clear it */
985 interrupts = readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
986 writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
989 * Handle temperature alert
990 * Temperature alert should be same for all ports
991 * So, it's enough to process it only for one of the ports
993 if (interrupts & TA_SYS_MASK)
994 ret = handle_temp_alert(base, emif);
996 if (interrupts & ERR_SYS_MASK)
997 dev_err(dev, "Access error from SYS port - %x\n", interrupts);
999 if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
1000 /* Save the status and clear it */
1001 interrupts = readl(base + EMIF_LL_OCP_INTERRUPT_STATUS);
1002 writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_STATUS);
1004 if (interrupts & ERR_LL_MASK)
1005 dev_err(dev, "Access error from LL port - %x\n",
1012 static irqreturn_t emif_threaded_isr(int irq, void *dev_id)
1014 struct emif_data *emif = dev_id;
1016 if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
1017 dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
1022 spin_lock_irqsave(&emif_lock, irq_state);
1024 if (emif->curr_regs) {
1025 setup_temperature_sensitive_regs(emif, emif->curr_regs);
1028 dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
1031 spin_unlock_irqrestore(&emif_lock, irq_state);
1036 static void clear_all_interrupts(struct emif_data *emif)
1038 void __iomem *base = emif->base;
1040 writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS),
1041 base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
1042 if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
1043 writel(readl(base + EMIF_LL_OCP_INTERRUPT_STATUS),
1044 base + EMIF_LL_OCP_INTERRUPT_STATUS);
1047 static void disable_and_clear_all_interrupts(struct emif_data *emif)
1049 void __iomem *base = emif->base;
1051 /* Disable all interrupts */
1052 writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET),
1053 base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR);
1054 if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
1055 writel(readl(base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET),
1056 base + EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR);
1058 /* Clear all interrupts */
1059 clear_all_interrupts(emif);
1062 static int __init_or_module setup_interrupts(struct emif_data *emif, u32 irq)
1064 u32 interrupts, type;
1065 void __iomem *base = emif->base;
1067 type = emif->plat_data->device_info->type;
1069 clear_all_interrupts(emif);
1071 /* Enable interrupts for SYS interface */
1072 interrupts = EN_ERR_SYS_MASK;
1073 if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4)
1074 interrupts |= EN_TA_SYS_MASK;
1075 writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET);
1077 /* Enable interrupts for LL interface */
1078 if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
1079 /* TA need not be enabled for LL */
1080 interrupts = EN_ERR_LL_MASK;
1081 writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET);
1084 /* setup IRQ handlers */
1085 return devm_request_threaded_irq(emif->dev, irq,
1086 emif_interrupt_handler,
1088 0, dev_name(emif->dev),
1093 static void __init_or_module emif_onetime_settings(struct emif_data *emif)
1095 u32 pwr_mgmt_ctrl, zq, temp_alert_cfg;
1096 void __iomem *base = emif->base;
1097 const struct lpddr2_addressing *addressing;
1098 const struct ddr_device_info *device_info;
1100 device_info = emif->plat_data->device_info;
1101 addressing = get_addressing_table(device_info);
1104 * Init power management settings
1105 * We don't know the frequency yet. Use a high frequency
1106 * value for a conservative timeout setting
1108 pwr_mgmt_ctrl = get_pwr_mgmt_ctrl(1000000000, emif,
1109 emif->plat_data->ip_rev);
1110 emif->lpmode = (pwr_mgmt_ctrl & LP_MODE_MASK) >> LP_MODE_SHIFT;
1111 writel(pwr_mgmt_ctrl, base + EMIF_POWER_MANAGEMENT_CONTROL);
1113 /* Init ZQ calibration settings */
1114 zq = get_zq_config_reg(addressing, device_info->cs1_used,
1115 device_info->cal_resistors_per_cs);
1116 writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG);
1118 /* Check temperature level temperature level*/
1119 get_temperature_level(emif);
1120 if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN)
1121 dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
1123 /* Init temperature polling */
1124 temp_alert_cfg = get_temp_alert_config(addressing,
1125 emif->plat_data->custom_configs, device_info->cs1_used,
1126 device_info->io_width, get_emif_bus_width(emif));
1127 writel(temp_alert_cfg, base + EMIF_TEMPERATURE_ALERT_CONFIG);
1130 * Program external PHY control registers that are not frequency
1133 if (emif->plat_data->phy_type != EMIF_PHY_TYPE_INTELLIPHY)
1135 writel(EMIF_EXT_PHY_CTRL_1_VAL, base + EMIF_EXT_PHY_CTRL_1_SHDW);
1136 writel(EMIF_EXT_PHY_CTRL_5_VAL, base + EMIF_EXT_PHY_CTRL_5_SHDW);
1137 writel(EMIF_EXT_PHY_CTRL_6_VAL, base + EMIF_EXT_PHY_CTRL_6_SHDW);
1138 writel(EMIF_EXT_PHY_CTRL_7_VAL, base + EMIF_EXT_PHY_CTRL_7_SHDW);
1139 writel(EMIF_EXT_PHY_CTRL_8_VAL, base + EMIF_EXT_PHY_CTRL_8_SHDW);
1140 writel(EMIF_EXT_PHY_CTRL_9_VAL, base + EMIF_EXT_PHY_CTRL_9_SHDW);
1141 writel(EMIF_EXT_PHY_CTRL_10_VAL, base + EMIF_EXT_PHY_CTRL_10_SHDW);
1142 writel(EMIF_EXT_PHY_CTRL_11_VAL, base + EMIF_EXT_PHY_CTRL_11_SHDW);
1143 writel(EMIF_EXT_PHY_CTRL_12_VAL, base + EMIF_EXT_PHY_CTRL_12_SHDW);
1144 writel(EMIF_EXT_PHY_CTRL_13_VAL, base + EMIF_EXT_PHY_CTRL_13_SHDW);
1145 writel(EMIF_EXT_PHY_CTRL_14_VAL, base + EMIF_EXT_PHY_CTRL_14_SHDW);
1146 writel(EMIF_EXT_PHY_CTRL_15_VAL, base + EMIF_EXT_PHY_CTRL_15_SHDW);
1147 writel(EMIF_EXT_PHY_CTRL_16_VAL, base + EMIF_EXT_PHY_CTRL_16_SHDW);
1148 writel(EMIF_EXT_PHY_CTRL_17_VAL, base + EMIF_EXT_PHY_CTRL_17_SHDW);
1149 writel(EMIF_EXT_PHY_CTRL_18_VAL, base + EMIF_EXT_PHY_CTRL_18_SHDW);
1150 writel(EMIF_EXT_PHY_CTRL_19_VAL, base + EMIF_EXT_PHY_CTRL_19_SHDW);
1151 writel(EMIF_EXT_PHY_CTRL_20_VAL, base + EMIF_EXT_PHY_CTRL_20_SHDW);
1152 writel(EMIF_EXT_PHY_CTRL_21_VAL, base + EMIF_EXT_PHY_CTRL_21_SHDW);
1153 writel(EMIF_EXT_PHY_CTRL_22_VAL, base + EMIF_EXT_PHY_CTRL_22_SHDW);
1154 writel(EMIF_EXT_PHY_CTRL_23_VAL, base + EMIF_EXT_PHY_CTRL_23_SHDW);
1155 writel(EMIF_EXT_PHY_CTRL_24_VAL, base + EMIF_EXT_PHY_CTRL_24_SHDW);
1158 static void get_default_timings(struct emif_data *emif)
1160 struct emif_platform_data *pd = emif->plat_data;
1162 pd->timings = lpddr2_jedec_timings;
1163 pd->timings_arr_size = ARRAY_SIZE(lpddr2_jedec_timings);
1165 dev_warn(emif->dev, "%s: using default timings\n", __func__);
1168 static int is_dev_data_valid(u32 type, u32 density, u32 io_width, u32 phy_type,
1169 u32 ip_rev, struct device *dev)
1173 valid = (type == DDR_TYPE_LPDDR2_S4 ||
1174 type == DDR_TYPE_LPDDR2_S2)
1175 && (density >= DDR_DENSITY_64Mb
1176 && density <= DDR_DENSITY_8Gb)
1177 && (io_width >= DDR_IO_WIDTH_8
1178 && io_width <= DDR_IO_WIDTH_32);
1180 /* Combinations of EMIF and PHY revisions that we support today */
1183 valid = valid && (phy_type == EMIF_PHY_TYPE_ATTILAPHY);
1186 valid = valid && (phy_type == EMIF_PHY_TYPE_INTELLIPHY);
1193 dev_err(dev, "%s: invalid DDR details\n", __func__);
1197 static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs,
1202 if ((cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE) &&
1203 (cust_cfgs->lpmode != EMIF_LP_MODE_DISABLE))
1204 valid = cust_cfgs->lpmode_freq_threshold &&
1205 cust_cfgs->lpmode_timeout_performance &&
1206 cust_cfgs->lpmode_timeout_power;
1208 if (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL)
1209 valid = valid && cust_cfgs->temp_alert_poll_interval_ms;
1212 dev_warn(dev, "%s: invalid custom configs\n", __func__);
1217 #if defined(CONFIG_OF)
1218 static void __init_or_module of_get_custom_configs(struct device_node *np_emif,
1219 struct emif_data *emif)
1221 struct emif_custom_configs *cust_cfgs = NULL;
1223 const int *lpmode, *poll_intvl;
1225 lpmode = of_get_property(np_emif, "low-power-mode", &len);
1226 poll_intvl = of_get_property(np_emif, "temp-alert-poll-interval", &len);
1228 if (lpmode || poll_intvl)
1229 cust_cfgs = devm_kzalloc(emif->dev, sizeof(*cust_cfgs),
1236 cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_LPMODE;
1237 cust_cfgs->lpmode = *lpmode;
1238 of_property_read_u32(np_emif,
1239 "low-power-mode-timeout-performance",
1240 &cust_cfgs->lpmode_timeout_performance);
1241 of_property_read_u32(np_emif,
1242 "low-power-mode-timeout-power",
1243 &cust_cfgs->lpmode_timeout_power);
1244 of_property_read_u32(np_emif,
1245 "low-power-mode-freq-threshold",
1246 &cust_cfgs->lpmode_freq_threshold);
1251 EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL;
1252 cust_cfgs->temp_alert_poll_interval_ms = *poll_intvl;
1255 if (of_find_property(np_emif, "extended-temp-part", &len))
1256 cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_EXTENDED_TEMP_PART;
1258 if (!is_custom_config_valid(cust_cfgs, emif->dev)) {
1259 devm_kfree(emif->dev, cust_cfgs);
1263 emif->plat_data->custom_configs = cust_cfgs;
1266 static void __init_or_module of_get_ddr_info(struct device_node *np_emif,
1267 struct device_node *np_ddr,
1268 struct ddr_device_info *dev_info)
1270 u32 density = 0, io_width = 0;
1273 if (of_find_property(np_emif, "cs1-used", &len))
1274 dev_info->cs1_used = true;
1276 if (of_find_property(np_emif, "cal-resistor-per-cs", &len))
1277 dev_info->cal_resistors_per_cs = true;
1279 if (of_device_is_compatible(np_ddr , "jedec,lpddr2-s4"))
1280 dev_info->type = DDR_TYPE_LPDDR2_S4;
1281 else if (of_device_is_compatible(np_ddr , "jedec,lpddr2-s2"))
1282 dev_info->type = DDR_TYPE_LPDDR2_S2;
1284 of_property_read_u32(np_ddr, "density", &density);
1285 of_property_read_u32(np_ddr, "io-width", &io_width);
1287 /* Convert from density in Mb to the density encoding in jedc_ddr.h */
1288 if (density & (density - 1))
1289 dev_info->density = 0;
1291 dev_info->density = __fls(density) - 5;
1293 /* Convert from io_width in bits to io_width encoding in jedc_ddr.h */
1294 if (io_width & (io_width - 1))
1295 dev_info->io_width = 0;
1297 dev_info->io_width = __fls(io_width) - 1;
1300 static struct emif_data * __init_or_module of_get_memory_device_details(
1301 struct device_node *np_emif, struct device *dev)
1303 struct emif_data *emif = NULL;
1304 struct ddr_device_info *dev_info = NULL;
1305 struct emif_platform_data *pd = NULL;
1306 struct device_node *np_ddr;
1309 np_ddr = of_parse_phandle(np_emif, "device-handle", 0);
1312 emif = devm_kzalloc(dev, sizeof(struct emif_data), GFP_KERNEL);
1313 pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
1314 dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
1316 if (!emif || !pd || !dev_info) {
1317 dev_err(dev, "%s: Out of memory!!\n",
1322 emif->plat_data = pd;
1323 pd->device_info = dev_info;
1325 emif->np_ddr = np_ddr;
1326 emif->temperature_level = SDRAM_TEMP_NOMINAL;
1328 if (of_device_is_compatible(np_emif, "ti,emif-4d"))
1329 emif->plat_data->ip_rev = EMIF_4D;
1330 else if (of_device_is_compatible(np_emif, "ti,emif-4d5"))
1331 emif->plat_data->ip_rev = EMIF_4D5;
1333 of_property_read_u32(np_emif, "phy-type", &pd->phy_type);
1335 if (of_find_property(np_emif, "hw-caps-ll-interface", &len))
1336 pd->hw_caps |= EMIF_HW_CAPS_LL_INTERFACE;
1338 of_get_ddr_info(np_emif, np_ddr, dev_info);
1339 if (!is_dev_data_valid(pd->device_info->type, pd->device_info->density,
1340 pd->device_info->io_width, pd->phy_type, pd->ip_rev,
1342 dev_err(dev, "%s: invalid device data!!\n", __func__);
1346 * For EMIF instances other than EMIF1 see if the devices connected
1347 * are exactly same as on EMIF1(which is typically the case). If so,
1348 * mark it as a duplicate of EMIF1. This will save some memory and
1351 if (emif1 && emif1->np_ddr == np_ddr) {
1352 emif->duplicate = true;
1355 dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
1359 of_get_custom_configs(np_emif, emif);
1360 emif->plat_data->timings = of_get_ddr_timings(np_ddr, emif->dev,
1361 emif->plat_data->device_info->type,
1362 &emif->plat_data->timings_arr_size);
1364 emif->plat_data->min_tck = of_get_min_tck(np_ddr, emif->dev);
1375 static struct emif_data * __init_or_module of_get_memory_device_details(
1376 struct device_node *np_emif, struct device *dev)
1382 static struct emif_data *__init_or_module get_device_details(
1383 struct platform_device *pdev)
1386 struct emif_data *emif = NULL;
1387 struct ddr_device_info *dev_info;
1388 struct emif_custom_configs *cust_cfgs;
1389 struct emif_platform_data *pd;
1393 pd = pdev->dev.platform_data;
1396 if (!(pd && pd->device_info && is_dev_data_valid(pd->device_info->type,
1397 pd->device_info->density, pd->device_info->io_width,
1398 pd->phy_type, pd->ip_rev, dev))) {
1399 dev_err(dev, "%s: invalid device data\n", __func__);
1403 emif = devm_kzalloc(dev, sizeof(*emif), GFP_KERNEL);
1404 temp = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
1405 dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
1407 if (!emif || !pd || !dev_info) {
1408 dev_err(dev, "%s:%d: allocation error\n", __func__, __LINE__);
1412 memcpy(temp, pd, sizeof(*pd));
1414 memcpy(dev_info, pd->device_info, sizeof(*dev_info));
1416 pd->device_info = dev_info;
1417 emif->plat_data = pd;
1419 emif->temperature_level = SDRAM_TEMP_NOMINAL;
1422 * For EMIF instances other than EMIF1 see if the devices connected
1423 * are exactly same as on EMIF1(which is typically the case). If so,
1424 * mark it as a duplicate of EMIF1 and skip copying timings data.
1425 * This will save some memory and some computation later.
1427 emif->duplicate = emif1 && (memcmp(dev_info,
1428 emif1->plat_data->device_info,
1429 sizeof(struct ddr_device_info)) == 0);
1431 if (emif->duplicate) {
1436 dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
1441 * Copy custom configs - ignore allocation error, if any, as
1442 * custom_configs is not very critical
1444 cust_cfgs = pd->custom_configs;
1445 if (cust_cfgs && is_custom_config_valid(cust_cfgs, dev)) {
1446 temp = devm_kzalloc(dev, sizeof(*cust_cfgs), GFP_KERNEL);
1448 memcpy(temp, cust_cfgs, sizeof(*cust_cfgs));
1450 dev_warn(dev, "%s:%d: allocation error\n", __func__,
1452 pd->custom_configs = temp;
1456 * Copy timings and min-tck values from platform data. If it is not
1457 * available or if memory allocation fails, use JEDEC defaults
1459 size = sizeof(struct lpddr2_timings) * pd->timings_arr_size;
1461 temp = devm_kzalloc(dev, size, GFP_KERNEL);
1463 memcpy(temp, pd->timings, sizeof(*pd->timings));
1466 dev_warn(dev, "%s:%d: allocation error\n", __func__,
1468 get_default_timings(emif);
1471 get_default_timings(emif);
1475 temp = devm_kzalloc(dev, sizeof(*pd->min_tck), GFP_KERNEL);
1477 memcpy(temp, pd->min_tck, sizeof(*pd->min_tck));
1480 dev_warn(dev, "%s:%d: allocation error\n", __func__,
1482 pd->min_tck = &lpddr2_jedec_min_tck;
1485 pd->min_tck = &lpddr2_jedec_min_tck;
1495 static int __init_or_module emif_probe(struct platform_device *pdev)
1497 struct emif_data *emif;
1498 struct resource *res;
1501 if (pdev->dev.of_node)
1502 emif = of_get_memory_device_details(pdev->dev.of_node, &pdev->dev);
1504 emif = get_device_details(pdev);
1507 pr_err("%s: error getting device data\n", __func__);
1511 list_add(&emif->node, &device_list);
1512 emif->addressing = get_addressing_table(emif->plat_data->device_info);
1514 /* Save pointers to each other in emif and device structures */
1515 emif->dev = &pdev->dev;
1516 platform_set_drvdata(pdev, emif);
1518 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1520 dev_err(emif->dev, "%s: error getting memory resource\n",
1525 emif->base = devm_ioremap_resource(emif->dev, res);
1526 if (IS_ERR(emif->base))
1529 irq = platform_get_irq(pdev, 0);
1531 dev_err(emif->dev, "%s: error getting IRQ resource - %d\n",
1536 emif_onetime_settings(emif);
1537 emif_debugfs_init(emif);
1538 disable_and_clear_all_interrupts(emif);
1539 setup_interrupts(emif, irq);
1541 /* One-time actions taken on probing the first device */
1544 spin_lock_init(&emif_lock);
1547 * TODO: register notifiers for frequency and voltage
1548 * change here once the respective frameworks are
1553 dev_info(&pdev->dev, "%s: device configured with addr = %p and IRQ%d\n",
1554 __func__, emif->base, irq);
1561 static int __exit emif_remove(struct platform_device *pdev)
1563 struct emif_data *emif = platform_get_drvdata(pdev);
1565 emif_debugfs_exit(emif);
1570 static void emif_shutdown(struct platform_device *pdev)
1572 struct emif_data *emif = platform_get_drvdata(pdev);
1574 disable_and_clear_all_interrupts(emif);
1577 static int get_emif_reg_values(struct emif_data *emif, u32 freq,
1578 struct emif_regs *regs)
1580 u32 cs1_used, ip_rev, phy_type;
1582 const struct lpddr2_timings *timings;
1583 const struct lpddr2_min_tck *min_tck;
1584 const struct ddr_device_info *device_info;
1585 const struct lpddr2_addressing *addressing;
1586 struct emif_data *emif_for_calc;
1588 const struct emif_custom_configs *custom_configs;
1592 * If the devices on this EMIF instance is duplicate of EMIF1,
1593 * use EMIF1 details for the calculation
1595 emif_for_calc = emif->duplicate ? emif1 : emif;
1596 timings = get_timings_table(emif_for_calc, freq);
1597 addressing = emif_for_calc->addressing;
1598 if (!timings || !addressing) {
1599 dev_err(dev, "%s: not enough data available for %dHz",
1604 device_info = emif_for_calc->plat_data->device_info;
1605 type = device_info->type;
1606 cs1_used = device_info->cs1_used;
1607 ip_rev = emif_for_calc->plat_data->ip_rev;
1608 phy_type = emif_for_calc->plat_data->phy_type;
1610 min_tck = emif_for_calc->plat_data->min_tck;
1611 custom_configs = emif_for_calc->plat_data->custom_configs;
1613 set_ddr_clk_period(freq);
1615 regs->ref_ctrl_shdw = get_sdram_ref_ctrl_shdw(freq, addressing);
1616 regs->sdram_tim1_shdw = get_sdram_tim_1_shdw(timings, min_tck,
1618 regs->sdram_tim2_shdw = get_sdram_tim_2_shdw(timings, min_tck,
1620 regs->sdram_tim3_shdw = get_sdram_tim_3_shdw(timings, min_tck,
1621 addressing, type, ip_rev, EMIF_NORMAL_TIMINGS);
1625 if (phy_type == EMIF_PHY_TYPE_ATTILAPHY && ip_rev == EMIF_4D) {
1626 regs->phy_ctrl_1_shdw = get_ddr_phy_ctrl_1_attilaphy_4d(
1628 } else if (phy_type == EMIF_PHY_TYPE_INTELLIPHY && ip_rev == EMIF_4D5) {
1629 regs->phy_ctrl_1_shdw = get_phy_ctrl_1_intelliphy_4d5(freq, cl);
1630 regs->ext_phy_ctrl_2_shdw = get_ext_phy_ctrl_2_intelliphy_4d5();
1631 regs->ext_phy_ctrl_3_shdw = get_ext_phy_ctrl_3_intelliphy_4d5();
1632 regs->ext_phy_ctrl_4_shdw = get_ext_phy_ctrl_4_intelliphy_4d5();
1637 /* Only timeout values in pwr_mgmt_ctrl_shdw register */
1638 regs->pwr_mgmt_ctrl_shdw =
1639 get_pwr_mgmt_ctrl(freq, emif_for_calc, ip_rev) &
1640 (CS_TIM_MASK | SR_TIM_MASK | PD_TIM_MASK);
1642 if (ip_rev & EMIF_4D) {
1643 regs->read_idle_ctrl_shdw_normal =
1644 get_read_idle_ctrl_shdw(DDR_VOLTAGE_STABLE);
1646 regs->read_idle_ctrl_shdw_volt_ramp =
1647 get_read_idle_ctrl_shdw(DDR_VOLTAGE_RAMPING);
1648 } else if (ip_rev & EMIF_4D5) {
1649 regs->dll_calib_ctrl_shdw_normal =
1650 get_dll_calib_ctrl_shdw(DDR_VOLTAGE_STABLE);
1652 regs->dll_calib_ctrl_shdw_volt_ramp =
1653 get_dll_calib_ctrl_shdw(DDR_VOLTAGE_RAMPING);
1656 if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
1657 regs->ref_ctrl_shdw_derated = get_sdram_ref_ctrl_shdw(freq / 4,
1660 regs->sdram_tim1_shdw_derated =
1661 get_sdram_tim_1_shdw_derated(timings, min_tck,
1664 regs->sdram_tim3_shdw_derated = get_sdram_tim_3_shdw(timings,
1665 min_tck, addressing, type, ip_rev,
1666 EMIF_DERATED_TIMINGS);
1675 * get_regs() - gets the cached emif_regs structure for a given EMIF instance
1676 * given frequency(freq):
1678 * As an optimisation, every EMIF instance other than EMIF1 shares the
1679 * register cache with EMIF1 if the devices connected on this instance
1680 * are same as that on EMIF1(indicated by the duplicate flag)
1682 * If we do not have an entry corresponding to the frequency given, we
1683 * allocate a new entry and calculate the values
1685 * Upon finding the right reg dump, save it in curr_regs. It can be
1686 * directly used for thermal de-rating and voltage ramping changes.
1688 static struct emif_regs *get_regs(struct emif_data *emif, u32 freq)
1691 struct emif_regs **regs_cache;
1692 struct emif_regs *regs = NULL;
1696 if (emif->curr_regs && emif->curr_regs->freq == freq) {
1697 dev_dbg(dev, "%s: using curr_regs - %u Hz", __func__, freq);
1698 return emif->curr_regs;
1701 if (emif->duplicate)
1702 regs_cache = emif1->regs_cache;
1704 regs_cache = emif->regs_cache;
1706 for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
1707 if (regs_cache[i]->freq == freq) {
1708 regs = regs_cache[i];
1710 "%s: reg dump found in reg cache for %u Hz\n",
1717 * If we don't have an entry for this frequency in the cache create one
1718 * and calculate the values
1721 regs = devm_kzalloc(emif->dev, sizeof(*regs), GFP_ATOMIC);
1725 if (get_emif_reg_values(emif, freq, regs)) {
1726 devm_kfree(emif->dev, regs);
1731 * Now look for an un-used entry in the cache and save the
1732 * newly created struct. If there are no free entries
1733 * over-write the last entry
1735 for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++)
1738 if (i >= EMIF_MAX_NUM_FREQUENCIES) {
1739 dev_warn(dev, "%s: regs_cache full - reusing a slot!!\n",
1741 i = EMIF_MAX_NUM_FREQUENCIES - 1;
1742 devm_kfree(emif->dev, regs_cache[i]);
1744 regs_cache[i] = regs;
1750 static void do_volt_notify_handling(struct emif_data *emif, u32 volt_state)
1752 dev_dbg(emif->dev, "%s: voltage notification : %d", __func__,
1755 if (!emif->curr_regs) {
1757 "%s: volt-notify before registers are ready: %d\n",
1758 __func__, volt_state);
1762 setup_volt_sensitive_regs(emif, emif->curr_regs, volt_state);
1766 * TODO: voltage notify handling should be hooked up to
1767 * regulator framework as soon as the necessary support
1768 * is available in mainline kernel. This function is un-used
1771 static void __attribute__((unused)) volt_notify_handling(u32 volt_state)
1773 struct emif_data *emif;
1775 spin_lock_irqsave(&emif_lock, irq_state);
1777 list_for_each_entry(emif, &device_list, node)
1778 do_volt_notify_handling(emif, volt_state);
1781 spin_unlock_irqrestore(&emif_lock, irq_state);
1784 static void do_freq_pre_notify_handling(struct emif_data *emif, u32 new_freq)
1786 struct emif_regs *regs;
1788 regs = get_regs(emif, new_freq);
1792 emif->curr_regs = regs;
1795 * Update the shadow registers:
1796 * Temperature and voltage-ramp sensitive settings are also configured
1797 * in terms of DDR cycles. So, we need to update them too when there
1800 dev_dbg(emif->dev, "%s: setting up shadow registers for %uHz",
1801 __func__, new_freq);
1802 setup_registers(emif, regs);
1803 setup_temperature_sensitive_regs(emif, regs);
1804 setup_volt_sensitive_regs(emif, regs, DDR_VOLTAGE_STABLE);
1807 * Part of workaround for errata i728. See do_freq_update()
1810 if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
1811 set_lpmode(emif, EMIF_LP_MODE_DISABLE);
1815 * TODO: frequency notify handling should be hooked up to
1816 * clock framework as soon as the necessary support is
1817 * available in mainline kernel. This function is un-used
1820 static void __attribute__((unused)) freq_pre_notify_handling(u32 new_freq)
1822 struct emif_data *emif;
1825 * NOTE: we are taking the spin-lock here and releases it
1826 * only in post-notifier. This doesn't look good and
1827 * Sparse complains about it, but this seems to be
1828 * un-avoidable. We need to lock a sequence of events
1829 * that is split between EMIF and clock framework.
1831 * 1. EMIF driver updates EMIF timings in shadow registers in the
1832 * frequency pre-notify callback from clock framework
1833 * 2. clock framework sets up the registers for the new frequency
1834 * 3. clock framework initiates a hw-sequence that updates
1835 * the frequency EMIF timings synchronously.
1837 * All these 3 steps should be performed as an atomic operation
1838 * vis-a-vis similar sequence in the EMIF interrupt handler
1839 * for temperature events. Otherwise, there could be race
1840 * conditions that could result in incorrect EMIF timings for
1843 spin_lock_irqsave(&emif_lock, irq_state);
1845 list_for_each_entry(emif, &device_list, node)
1846 do_freq_pre_notify_handling(emif, new_freq);
1849 static void do_freq_post_notify_handling(struct emif_data *emif)
1852 * Part of workaround for errata i728. See do_freq_update()
1855 if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
1856 set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
1860 * TODO: frequency notify handling should be hooked up to
1861 * clock framework as soon as the necessary support is
1862 * available in mainline kernel. This function is un-used
1865 static void __attribute__((unused)) freq_post_notify_handling(void)
1867 struct emif_data *emif;
1869 list_for_each_entry(emif, &device_list, node)
1870 do_freq_post_notify_handling(emif);
1873 * Lock is done in pre-notify handler. See freq_pre_notify_handling()
1876 spin_unlock_irqrestore(&emif_lock, irq_state);
1879 #if defined(CONFIG_OF)
1880 static const struct of_device_id emif_of_match[] = {
1881 { .compatible = "ti,emif-4d" },
1882 { .compatible = "ti,emif-4d5" },
1885 MODULE_DEVICE_TABLE(of, emif_of_match);
1888 static struct platform_driver emif_driver = {
1889 .remove = __exit_p(emif_remove),
1890 .shutdown = emif_shutdown,
1893 .of_match_table = of_match_ptr(emif_of_match),
1897 module_platform_driver_probe(emif_driver, emif_probe);
1899 MODULE_DESCRIPTION("TI EMIF SDRAM Controller Driver");
1900 MODULE_LICENSE("GPL");
1901 MODULE_ALIAS("platform:emif");
1902 MODULE_AUTHOR("Texas Instruments Inc");