2 * linux/drivers/media/video/samsung/mfc5x/mfc_dec.c
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com/
7 * Decoder interface for Samsung MFC (Multi Function Codec - FIMV) driver
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <asm/cacheflush.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
20 #ifdef CONFIG_CPU_FREQ
21 #include <mach/cpufreq.h>
24 #if defined(CONFIG_CPU_S5PV310)
25 #include <mach/regs-mfc.h>
26 #elif defined(CONFIG_ARCH_S5PV210)
27 #include <plat/regs-mfc.h>
39 /*#undef DUMP_STREAM*/
43 #include <linux/syscalls.h>
44 #include <linux/uaccess.h>
45 #include <linux/file.h>
47 static void mfc_fw_debug(void);
48 static void dump_stream(unsigned long address, unsigned int size);
50 static LIST_HEAD(mfc_decoders);
53 #define MPEG4_START_CODE_PREFIX_SIZE 3
54 #define MPEG4_START_CODE_PREFIX 0x000001
55 #define MPEG4_START_CODE_MASK 0x000000FF
56 static int find_mpeg4_startcode(unsigned long addr, unsigned int size)
61 /* FIXME: optimize cache operation size */
62 mfc_mem_cache_inv((void *)addr, size);
64 /* FIXME: optimize matching algorithm */
65 data = (unsigned char *)addr;
67 for (i = 0; i < (size - MPEG4_START_CODE_PREFIX_SIZE); i++) {
68 if ((data[i] == 0x00) && (data[i + 1] == 0x00) && (data[i + 2] == 0x01))
75 static int check_vcl(unsigned long addr, unsigned int size)
82 static void mfc_fw_debug(void)
84 mfc_err("============= MFC FW Debug (Ver: 0x%08x) ================\n",
86 mfc_err("== (0x64: 0x%08x) (0x68: 0x%08x) (0xE4: 0x%08x) \
87 (0xE8: 0x%08x)\n", read_reg(0x64), read_reg(0x68),
88 read_reg(0xe4), read_reg(0xe8));
89 mfc_err("== (0xF0: 0x%08x) (0xF4: 0x%08x) (0xF8: 0x%08x) \
90 (0xFC: 0x%08x)\n", read_reg(0xf0), read_reg(0xf4),
91 read_reg(0xf8), read_reg(0xfc));
94 static void dump_stream(unsigned long address, unsigned int size)
100 unsigned long addr = (unsigned long) phys_to_virt(address);
102 char filename[] = "/data/mfc_decinit_instream.raw";
104 printk(KERN_INFO "---- start stream dump ----\n");
105 printk(KERN_INFO "size: 0x%04x\n", size);
106 for (i = 0; i < size; i += 16) {
107 mfc_dbg("0x%04x: ", i);
109 if ((size - i) >= 16) {
110 for (j = 0; j < 16; j++)
112 (u8)(*(u8 *)(addr + i + j)));
114 for (j = 0; j < (size - i); j++)
116 (u8)(*(u8 *)(addr + i + j)));
120 printk(KERN_INFO "---- end stream dump ----\n");
125 fd = sys_open(filename, O_WRONLY|O_CREAT, 0644);
127 sys_write(fd, (u8 *)addr, size);
130 vfs_write(file, (u8 *)addr, size, &pos);
135 mfc_err("........Open fail : %d\n", fd);
143 * [1] alloc_ctx_buf() implementations
145 static int alloc_ctx_buf(struct mfc_inst_ctx *ctx)
147 struct mfc_alloc_buffer *alloc;
149 alloc = _mfc_alloc_buf(ctx, MFC_CTX_SIZE, ALIGN_2KB, MBT_CTX | PORT_A);
151 mfc_err("failed alloc context buffer\n");
156 ctx->ctxbufofs = mfc_mem_base_ofs(alloc->real) >> 11;
157 ctx->ctxbufsize = alloc->size;
159 memset((void *)alloc->addr, 0, alloc->size);
161 mfc_mem_cache_clean((void *)alloc->addr, alloc->size);
166 static int h264_alloc_ctx_buf(struct mfc_inst_ctx *ctx)
168 struct mfc_alloc_buffer *alloc;
170 alloc = _mfc_alloc_buf(ctx, MFC_CTX_SIZE_L, ALIGN_2KB, MBT_CTX | PORT_A);
172 mfc_err("failed alloc context buffer\n");
177 ctx->ctxbufofs = mfc_mem_base_ofs(alloc->real) >> 11;
178 ctx->ctxbufsize = alloc->size;
180 memset((void *)alloc->addr, 0, alloc->size);
182 mfc_mem_cache_clean((void *)alloc->addr, alloc->size);
188 * [2] alloc_desc_buf() implementations
190 static int alloc_desc_buf(struct mfc_inst_ctx *ctx)
192 struct mfc_alloc_buffer *alloc;
194 /* FIXME: size fixed? */
195 alloc = _mfc_alloc_buf(ctx, MFC_DESC_SIZE, ALIGN_2KB, MBT_DESC | PORT_A);
197 mfc_err("failed alloc descriptor buffer\n");
202 ctx->descbufofs = mfc_mem_base_ofs(alloc->real) >> 11;
203 /* FIXME: size fixed? */
204 ctx->descbufsize = MFC_DESC_SIZE;
210 * [3] pre_seq_start() implementations
212 static int pre_seq_start(struct mfc_inst_ctx *ctx)
214 struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
217 /* slice interface */
218 reg = read_reg(MFC_SI_CH1_DPB_CONF_CTRL);
223 write_reg(reg, MFC_SI_CH1_DPB_CONF_CTRL);
228 static int h264_pre_seq_start(struct mfc_inst_ctx *ctx)
230 struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
231 struct mfc_dec_h264 *h264 = (struct mfc_dec_h264 *)dec_ctx->d_priv;
237 reg = read_reg(MFC_SI_CH1_DPB_CONF_CTRL);
238 if (h264->dispdelay_en > 0) {
242 reg &= ~(0x3FFF << 16);
243 reg |= ((h264->dispdelay_val & 0x3FFF) << 16);
245 /* disable & value clear */
246 reg &= ~(0x7FFF << 16);
248 write_reg(reg, MFC_SI_CH1_DPB_CONF_CTRL);
253 static int mpeg4_pre_seq_start(struct mfc_inst_ctx *ctx)
255 struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
256 struct mfc_dec_mpeg4 *mpeg4 = (struct mfc_dec_mpeg4 *)dec_ctx->d_priv;
261 /* loop filter, this register can be used by both decoders & encoders */
262 reg = read_reg(MFC_ENC_LF_CTRL);
263 if (mpeg4->postfilter)
267 write_reg(reg, MFC_ENC_LF_CTRL);
272 static int fimv1_pre_seq_start(struct mfc_inst_ctx *ctx)
274 struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
275 struct mfc_dec_fimv1 *fimv1 = (struct mfc_dec_fimv1 *)dec_ctx->d_priv;
279 /* set width, height for FIMV1 */
280 write_reg(fimv1->width, MFC_SI_FIMV1_HRESOL);
281 write_reg(fimv1->height, MFC_SI_FIMV1_VRESOL);
287 * [4] post_seq_start() implementations
289 static int post_seq_start(struct mfc_inst_ctx *ctx)
291 struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
294 /* CHKME: case of FIMV1 */
295 ctx->width = read_reg(MFC_SI_HRESOL);
296 ctx->height = read_reg(MFC_SI_VRESOL);
298 dec_ctx->nummindpb = read_reg(MFC_SI_BUF_NUMBER);
299 dec_ctx->numtotaldpb = dec_ctx->nummindpb + dec_ctx->numextradpb;
301 shm = read_shm(ctx, DISP_PIC_PROFILE);
302 dec_ctx->level = (shm >> 8) & 0xFF;
303 dec_ctx->profile = shm & 0x1F;
308 static int h264_post_seq_start(struct mfc_inst_ctx *ctx)
310 struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
311 struct mfc_dec_h264 *h264 = (struct mfc_dec_h264 *)dec_ctx->d_priv;
317 ctx->width = read_reg(MFC_SI_HRESOL);
318 ctx->height = read_reg(MFC_SI_VRESOL);
320 dec_ctx->nummindpb = read_reg(MFC_SI_BUF_NUMBER);
321 dec_ctx->numtotaldpb = dec_ctx->nummindpb + dec_ctx->numextradpb;
323 mfc_dbg("nummindpb: %d, numextradpb: %d\n", dec_ctx->nummindpb,
324 dec_ctx->numextradpb);
326 shm = read_shm(ctx, DISP_PIC_PROFILE);
327 dec_ctx->level = (shm >> 8) & 0xFF;
328 dec_ctx->profile = shm & 0x1F;
330 /* FIXME: consider it */
332 h264->dispdelay_en > 0
334 if (dec_ctx->numtotaldpb < h264->dispdelay_val)
335 dec_ctx->numtotaldpb = h264->dispdelay_val;
338 h264->crop_r_ofs = (read_shm(ctx, CROP_INFO1) >> 16) & 0xFFFF;
339 h264->crop_l_ofs = read_shm(ctx, CROP_INFO1) & 0xFFFF;
340 h264->crop_b_ofs = (read_shm(ctx, CROP_INFO2) >> 16) & 0xFFFF;
341 h264->crop_t_ofs = read_shm(ctx, CROP_INFO2) & 0xFFFF;
346 static int mpeg4_post_seq_start(struct mfc_inst_ctx *ctx)
348 struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
349 struct mfc_dec_mpeg4 *mpeg4 = (struct mfc_dec_mpeg4 *)dec_ctx->d_priv;
355 ctx->width = read_reg(MFC_SI_HRESOL);
356 ctx->height = read_reg(MFC_SI_VRESOL);
358 dec_ctx->nummindpb = read_reg(MFC_SI_BUF_NUMBER);
359 dec_ctx->numtotaldpb = dec_ctx->nummindpb + dec_ctx->numextradpb;
361 shm = read_shm(ctx, DISP_PIC_PROFILE);
362 dec_ctx->level = (shm >> 8) & 0xFF;
363 dec_ctx->profile = shm & 0x1F;
365 mpeg4->aspect_ratio = read_shm(ctx, ASPECT_RATIO_INFO) & 0xF;
366 if (mpeg4->aspect_ratio == 0xF) {
367 shm = read_shm(ctx, EXTENDED_PAR);
368 mpeg4->ext_par_width = (shm >> 16) & 0xFFFF;
369 mpeg4->ext_par_height = shm & 0xFFFF;
371 mpeg4->ext_par_width = 0;
372 mpeg4->ext_par_height = 0;
378 static int vc1_post_seq_start(struct mfc_inst_ctx *ctx)
380 struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
386 ctx->width = read_reg(MFC_SI_HRESOL);
387 ctx->height = read_reg(MFC_SI_VRESOL);
389 dec_ctx->nummindpb = read_reg(MFC_SI_BUF_NUMBER);
390 dec_ctx->numtotaldpb = dec_ctx->nummindpb + dec_ctx->numextradpb;
392 shm = read_shm(ctx, DISP_PIC_PROFILE);
393 dec_ctx->level = (shm >> 8) & 0xFF;
394 dec_ctx->profile = shm & 0x1F;
399 static int fimv1_post_seq_start(struct mfc_inst_ctx *ctx)
401 struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
402 struct mfc_dec_fimv1 *fimv1 = (struct mfc_dec_fimv1 *)dec_ctx->d_priv;
408 ctx->width = read_reg(MFC_SI_HRESOL);
409 ctx->height = read_reg(MFC_SI_VRESOL);
411 dec_ctx->nummindpb = read_reg(MFC_SI_BUF_NUMBER);
412 dec_ctx->numtotaldpb = dec_ctx->nummindpb + dec_ctx->numextradpb;
414 shm = read_shm(ctx, DISP_PIC_PROFILE);
415 dec_ctx->level = (shm >> 8) & 0xFF;
416 dec_ctx->profile = shm & 0x1F;
418 fimv1->aspect_ratio = read_shm(ctx, ASPECT_RATIO_INFO) & 0xF;
419 if (fimv1->aspect_ratio == 0xF) {
420 shm = read_shm(ctx, EXTENDED_PAR);
421 fimv1->ext_par_width = (shm >> 16) & 0xFFFF;
422 fimv1->ext_par_height = shm & 0xFFFF;
424 fimv1->ext_par_width = 0;
425 fimv1->ext_par_height = 0;
432 * [5] set_init_arg() implementations
434 static int set_init_arg(struct mfc_inst_ctx *ctx, void *arg)
436 struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
437 struct mfc_dec_init_arg *dec_init_arg = (struct mfc_dec_init_arg *)arg;
439 dec_init_arg->out_frm_width = ctx->width;
440 dec_init_arg->out_frm_height = ctx->height;
441 dec_init_arg->out_buf_width = ALIGN(ctx->width, ALIGN_W);
442 dec_init_arg->out_buf_height = ALIGN(ctx->height, ALIGN_H);
444 dec_init_arg->out_dpb_cnt = dec_ctx->numtotaldpb;
449 static int h264_set_init_arg(struct mfc_inst_ctx *ctx, void *arg)
451 struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
452 struct mfc_dec_h264 *h264 = (struct mfc_dec_h264 *)dec_ctx->d_priv;
453 struct mfc_dec_init_arg *dec_init_arg = (struct mfc_dec_init_arg *)arg;
455 set_init_arg(ctx, arg);
457 dec_init_arg->out_crop_right_offset = h264->crop_r_ofs;
458 dec_init_arg->out_crop_left_offset = h264->crop_l_ofs;
459 dec_init_arg->out_crop_bottom_offset = h264->crop_b_ofs;
460 dec_init_arg->out_crop_top_offset = h264->crop_t_ofs;
465 static int mpeg4_set_init_arg(struct mfc_inst_ctx *ctx, void *arg)
468 struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
469 struct mfc_dec_mpeg4 *mpeg4 = (struct mfc_dec_mpeg4 *)dec_ctx->d_priv;
470 struct mfc_dec_init_arg *dec_init_arg = (struct mfc_dec_init_arg *)arg;
473 set_init_arg(ctx, arg);
476 dec_init_arg->out_aspect_ratio = mpeg4->aspect_ratio;
477 dec_init_arg->out_ext_par_width = mpeg4->ext_par_width;
478 dec_init_arg->out_ext_par_height = mpeg4->ext_par_height;
485 * [6] set_codec_bufs() implementations
487 static int set_codec_bufs(struct mfc_inst_ctx *ctx)
492 static int h264_set_codec_bufs(struct mfc_inst_ctx *ctx)
494 struct mfc_alloc_buffer *alloc;
496 alloc = _mfc_alloc_buf(ctx, MFC_DEC_NBMV_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
498 mfc_err("failed alloc codec buffer\n");
502 write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_VERT_NB_MV_ADR);
504 alloc = _mfc_alloc_buf(ctx, MFC_DEC_NBIP_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
506 mfc_free_buf_type(ctx->id, MBT_CODEC);
507 mfc_err("failed alloc codec buffer\n");
511 write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_VERT_NB_IP_ADR);
516 static int vc1_set_codec_bufs(struct mfc_inst_ctx *ctx)
518 struct mfc_alloc_buffer *alloc;
520 alloc = _mfc_alloc_buf(ctx, MFC_DEC_NBDCAC_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
522 mfc_err("failed alloc codec buffer\n");
526 write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_NB_DCAC_ADR);
528 alloc = _mfc_alloc_buf(ctx, MFC_DEC_UPNBMV_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
530 mfc_free_buf_type(ctx->id, MBT_CODEC);
531 mfc_err("failed alloc codec buffer\n");
535 write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_UP_NB_MV_ADR);
537 alloc = _mfc_alloc_buf(ctx, MFC_DEC_SAMV_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
539 mfc_free_buf_type(ctx->id, MBT_CODEC);
540 mfc_err("failed alloc codec buffer\n");
544 write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_SA_MV_ADR);
546 alloc = _mfc_alloc_buf(ctx, MFC_DEC_OTLINE_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
548 mfc_free_buf_type(ctx->id, MBT_CODEC);
549 mfc_err("failed alloc codec buffer\n");
553 write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_OT_LINE_ADR);
555 alloc = _mfc_alloc_buf(ctx, MFC_DEC_BITPLANE_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
557 mfc_free_buf_type(ctx->id, MBT_CODEC);
558 mfc_err("failed alloc codec buffer\n");
562 write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_BITPLANE3_ADR);
564 alloc = _mfc_alloc_buf(ctx, MFC_DEC_BITPLANE_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
566 mfc_free_buf_type(ctx->id, MBT_CODEC);
567 mfc_err("failed alloc codec buffer\n");
571 write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_BITPLANE2_ADR);
573 alloc = _mfc_alloc_buf(ctx, MFC_DEC_BITPLANE_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
575 mfc_free_buf_type(ctx->id, MBT_CODEC);
576 mfc_err("failed alloc codec buffer\n");
580 write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_BITPLANE1_ADR);
585 static int mpeg4_set_codec_bufs(struct mfc_inst_ctx *ctx)
587 struct mfc_alloc_buffer *alloc;
589 alloc = _mfc_alloc_buf(ctx, MFC_DEC_NBDCAC_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
591 mfc_err("failed alloc codec buffer\n");
595 write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_NB_DCAC_ADR);
597 alloc = _mfc_alloc_buf(ctx, MFC_DEC_UPNBMV_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
599 mfc_free_buf_type(ctx->id, MBT_CODEC);
600 mfc_err("failed alloc codec buffer\n");
604 write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_UP_NB_MV_ADR);
606 alloc = _mfc_alloc_buf(ctx, MFC_DEC_SAMV_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
608 mfc_free_buf_type(ctx->id, MBT_CODEC);
609 mfc_err("failed alloc codec buffer\n");
613 write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_SA_MV_ADR);
615 alloc = _mfc_alloc_buf(ctx, MFC_DEC_OTLINE_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
617 mfc_free_buf_type(ctx->id, MBT_CODEC);
618 mfc_err("failed alloc codec buffer\n");
622 write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_OT_LINE_ADR);
624 alloc = _mfc_alloc_buf(ctx, MFC_DEC_SYNPAR_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
626 mfc_free_buf_type(ctx->id, MBT_CODEC);
627 mfc_err("failed alloc codec buffer\n");
631 write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_SP_ADR);
636 static int h263_set_codec_bufs(struct mfc_inst_ctx *ctx)
638 struct mfc_alloc_buffer *alloc;
640 alloc = _mfc_alloc_buf(ctx, MFC_DEC_NBDCAC_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
642 mfc_err("failed alloc codec buffer\n");
646 write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_NB_DCAC_ADR);
648 alloc = _mfc_alloc_buf(ctx, MFC_DEC_UPNBMV_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
650 mfc_free_buf_type(ctx->id, MBT_CODEC);
651 mfc_err("failed alloc codec buffer\n");
655 write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_UP_NB_MV_ADR);
657 alloc = _mfc_alloc_buf(ctx, MFC_DEC_SAMV_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
659 mfc_free_buf_type(ctx->id, MBT_CODEC);
660 mfc_err("failed alloc codec buffer\n");
664 write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_SA_MV_ADR);
666 alloc = _mfc_alloc_buf(ctx, MFC_DEC_OTLINE_SIZE, ALIGN_2KB, MBT_CODEC | PORT_A);
668 mfc_free_buf_type(ctx->id, MBT_CODEC);
669 mfc_err("failed alloc codec buffer\n");
673 write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_OT_LINE_ADR);
679 * [7] set_dpbs() implementations
681 static int set_dpbs(struct mfc_inst_ctx *ctx)
683 struct mfc_alloc_buffer *alloc;
686 struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
688 /* width: 128B align, height: 32B align, size: 8KB align */
689 /* add some guard buffers to luma & chroma */
690 dec_ctx->lumasize = ALIGN(ctx->width + 24, ALIGN_W) * ALIGN(ctx->height + 16, ALIGN_H);
691 dec_ctx->lumasize = ALIGN(dec_ctx->lumasize, ALIGN_8KB);
692 dec_ctx->chromasize = ALIGN(ctx->width + 16, ALIGN_W) * ALIGN((ctx->height >> 1) + 4, ALIGN_H);
693 dec_ctx->chromasize = ALIGN(dec_ctx->chromasize, ALIGN_8KB);
695 for (i = 0; i < dec_ctx->numtotaldpb; i++) {
697 * allocate chroma buffer
699 alloc = _mfc_alloc_buf(ctx, dec_ctx->chromasize, ALIGN_2KB, MBT_DPB | PORT_A);
701 mfc_free_buf_type(ctx->id, MBT_DPB);
702 mfc_err("failed alloc chroma buffer\n");
707 /* clear first DPB chroma buffer, referrence buffer for
708 vectors starting with p-frame */
710 memset((void *)alloc->addr, 0x80, alloc->size);
711 mfc_mem_cache_clean((void *)alloc->addr, alloc->size);
715 * set chroma buffer address
717 write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_CHROMA_ADR + (4 * i));
720 * allocate luma buffer
722 alloc = _mfc_alloc_buf(ctx, dec_ctx->lumasize, ALIGN_2KB, MBT_DPB | PORT_B);
724 mfc_free_buf_type(ctx->id, MBT_DPB);
725 mfc_err("failed alloc luma buffer\n");
730 /* clear first DPB luma buffer, referrence buffer for
731 vectors starting with p-frame */
733 memset((void *)alloc->addr, 0x0, alloc->size);
734 mfc_mem_cache_clean((void *)alloc->addr, alloc->size);
738 * set luma buffer address
740 write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_LUMA_ADR + (4 * i));
743 write_shm(ctx, dec_ctx->lumasize, ALLOCATED_LUMA_DPB_SIZE);
744 write_shm(ctx, dec_ctx->chromasize, ALLOCATED_CHROMA_DPB_SIZE);
745 write_shm(ctx, 0, ALLOCATED_MV_SIZE);
748 reg = read_reg(MFC_SI_CH1_DPB_CONF_CTRL);
750 reg |= dec_ctx->numtotaldpb;
751 write_reg(reg, MFC_SI_CH1_DPB_CONF_CTRL);
756 static int h264_set_dpbs(struct mfc_inst_ctx *ctx)
758 struct mfc_alloc_buffer *alloc;
761 struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
762 struct mfc_dec_h264 *h264 = (struct mfc_dec_h264 *)dec_ctx->d_priv;
764 /* width: 128B align, height: 32B align, size: 8KB align */
765 dec_ctx->lumasize = ALIGN(ctx->width, ALIGN_W) * ALIGN(ctx->height, ALIGN_H);
766 dec_ctx->lumasize = ALIGN(dec_ctx->lumasize, ALIGN_8KB);
767 dec_ctx->chromasize = ALIGN(ctx->width, ALIGN_W) * ALIGN(ctx->height >> 1, ALIGN_H);
768 dec_ctx->chromasize = ALIGN(dec_ctx->chromasize, ALIGN_8KB);
770 h264->mvsize = ALIGN(ctx->width, ALIGN_W) * ALIGN(ctx->height >> 2, ALIGN_H);
771 h264->mvsize = ALIGN(h264->mvsize, ALIGN_8KB);
773 for (i = 0; i < dec_ctx->numtotaldpb; i++) {
775 * allocate chroma buffer
777 alloc = _mfc_alloc_buf(ctx, dec_ctx->chromasize, ALIGN_2KB, MBT_DPB | PORT_A);
779 mfc_free_buf_type(ctx->id, MBT_DPB);
780 mfc_err("failed alloc chroma buffer\n");
785 /* clear first DPB chroma buffer, referrence buffer for
786 vectors starting with p-frame */
788 memset((void *)alloc->addr, 0x80, alloc->size);
789 mfc_mem_cache_clean((void *)alloc->addr, alloc->size);
793 * set chroma buffer address
795 write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_CHROMA_ADR + (4 * i));
798 * allocate luma buffer
800 alloc = _mfc_alloc_buf(ctx, dec_ctx->lumasize, ALIGN_2KB, MBT_DPB | PORT_B);
802 mfc_free_buf_type(ctx->id, MBT_DPB);
803 mfc_err("failed alloc luma buffer\n");
808 /* clear first DPB luma buffer, referrence buffer for
809 vectors starting with p-frame */
811 memset((void *)alloc->addr, 0x0, alloc->size);
812 mfc_mem_cache_clean((void *)alloc->addr, alloc->size);
816 * set luma buffer address
818 write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_LUMA_ADR + (4 * i));
823 alloc = _mfc_alloc_buf(ctx, h264->mvsize, ALIGN_2KB, MBT_DPB | PORT_B);
825 mfc_free_buf_type(ctx->id, MBT_DPB);
826 mfc_err("failed alloc mv buffer\n");
831 * set mv buffer address
833 write_reg(mfc_mem_base_ofs(alloc->real) >> 11, MFC_MV_ADR + (4 * i));
836 write_shm(ctx, dec_ctx->lumasize, ALLOCATED_LUMA_DPB_SIZE);
837 write_shm(ctx, dec_ctx->chromasize, ALLOCATED_CHROMA_DPB_SIZE);
839 write_shm(ctx, h264->mvsize, ALLOCATED_MV_SIZE);
842 reg = read_reg(MFC_SI_CH1_DPB_CONF_CTRL);
844 reg |= dec_ctx->numtotaldpb;
845 write_reg(reg, MFC_SI_CH1_DPB_CONF_CTRL);
851 * [8] pre_frame_start() implementations
853 static int pre_frame_start(struct mfc_inst_ctx *ctx)
859 * [9] post_frame_start() implementations
861 static int post_frame_start(struct mfc_inst_ctx *ctx)
867 * [10] multi_frame_start() implementations
869 static int multi_data_frame(struct mfc_inst_ctx *ctx)
874 static int mpeg4_multi_data_frame(struct mfc_inst_ctx *ctx)
876 struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
877 struct mfc_dec_mpeg4 *mpeg4 = (struct mfc_dec_mpeg4 *)dec_ctx->d_priv;
879 if (!mpeg4->packedpb)
882 /* FIXME: I_FRAME is valid? */
883 if ((dec_ctx->decframetype == DEC_FRM_I) || (dec_ctx->decframetype == DEC_FRM_P)) {
891 * [11] set_exe_arg() implementations
893 static int set_exe_arg(struct mfc_inst_ctx *ctx, void *arg)
896 struct mfc_dec_exe_arg *dec_exe_arg = (struct mfc_dec_exe_arg *)arg;
903 * [12] get_codec_cfg() implementations
905 static int get_codec_cfg(struct mfc_inst_ctx *ctx, unsigned int type, int *value)
907 //struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
910 mfc_dbg("type: 0x%08x", type);
913 MFC_DEC_GETCONF_CRC_DATA = DEC_GET,
914 MFC_DEC_GETCONF_BUF_WIDTH_HEIGHT
915 MFC_DEC_GETCONF_FRAME_TAG,
916 MFC_DEC_GETCONF_PIC_TIME,
918 MFC_DEC_GETCONF_ASPECT_RATIO:
919 MFC_DEC_GETCONF_EXTEND_PAR:
923 case MFC_DEC_GETCONF_CRC_DATA:
932 mfc_err("invalid get config type: 0x%08x\n", type);
942 * [13] set_codec_cfg() implementations
944 static int set_codec_cfg(struct mfc_inst_ctx *ctx, unsigned int type, int *value)
946 struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
949 mfc_dbg("type: 0x%08x", type);
952 MFC_DEC_SETCONF_FRAME_TAG,
958 case MFC_DEC_SETCONF_EXTRA_BUFFER_NUM:
959 if (ctx->state >= INST_STATE_INIT)
960 return MFC_STATE_INVALID;
962 if ((value[0] >= 0) && (value[0] <= MFC_MAX_EXTRA_DPB)) {
963 dec_ctx->numextradpb = value[0];
965 dec_ctx->numextradpb = MFC_MAX_EXTRA_DPB;
966 mfc_warn("invalid extra dpb buffer number: %d", value[0]);
967 mfc_warn("set %d by default", MFC_MAX_EXTRA_DPB);
972 case MFC_DEC_SETCONF_IS_LAST_FRAME:
973 mfc_dbg("ctx->state: 0x%08x", ctx->state);
975 if (ctx->state < INST_STATE_EXE) {
976 mfc_dbg("invalid instance state: 0x%08x\n", type);
981 dec_ctx->lastframe = 1;
983 dec_ctx->lastframe = 0;
987 case MFC_DEC_SETCONF_SLICE_ENABLE:
988 if (ctx->state >= INST_STATE_INIT)
989 return MFC_STATE_INVALID;
999 case MFC_DEC_SETCONF_CRC_ENABLE:
1000 if (ctx->state >= INST_STATE_INIT)
1001 return MFC_STATE_INVALID;
1010 case MFC_DEC_SETCONF_DPB_FLUSH:
1011 if (ctx->state < INST_STATE_EXE) {
1012 mfc_dbg("invalid instance state: 0x%08x\n", type);
1013 return MFC_STATE_INVALID;
1017 dec_ctx->dpbflush = 1;
1021 mfc_dbg("invalid set cfg type: 0x%08x\n", type);
1030 static int h264_set_codec_cfg(struct mfc_inst_ctx *ctx, unsigned int type, int *value)
1032 struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
1033 struct mfc_dec_h264 *h264 = (struct mfc_dec_h264 *)dec_ctx->d_priv;
1036 mfc_dbg("type: 0x%08x", type);
1038 ret = set_codec_cfg(ctx, type, value);
1045 case MFC_DEC_SETCONF_DISPLAY_DELAY:
1046 if (ctx->state >= INST_STATE_INIT) {
1047 mfc_dbg("invalid instance state: 0x%08x\n", type);
1051 h264->dispdelay_en = 1;
1052 if ((value[0] >= 0) && (value[0] <= MFC_MAX_DISP_DELAY)) {
1053 h264->dispdelay_val = value[0];
1055 h264->dispdelay_val = MFC_MAX_DISP_DELAY;
1056 mfc_warn("invalid diplay delay count: %d", value[0]);
1057 mfc_warn("set %d by default", MFC_MAX_DISP_DELAY);
1063 mfc_dbg("invalid set cfg type: 0x%08x\n", type);
1072 static int mpeg4_set_codec_cfg(struct mfc_inst_ctx *ctx, unsigned int type, int *value)
1074 struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
1075 struct mfc_dec_mpeg4 *mpeg4 = (struct mfc_dec_mpeg4 *)dec_ctx->d_priv;
1078 mfc_dbg("type: 0x%08x", type);
1080 ret = set_codec_cfg(ctx, type, value);
1087 case MFC_DEC_SETCONF_POST_ENABLE:
1088 if (ctx->state >= INST_STATE_INIT)
1092 mpeg4->postfilter = 1;
1094 mpeg4->postfilter = 0;
1098 case MFC_DEC_SETCONF_PACKEDPB:
1099 if (ctx->state < INST_STATE_OPEN)
1103 mpeg4->packedpb = 1;
1105 mpeg4->packedpb = 1;
1110 mfc_dbg("invalid set cfg type: 0x%08x\n", type);
1119 static int fimv1_set_codec_cfg(struct mfc_inst_ctx *ctx, unsigned int type, int *value)
1121 struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
1122 struct mfc_dec_fimv1 *fimv1 = (struct mfc_dec_fimv1 *)dec_ctx->d_priv;
1125 mfc_dbg("type: 0x%08x", type);
1127 ret = set_codec_cfg(ctx, type, value);
1134 case MFC_DEC_SETCONF_FIMV1_WIDTH_HEIGHT:
1135 if (ctx->state >= INST_STATE_INIT)
1138 fimv1->width = value[0];
1139 fimv1->height = value[1];
1143 case MFC_DEC_SETCONF_PACKEDPB:
1144 if (ctx->state < INST_STATE_OPEN)
1148 fimv1->packedpb = 1;
1150 fimv1->packedpb = 1;
1155 mfc_dbg("invalid set cfg type: 0x%08x\n", type);
1164 static struct mfc_dec_info unknown_dec = {
1166 .codectype = UNKNOWN_TYPE,
1170 * The unknown codec operations will be not call,
1171 * unused default operations raise build warning.
1174 .alloc_ctx_buf = alloc_ctx_buf,
1175 .alloc_desc_buf = alloc_desc_buf,
1176 .pre_seq_start = pre_seq_start,
1177 .post_seq_start = post_seq_start,
1178 .set_init_arg = set_init_arg,
1179 .set_codec_bufs = set_codec_bufs,
1180 .set_dpbs = set_dpbs,
1181 .pre_frame_start = pre_frame_start,
1182 .post_frame_start = post_frame_start,
1183 .multi_data_frame = multi_data_frame,
1184 .set_exe_arg = set_exe_arg,
1185 .get_codec_cfg = get_codec_cfg,
1186 .set_codec_cfg = set_codec_cfg,
1190 static struct mfc_dec_info h264_dec = {
1192 .codectype = H264_DEC,
1194 .d_priv_size = sizeof(struct mfc_dec_h264),
1196 .alloc_ctx_buf = h264_alloc_ctx_buf,
1197 .alloc_desc_buf = alloc_desc_buf,
1198 .pre_seq_start = h264_pre_seq_start,
1199 .post_seq_start = h264_post_seq_start,
1200 .set_init_arg = h264_set_init_arg,
1201 .set_codec_bufs = h264_set_codec_bufs,
1202 .set_dpbs = h264_set_dpbs,
1203 .pre_frame_start = NULL,
1204 .post_frame_start = NULL,
1205 .multi_data_frame = NULL,
1206 .set_exe_arg = set_exe_arg,
1207 .get_codec_cfg = get_codec_cfg,
1208 .set_codec_cfg = h264_set_codec_cfg,
1212 static struct mfc_dec_info vc1_dec = {
1214 .codectype = VC1_DEC,
1218 .alloc_ctx_buf = alloc_ctx_buf,
1219 .alloc_desc_buf = alloc_desc_buf,
1220 .pre_seq_start = pre_seq_start,
1221 .post_seq_start = vc1_post_seq_start,
1222 .set_init_arg = set_init_arg,
1223 .set_codec_bufs = vc1_set_codec_bufs,
1224 .set_dpbs = set_dpbs,
1225 .pre_frame_start = NULL,
1226 .post_frame_start = NULL,
1227 .multi_data_frame = NULL,
1228 .set_exe_arg = set_exe_arg,
1229 .get_codec_cfg = get_codec_cfg,
1230 .set_codec_cfg = set_codec_cfg,
1234 static struct mfc_dec_info mpeg4_dec = {
1236 .codectype = MPEG4_DEC,
1238 .d_priv_size = sizeof(struct mfc_dec_mpeg4),
1240 .alloc_ctx_buf = alloc_ctx_buf,
1241 .alloc_desc_buf = alloc_desc_buf,
1242 .pre_seq_start = mpeg4_pre_seq_start,
1243 .post_seq_start = mpeg4_post_seq_start,
1244 .set_init_arg = mpeg4_set_init_arg,
1245 .set_codec_bufs = mpeg4_set_codec_bufs,
1246 .set_dpbs = set_dpbs,
1247 .pre_frame_start = NULL,
1248 .post_frame_start = NULL,
1249 .multi_data_frame = NULL, /* FIXME: mpeg4_multi_data_frame */
1250 .set_exe_arg = set_exe_arg,
1251 .get_codec_cfg = get_codec_cfg,
1252 .set_codec_cfg = mpeg4_set_codec_cfg,
1256 static struct mfc_dec_info xvid_dec = {
1258 .codectype = XVID_DEC,
1260 .d_priv_size = sizeof(struct mfc_dec_mpeg4),
1262 .alloc_ctx_buf = alloc_ctx_buf,
1263 .alloc_desc_buf = alloc_desc_buf,
1264 .pre_seq_start = mpeg4_pre_seq_start,
1265 .post_seq_start = mpeg4_post_seq_start,
1266 .set_init_arg = mpeg4_set_init_arg,
1267 .set_codec_bufs = mpeg4_set_codec_bufs,
1268 .set_dpbs = set_dpbs,
1269 .pre_frame_start = NULL,
1270 .post_frame_start = NULL,
1271 .multi_data_frame = NULL, /* FIXME: mpeg4_multi_data_frame */
1272 .set_exe_arg = set_exe_arg,
1273 .get_codec_cfg = get_codec_cfg,
1274 .set_codec_cfg = mpeg4_set_codec_cfg,
1278 static struct mfc_dec_info mpeg1_dec = {
1280 .codectype = MPEG1_DEC,
1284 .alloc_ctx_buf = alloc_ctx_buf,
1285 .alloc_desc_buf = alloc_desc_buf,
1286 .pre_seq_start = pre_seq_start,
1287 .post_seq_start = post_seq_start,
1288 .set_init_arg = set_init_arg,
1289 .set_codec_bufs = NULL,
1290 .set_dpbs = set_dpbs,
1291 .pre_frame_start = NULL,
1292 .post_frame_start = NULL,
1293 .multi_data_frame = NULL,
1294 .set_exe_arg = set_exe_arg,
1295 .get_codec_cfg = get_codec_cfg,
1296 .set_codec_cfg = set_codec_cfg,
1300 static struct mfc_dec_info mpeg2_dec = {
1302 .codectype = MPEG2_DEC,
1306 .alloc_ctx_buf = alloc_ctx_buf,
1307 .alloc_desc_buf = alloc_desc_buf,
1308 .pre_seq_start = pre_seq_start,
1309 .post_seq_start = post_seq_start,
1310 .set_init_arg = set_init_arg,
1311 .set_codec_bufs = NULL,
1312 .set_dpbs = set_dpbs,
1313 .pre_frame_start = NULL,
1314 .post_frame_start = NULL,
1315 .multi_data_frame = NULL,
1316 .set_exe_arg = set_exe_arg,
1317 .get_codec_cfg = get_codec_cfg,
1318 .set_codec_cfg = set_codec_cfg,
1322 static struct mfc_dec_info h263_dec = {
1324 .codectype = H263_DEC,
1328 .alloc_ctx_buf = alloc_ctx_buf,
1329 .alloc_desc_buf = alloc_desc_buf,
1330 .pre_seq_start = pre_seq_start,
1331 .post_seq_start = post_seq_start,
1332 .set_init_arg = set_init_arg,
1333 .set_codec_bufs = h263_set_codec_bufs,
1334 .set_dpbs = set_dpbs,
1335 .pre_frame_start = NULL,
1336 .post_frame_start = NULL,
1337 .multi_data_frame = NULL,
1338 .set_exe_arg = set_exe_arg,
1339 .get_codec_cfg = get_codec_cfg,
1340 .set_codec_cfg = set_codec_cfg,
1344 static struct mfc_dec_info vc1rcv_dec = {
1346 .codectype = VC1RCV_DEC,
1350 .alloc_ctx_buf = alloc_ctx_buf,
1351 .alloc_desc_buf = alloc_desc_buf,
1352 .pre_seq_start = pre_seq_start,
1353 .post_seq_start = vc1_post_seq_start,
1354 .set_init_arg = set_init_arg,
1355 .set_codec_bufs = vc1_set_codec_bufs,
1356 .set_dpbs = set_dpbs,
1357 .pre_frame_start = NULL,
1358 .post_frame_start = NULL,
1359 .multi_data_frame = NULL,
1360 .set_exe_arg = set_exe_arg,
1361 .get_codec_cfg = get_codec_cfg,
1362 .set_codec_cfg = set_codec_cfg,
1366 static struct mfc_dec_info fimv1_dec = {
1368 .codectype = FIMV1_DEC,
1370 .d_priv_size = sizeof(struct mfc_dec_fimv1),
1372 .alloc_ctx_buf = alloc_ctx_buf,
1373 .alloc_desc_buf = alloc_desc_buf,
1374 .pre_seq_start = fimv1_pre_seq_start,
1375 .post_seq_start = fimv1_post_seq_start,
1376 .set_init_arg = set_init_arg, /* FIMXE */
1377 .set_codec_bufs = mpeg4_set_codec_bufs, /* FIXME */
1378 .set_dpbs = set_dpbs,
1379 .pre_frame_start = NULL,
1380 .post_frame_start = NULL,
1381 .multi_data_frame = mpeg4_multi_data_frame,
1382 .set_exe_arg = set_exe_arg,
1383 .get_codec_cfg = get_codec_cfg,
1384 .set_codec_cfg = fimv1_set_codec_cfg,
1388 static struct mfc_dec_info fimv2_dec = {
1390 .codectype = FIMV2_DEC,
1392 .d_priv_size = sizeof(struct mfc_dec_mpeg4),
1394 .alloc_ctx_buf = alloc_ctx_buf,
1395 .alloc_desc_buf = alloc_desc_buf,
1396 .pre_seq_start = mpeg4_pre_seq_start,
1397 .post_seq_start = mpeg4_post_seq_start,
1398 .set_init_arg = mpeg4_set_init_arg,
1399 .set_codec_bufs = mpeg4_set_codec_bufs,
1400 .set_dpbs = set_dpbs,
1401 .pre_frame_start = NULL,
1402 .post_frame_start = NULL,
1403 .multi_data_frame = mpeg4_multi_data_frame,
1404 .set_exe_arg = set_exe_arg,
1405 .get_codec_cfg = get_codec_cfg,
1406 .set_codec_cfg = mpeg4_set_codec_cfg,
1410 static struct mfc_dec_info fimv3_dec = {
1412 .codectype = FIMV3_DEC,
1414 .d_priv_size = sizeof(struct mfc_dec_mpeg4),
1416 .alloc_ctx_buf = alloc_ctx_buf,
1417 .alloc_desc_buf = alloc_desc_buf,
1418 .pre_seq_start = mpeg4_pre_seq_start,
1419 .post_seq_start = mpeg4_post_seq_start,
1420 .set_init_arg = mpeg4_set_init_arg,
1421 .set_codec_bufs = mpeg4_set_codec_bufs,
1422 .set_dpbs = set_dpbs,
1423 .pre_frame_start = NULL,
1424 .post_frame_start = NULL,
1425 .multi_data_frame = mpeg4_multi_data_frame,
1426 .set_exe_arg = set_exe_arg,
1427 .get_codec_cfg = get_codec_cfg,
1428 .set_codec_cfg = mpeg4_set_codec_cfg,
1432 static struct mfc_dec_info fimv4_dec = {
1434 .codectype = FIMV4_DEC,
1436 .d_priv_size = sizeof(struct mfc_dec_mpeg4),
1438 .alloc_ctx_buf = alloc_ctx_buf,
1439 .alloc_desc_buf = alloc_desc_buf,
1440 .pre_seq_start = mpeg4_pre_seq_start,
1441 .post_seq_start = mpeg4_post_seq_start,
1442 .set_init_arg = mpeg4_set_init_arg,
1443 .set_codec_bufs = mpeg4_set_codec_bufs,
1444 .set_dpbs = set_dpbs,
1445 .pre_frame_start = NULL,
1446 .post_frame_start = NULL,
1447 .multi_data_frame = mpeg4_multi_data_frame,
1448 .set_exe_arg = set_exe_arg,
1449 .get_codec_cfg = get_codec_cfg,
1450 .set_codec_cfg = mpeg4_set_codec_cfg,
1454 static int CheckMPEG4StartCode(unsigned char *src_mem, unsigned int remainSize)
1456 unsigned int index = 0;
1458 for (index = 0; index < remainSize-3; index++) {
1459 if ((src_mem[index] == 0x00) && (src_mem[index+1] == 0x00) &&
1460 (src_mem[index+2] == 0x01))
1467 static int CheckDecStartCode(unsigned char *src_mem,
1468 unsigned int nstreamSize,
1469 SSBSIP_MFC_CODEC_TYPE nCodecType)
1471 unsigned int index = 0;
1472 /* Check Start Code within "isearchSize" bytes */
1473 unsigned int isearchSize = 20;
1474 unsigned int nShift = 0;
1475 unsigned char nFlag = 0xFF;
1477 if (nCodecType == H263_DEC) {
1480 } else if (nCodecType == MPEG4_DEC) {
1483 } else if (nCodecType == H264_DEC) {
1489 /* Last frame detection from user */
1490 if (nstreamSize == 0)
1496 if (nstreamSize > 3) {
1497 if (nstreamSize > isearchSize) {
1498 for (index = 0; index < isearchSize-3; index++) {
1499 if ((src_mem[index] == 0x00) &&
1500 (src_mem[index+1] == 0x00) &&
1501 ((src_mem[index+2] >> nShift) == nFlag))
1505 for (index = 0; index < nstreamSize - 3; index++) {
1506 if ((src_mem[index] == 0x00) &&
1507 (src_mem[index+1] == 0x00) &&
1508 ((src_mem[index+2] >> nShift) == nFlag))
1517 void mfc_init_decoders(void)
1519 list_add_tail(&unknown_dec.list, &mfc_decoders);
1521 list_add_tail(&h264_dec.list, &mfc_decoders);
1522 list_add_tail(&vc1_dec.list, &mfc_decoders);
1523 list_add_tail(&mpeg4_dec.list, &mfc_decoders);
1524 list_add_tail(&xvid_dec.list, &mfc_decoders);
1525 list_add_tail(&mpeg1_dec.list, &mfc_decoders);
1526 list_add_tail(&mpeg2_dec.list, &mfc_decoders);
1527 list_add_tail(&h263_dec.list, &mfc_decoders);
1528 list_add_tail(&vc1rcv_dec.list, &mfc_decoders);
1529 list_add_tail(&fimv1_dec.list, &mfc_decoders);
1530 list_add_tail(&fimv2_dec.list, &mfc_decoders);
1531 list_add_tail(&fimv3_dec.list, &mfc_decoders);
1532 list_add_tail(&fimv4_dec.list, &mfc_decoders);
1537 static int mfc_set_decoder(struct mfc_inst_ctx *ctx, SSBSIP_MFC_CODEC_TYPE codectype)
1539 struct list_head *pos;
1540 struct mfc_dec_info *decoder;
1541 struct mfc_dec_ctx *dec_ctx;
1545 /* find and set codec private */
1546 list_for_each(pos, &mfc_decoders) {
1547 decoder = list_entry(pos, struct mfc_dec_info, list);
1549 if (decoder->codectype == codectype) {
1550 if (decoder->codecid < 0)
1553 /* Allocate Decoder context memory */
1554 dec_ctx = kzalloc(sizeof(struct mfc_dec_ctx), GFP_KERNEL);
1556 mfc_err("failed to allocate codec private\n");
1559 ctx->c_priv = dec_ctx;
1561 /* Allocate Decoder context private memory */
1562 dec_ctx->d_priv = kzalloc(decoder->d_priv_size, GFP_KERNEL);
1563 if (!dec_ctx->d_priv) {
1564 mfc_err("failed to allocate decoder private\n");
1570 ctx->codecid = decoder->codecid;
1571 ctx->type = DECODER;
1572 ctx->c_ops = (struct codec_operations *)&decoder->c_ops;
1578 if (ctx->codecid < 0)
1579 mfc_err("couldn't find proper decoder codec type: %d\n", codectype);
1581 return ctx->codecid;
1584 static void mfc_set_stream_info(
1585 struct mfc_inst_ctx *ctx,
1591 if (ctx->buf_cache_type == CACHE) {
1592 flush_all_cpu_caches();
1596 write_reg(addr, MFC_SI_CH1_ES_ADR);
1597 write_reg(size, MFC_SI_CH1_ES_SIZE);
1599 /* FIXME: IOCTL_MFC_GET_IN_BUF size */
1600 write_reg(MFC_CPB_SIZE, MFC_SI_CH1_CPB_SIZE);
1602 write_reg(ctx->descbufofs, MFC_SI_CH1_DESC_ADR);
1603 write_reg(ctx->descbufsize, MFC_SI_CH1_DESC_SIZE);
1605 /* FIXME: right position */
1606 write_shm(ctx, ofs, START_BYTE_NUM);
1609 int mfc_init_decoding(struct mfc_inst_ctx *ctx, union mfc_args *args)
1611 struct mfc_dec_init_arg *init_arg = (struct mfc_dec_init_arg *)args;
1612 struct mfc_dec_ctx *dec_ctx = NULL;
1613 struct mfc_pre_cfg *precfg;
1614 struct list_head *pos, *nxt;
1617 ret = mfc_set_decoder(ctx, init_arg->in_codec_type);
1619 mfc_err("failed to setup decoder codec\n");
1620 ret = MFC_DEC_INIT_FAIL;
1621 goto err_codec_setup;
1624 dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
1626 dec_ctx->streamaddr = init_arg->in_strm_buf;
1627 dec_ctx->streamsize = init_arg->in_strm_size;
1629 mfc_dbg("stream size: %d", init_arg->in_strm_size);
1631 dec_ctx->crc = init_arg->in_crc;
1632 dec_ctx->pixelcache = init_arg->in_pixelcache;
1634 mfc_warn("Slice Mode disabled forcefully\n");
1635 dec_ctx->numextradpb = init_arg->in_numextradpb;
1636 dec_ctx->dpbflush = 0;
1637 dec_ctx->ispackedpb = init_arg->in_packed_PB;
1640 * assign pre configuration values to instance context
1642 list_for_each_safe(pos, nxt, &ctx->presetcfgs) {
1643 precfg = list_entry(pos, struct mfc_pre_cfg, list);
1645 if (ctx->c_ops->set_codec_cfg) {
1646 ret = ctx->c_ops->set_codec_cfg(ctx, precfg->type, precfg->value);
1648 mfc_warn("cannot set preset config type: 0x%08x: %d",
1653 mfc_set_inst_state(ctx, INST_STATE_SETUP);
1656 * allocate context buffer
1658 if (ctx->c_ops->alloc_ctx_buf) {
1659 if (ctx->c_ops->alloc_ctx_buf(ctx) < 0) {
1660 ret = MFC_DEC_INIT_FAIL;
1665 /* [crc, pixelcache] */
1666 ret = mfc_cmd_inst_open(ctx);
1670 mfc_set_inst_state(ctx, INST_STATE_OPEN);
1672 if (init_shm(ctx) < 0) {
1673 ret = MFC_DEC_INIT_FAIL;
1678 * allocate descriptor buffer
1680 if (ctx->c_ops->alloc_desc_buf) {
1681 if (ctx->c_ops->alloc_desc_buf(ctx) < 0) {
1682 ret = MFC_DEC_INIT_FAIL;
1688 * execute pre sequence start operation
1691 if (ctx->c_ops->pre_seq_start) {
1692 if (ctx->c_ops->pre_seq_start(ctx) < 0) {
1693 ret = MFC_DEC_INIT_FAIL;
1698 /* FIXME: postion */
1699 mfc_set_stream_info(ctx, mfc_mem_base_ofs(dec_ctx->streamaddr) >> 11,
1700 dec_ctx->streamsize, 0);
1702 ret = mfc_cmd_seq_start(ctx);
1707 if (ctx->c_ops->post_seq_start) {
1708 if (ctx->c_ops->post_seq_start(ctx) < 0) {
1709 ret = MFC_DEC_INIT_FAIL;
1714 if (ctx->c_ops->set_init_arg) {
1715 if (ctx->c_ops->set_init_arg(ctx, (void *)init_arg) < 0) {
1716 ret = MFC_DEC_INIT_FAIL;
1721 mfc_dbg("H: %d, W: %d, DPB_Count: %d", ctx->width, ctx->height,
1722 dec_ctx->numtotaldpb);
1724 #ifdef CONFIG_CPU_FREQ
1725 /* Fix MFC & Bus Frequency for High resolution for better performance */
1726 if (ctx->width >= 1920 || ctx->height >= 1080) {
1727 if (atomic_read(&ctx->dev->busfreq_lock_cnt) == 0) {
1728 /* For fixed MFC & Bus Freq to 160 & 266 MHz for 1080p Contents */
1730 if (ctx->codecid == H264_DEC) {
1731 s5pv310_busfreq_lock(DVFS_LOCK_ID_MFC, BUS_L0);
1732 mfc_dbg("[%s] Bus Freq Locked L0!\n", __func__);
1734 s5pv310_busfreq_lock(DVFS_LOCK_ID_MFC, BUS_L1);
1735 mfc_dbg("[%s] Bus Freq Locked L1!\n", __func__);
1739 atomic_inc(&ctx->dev->busfreq_lock_cnt);
1740 ctx->busfreq_flag = true;
1745 * allocate & set codec buffers
1747 if (ctx->c_ops->set_codec_bufs) {
1748 if (ctx->c_ops->set_codec_bufs(ctx) < 0) {
1749 ret = MFC_DEC_INIT_FAIL;
1750 goto err_codec_bufs;
1755 * allocate & set DPBs
1757 if (ctx->c_ops->set_dpbs) {
1758 if (ctx->c_ops->set_dpbs(ctx) < 0) {
1759 ret = MFC_DEC_INIT_FAIL;
1764 ret = mfc_cmd_init_buffers(ctx);
1768 mfc_set_inst_state(ctx, INST_STATE_INIT);
1770 while (!list_empty(&ctx->presetcfgs)) {
1771 precfg = list_entry((&ctx->presetcfgs)->next,
1772 struct mfc_pre_cfg, list);
1774 mfc_dbg("remove used preset config [0x%08x]\n",
1777 list_del(&precfg->list);
1780 INIT_LIST_HEAD(&ctx->presetcfgs);
1787 mfc_free_buf_type(ctx->id, MBT_DPB);
1790 mfc_free_buf_type(ctx->id, MBT_CODEC);
1793 #ifdef CONFIG_BUSFREQ
1794 /* Release MFC & Bus Frequency lock for High resolution */
1795 if (ctx->busfreq_flag == true) {
1796 atomic_dec(&ctx->dev->busfreq_lock_cnt);
1797 ctx->busfreq_flag = false;
1799 if (atomic_read(&ctx->dev->busfreq_lock_cnt) == 0) {
1800 exynos4_busfreq_lock_free(DVFS_LOCK_ID_MFC);
1801 mfc_dbg("Bus FREQ released\n");
1811 dump_stream(dec_ctx->streamaddr, dec_ctx->streamsize);
1815 mfc_free_buf_type(ctx->id, MBT_DESC);
1818 mfc_free_buf_type(ctx->id, MBT_SHM);
1824 mfc_cmd_inst_close(ctx);
1826 ctx->state = INST_STATE_SETUP;
1829 mfc_free_buf_type(ctx->id, MBT_CTX);
1832 if (dec_ctx->d_priv)
1833 kfree(dec_ctx->d_priv);
1842 ctx->state = INST_STATE_CREATE;
1848 int mfc_change_resolution(struct mfc_inst_ctx *ctx, struct mfc_dec_exe_arg *exe_arg)
1852 mfc_free_buf_type(ctx->id, MBT_DPB);
1854 ret = mfc_cmd_seq_start(ctx);
1859 if (ctx->c_ops->post_seq_start) {
1860 if (ctx->c_ops->post_seq_start(ctx) < 0)
1861 return MFC_DEC_INIT_FAIL;
1864 exe_arg->out_img_width = ctx->width;
1865 exe_arg->out_img_height = ctx->height;
1866 exe_arg->out_buf_width = ALIGN(ctx->width, ALIGN_W);
1867 exe_arg->out_buf_height = ALIGN(ctx->height, ALIGN_H);
1870 * allocate & set DPBs
1872 if (ctx->c_ops->set_dpbs) {
1873 if (ctx->c_ops->set_dpbs(ctx) < 0)
1874 return MFC_DEC_INIT_FAIL;
1877 ret = mfc_cmd_init_buffers(ctx);
1884 int mfc_check_resolution_change(struct mfc_inst_ctx *ctx, struct mfc_dec_exe_arg *exe_arg)
1888 if (exe_arg->out_display_status != DISP_S_DECODING)
1891 resol_status = (read_reg(MFC_SI_DISPLAY_STATUS) >> DISP_RC_SHIFT) & DISP_RC_MASK;
1893 if (resol_status == DISP_RC_INC || resol_status == DISP_RC_DEC) {
1894 ctx->resolution_status = RES_SET_CHANGE;
1895 mfc_dbg("Change Resolution status: %d\n", resol_status);
1901 static int mfc_decoding_frame(struct mfc_inst_ctx *ctx, struct mfc_dec_exe_arg *exe_arg, int *consumed)
1903 int start_ofs = *consumed;
1904 int display_luma_addr;
1905 int display_chroma_addr;
1906 int display_frame_type;
1907 int display_frame_tag;
1908 unsigned char *stream_vir;
1911 struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
1913 #ifdef CONFIG_VIDEO_MFC_VCM_UMP
1916 /* Check Frame Start code */
1917 stream_vir = phys_to_virt(exe_arg->in_strm_buf + start_ofs);
1918 ret = CheckDecStartCode(stream_vir, exe_arg->in_strm_size,
1919 exe_arg->in_codec_type);
1921 mfc_err("Frame Check start Code Failed\n");
1922 /* FIXME: Need to define proper error */
1923 return MFC_FRM_BUF_SIZE_FAIL;
1927 write_shm(ctx, dec_ctx->frametag, SET_FRAME_TAG);
1930 write_reg(0xFFFFFFFF, MFC_SI_CH1_RELEASE_BUF);
1931 if (dec_ctx->dpbflush){
1933 reg = read_reg(MFC_SI_CH1_DPB_CONF_CTRL);
1936 write_reg(reg, MFC_SI_CH1_DPB_CONF_CTRL); /* for DPB Flush*/
1937 /*clear dbp flush in context*/
1938 dec_ctx->dpbflush = 0;
1941 /* FIXME: postion */
1942 mfc_set_stream_info(ctx, mfc_mem_base_ofs(exe_arg->in_strm_buf) >> 11,
1943 exe_arg->in_strm_size, start_ofs);
1945 /* lastframe: mfc_dec_cfg */
1946 ret = mfc_cmd_frame_start(ctx);
1950 /* update display status information */
1951 dec_ctx->dispstatus = read_reg(MFC_SI_DISPLAY_STATUS) & DISP_S_MASK;
1953 /* get decode status, frame type */
1954 dec_ctx->decstatus = read_reg(MFC_SI_DECODE_STATUS) & DEC_S_MASK;
1955 dec_ctx->decframetype = read_reg(MFC_SI_FRAME_TYPE) & DEC_FRM_MASK;
1957 if (dec_ctx->dispstatus == DISP_S_DECODING) {
1958 display_luma_addr = 0;
1959 display_chroma_addr = 0;
1961 display_frame_type = DISP_FRM_X;
1962 display_frame_tag = read_shm(ctx, GET_FRAME_TAG_TOP);
1964 display_luma_addr = read_reg(MFC_SI_DISPLAY_Y_ADR);
1965 display_chroma_addr = read_reg(MFC_SI_DISPLAY_C_ADR);
1967 display_frame_type = get_disp_frame_type();
1968 display_frame_tag = read_shm(ctx, GET_FRAME_TAG_TOP);
1970 if (dec_ctx->ispackedpb) {
1971 if ((dec_ctx->decframetype == DEC_FRM_P) || (dec_ctx->decframetype == DEC_FRM_I)) {
1972 if (display_frame_type == DISP_FRM_N)
1973 display_frame_type = dec_ctx->predispframetype;
1975 display_luma_addr = dec_ctx->predisplumaaddr;
1976 display_chroma_addr = dec_ctx->predispchromaaddr;
1977 display_frame_type = dec_ctx->predispframetype;
1978 /* over write frame tag */
1979 display_frame_tag = dec_ctx->predispframetag;
1982 /* save the display addr */
1983 dec_ctx->predisplumaaddr = read_reg(MFC_SI_DISPLAY_Y_ADR);
1984 dec_ctx->predispchromaaddr = read_reg(MFC_SI_DISPLAY_C_ADR);
1986 /* save the display frame type */
1987 if (get_disp_frame_type() != DISP_FRM_N) {
1988 dec_ctx->predispframetype = get_disp_frame_type();
1990 dec_ctx->predispframetag =
1991 read_shm(ctx, GET_FRAME_TAG_TOP);
1994 mfc_dbg("pre_luma_addr: 0x%08x, pre_chroma_addr:"
1995 "0x%08x, pre_disp_frame_type: %d\n",
1996 (dec_ctx->predisplumaaddr << 11),
1997 (dec_ctx->predispchromaaddr << 11),
1998 dec_ctx->predispframetype);
2002 /* handle ImmeidatelyDisplay for Seek, I frame only */
2003 if (dec_ctx->immediatelydisplay) {
2004 mfc_dbg("Immediately display\n");
2005 dec_ctx->dispstatus = dec_ctx->decstatus;
2006 /* update frame tag information with current ID */
2007 exe_arg->out_frametag_top = dec_ctx->frametag;
2008 /* FIXME : need to check this */
2009 exe_arg->out_frametag_bottom = 0;
2011 if (dec_ctx->decstatus == DEC_S_DD) {
2012 mfc_dbg("Immediately display status: DEC_S_DD\n");
2013 display_luma_addr = read_reg(MFC_SI_DECODE_Y_ADR);
2014 display_chroma_addr = read_reg(MFC_SI_DECODE_C_ADR);
2017 display_frame_type = dec_ctx->decframetype;
2019 /* clear Immediately Display in decode context */
2020 dec_ctx->immediatelydisplay = 0;
2022 /* Get Frame Tag top and bottom */
2023 exe_arg->out_frametag_top = display_frame_tag;
2024 exe_arg->out_frametag_bottom = read_shm(ctx, GET_FRAME_TAG_BOT);
2027 mfc_dbg("decode y: 0x%08x, c: 0x%08x\n",
2028 read_reg(MFC_SI_DECODE_Y_ADR) << 11,
2029 read_reg(MFC_SI_DECODE_C_ADR) << 11);
2031 exe_arg->out_display_status = dec_ctx->dispstatus;
2033 exe_arg->out_display_Y_addr = (display_luma_addr << 11);
2034 exe_arg->out_display_C_addr = (display_chroma_addr << 11);
2036 exe_arg->out_disp_pic_frame_type = display_frame_type;
2038 exe_arg->out_y_offset = mfc_mem_data_ofs(display_luma_addr << 11, 1);
2039 exe_arg->out_c_offset = mfc_mem_data_ofs(display_chroma_addr << 11, 1);
2041 #if defined(CONFIG_VIDEO_MFC_VCM_UMP)
2042 exe_arg->out_y_secure_id = 0;
2043 exe_arg->out_c_secure_id = 0;
2045 ump_handle = mfc_get_buf_ump_handle(out_display_Y_addr << 11);
2046 if (ump_handle != NULL)
2047 exe_arg->out_y_secure_id = mfc_ump_get_id(ump_handle);
2049 ump_handle = mfc_get_buf_ump_handle(out_display_C_addr << 11);
2050 if (ump_handle != NULL)
2051 exe_arg->out_c_secure_id = mfc_ump_get_id(ump_handle);
2053 mfc_dbg("secure IDs Y: 0x%08x, C:0x%08x\n", exe_arg->out_y_secure_id,
2054 exe_arg->out_c_secure_id);
2055 #elif defined(CONFIG_S5P_VMEM)
2056 exe_arg->out_y_cookie = s5p_getcookie((void *)(out_display_Y_addr << 11));
2057 exe_arg->out_c_cookie = s5p_getcookie((void *)(out_display_C_addr << 11));
2059 mfc_dbg("cookie Y: 0x%08x, C:0x%08x\n", exe_arg->out_y_cookie,
2060 exe_arg->out_c_cookie);
2063 exe_arg->out_pic_time_top = read_shm(ctx, PIC_TIME_TOP);
2064 exe_arg->out_pic_time_bottom = read_shm(ctx, PIC_TIME_BOT);
2066 exe_arg->out_consumed_byte = read_reg(MFC_SI_FRM_COUNT);
2068 if (ctx->codecid == H264_DEC) {
2069 exe_arg->out_crop_right_offset = (read_shm(ctx, CROP_INFO1) >> 16) & 0xFFFF;
2070 exe_arg->out_crop_left_offset = read_shm(ctx, CROP_INFO1) & 0xFFFF;
2071 exe_arg->out_crop_bottom_offset = (read_shm(ctx, CROP_INFO2) >> 16) & 0xFFFF;
2072 exe_arg->out_crop_top_offset = read_shm(ctx, CROP_INFO2) & 0xFFFF;
2074 mfc_dbg("crop info t: %d, r: %d, b: %d, l: %d\n",
2075 exe_arg->out_crop_top_offset,
2076 exe_arg->out_crop_right_offset,
2077 exe_arg->out_crop_bottom_offset,
2078 exe_arg->out_crop_left_offset);
2081 mfc_dbg("decode frame type: %d\n", dec_ctx->decframetype);
2082 mfc_dbg("display frame type: %d\n", exe_arg->out_disp_pic_frame_type);
2083 mfc_dbg("display y: 0x%08x, c: 0x%08x\n",
2084 exe_arg->out_display_Y_addr, exe_arg->out_display_C_addr);
2087 mfc_dbg("decode frame type: %d\n", dec_ctx->decframetype);
2088 mfc_dbg("display frame type: %d,%d\n",
2089 exe_arg->out_disp_pic_frame_type,
2090 exe_arg->out_frametag_top);
2091 mfc_dbg("display y: 0x%08x, c: 0x%08x\n",
2092 exe_arg->out_display_Y_addr,
2093 exe_arg->out_display_C_addr);
2095 *consumed = read_reg(MFC_SI_FRM_COUNT);
2096 mfc_dbg("stream size: %d, consumed: %d\n",
2097 exe_arg->in_strm_size, *consumed);
2102 int mfc_exec_decoding(struct mfc_inst_ctx *ctx, union mfc_args *args)
2104 struct mfc_dec_exe_arg *exe_arg;
2107 struct mfc_dec_ctx *dec_ctx = (struct mfc_dec_ctx *)ctx->c_priv;
2108 int sec_try_tag; /* tag store for second try */
2110 exe_arg = (struct mfc_dec_exe_arg *)args;
2112 /* set pre-decoding informations */
2113 dec_ctx->streamaddr = exe_arg->in_strm_buf;
2114 dec_ctx->streamsize = exe_arg->in_strm_size;
2115 dec_ctx->frametag = exe_arg->in_frametag;
2116 dec_ctx->immediatelydisplay = exe_arg->in_immediately_disp;
2118 mfc_set_inst_state(ctx, INST_STATE_EXE);
2120 ret = mfc_decoding_frame(ctx, exe_arg, &consumed);
2121 sec_try_tag = exe_arg->out_frametag_top;
2123 mfc_set_inst_state(ctx, INST_STATE_EXE_DONE);
2126 mfc_check_resolution_change(ctx, exe_arg);
2127 if (ctx->resolution_status == RES_SET_CHANGE) {
2128 ret = mfc_decoding_frame(ctx, exe_arg, &consumed);
2129 } else if ((ctx->resolution_status == RES_WAIT_FRAME_DONE) &&
2130 (exe_arg->out_display_status == DISP_S_FINISH)) {
2131 exe_arg->out_display_status = 4;
2132 mfc_change_resolution(ctx, exe_arg);
2133 ctx->resolution_status = RES_NO_CHANGE;
2136 if ((dec_ctx->ispackedpb) &&
2137 (dec_ctx->decframetype == DEC_FRM_P) &&
2138 (exe_arg->in_strm_size - consumed > 4)) {
2139 unsigned char *stream_vir;
2142 mfc_dbg("[%s] strmsize : %d consumed : %d\n", __func__,
2143 exe_arg->in_strm_size, consumed);
2145 stream_vir = phys_to_virt(exe_arg->in_strm_buf);
2147 mfc_mem_cache_inv((void *)stream_vir,
2148 exe_arg->in_strm_size);
2150 offset = CheckMPEG4StartCode(stream_vir+consumed,
2151 dec_ctx->streamsize - consumed);
2155 exe_arg->in_strm_size -= consumed;
2156 dec_ctx->frametag = exe_arg->in_frametag;
2157 dec_ctx->immediatelydisplay =
2158 exe_arg->in_immediately_disp;
2160 mfc_set_inst_state(ctx, INST_STATE_EXE);
2162 ret = mfc_decoding_frame(ctx, exe_arg, &consumed);
2163 exe_arg->out_frametag_top = sec_try_tag;
2165 mfc_set_inst_state(ctx, INST_STATE_EXE_DONE);
2170 if (ctx->c_ops->set_dpbs) {
2171 if (ctx->c_ops->set_dpbs(ctx) < 0)
2172 return MFC_DEC_INIT_FAIL;