drivers/media/video/s5p-tv/regs-hdmi.h

   1 /* linux/arch/arm/mach-s5pv310/include/mach/regs-hdmi.h
   2  *
   3  * Copyright (c) 2010 Samsung Electronics
   4  * http://www.samsung.com/
   5  *
   6  * HDMI register header file for Samsung TVOUT driver
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #ifndef __ASM_ARCH_REGS_HDMI_H
  14
  15 /*
  16  * Register part
  17 */
  18 #define HDMI_CTRL_BASE(x)                       (x)
  19 #define HDMI_BASE(x)                            ((x) + 0x00010000)
  20 #define HDMI_SPDIF_BASE(x)                      ((x) + 0x00030000)
  21 #define HDMI_I2S_BASE(x)                        ((x) + 0x00040000)
  22 #define HDMI_TG_BASE(x)                         ((x) + 0x00050000)
  23 #define HDMI_EFUSE_BASE(x)                      ((x) + 0x00060000)
  24
  25
  26 /* Interrupt Control Register */
  27 #define HDMI_INTC_CON                   HDMI_CTRL_BASE(0x0000)
  28 /* Interrupt Flag Register */
  29 #define HDMI_INTC_FLAG                  HDMI_CTRL_BASE(0x0004)
  30 /* HDCP KEY Status */
  31 #define HDMI_HDCP_KEY_LOAD                      HDMI_CTRL_BASE(0x0008)
  32 /* HPD signal */
  33 #define HDMI_HPD_STATUS                 HDMI_CTRL_BASE(0x000C)
  34 /* Audio system clock selection */
  35 #define HDMI_AUDIO_CLKSEL                       HDMI_CTRL_BASE(0x0010)
  36 /* HDMI PHY Reset Out */
  37 #define HDMI_PHY_RSTOUT                 HDMI_CTRL_BASE(0x0014)
  38 /* HDMI PHY VPLL Monitor */
  39 #define HDMI_PHY_VPLL                   HDMI_CTRL_BASE(0x0018)
  40 /* HDMI PHY CMU Monitor */
  41 #define HDMI_PHY_CMU                    HDMI_CTRL_BASE(0x001C)
  42 /* HDMI TX Core S/W reset */
  43 #define HDMI_CORE_RSTOUT                        HDMI_CTRL_BASE(0x0020)
  44
  45 /* HDMI System Control Register 0 0x00 */
  46 #define HDMI_CON_0                              HDMI_BASE(0x0000)
  47 /* HDMI System Control Register 1 0x00 */
  48 #define HDMI_CON_1                              HDMI_BASE(0x0004)
  49 /* HDMI System Control Register 2. 0x00 */
  50 #define HDMI_CON_2                              HDMI_BASE(0x0008)
  51 /* HDMI System Status Register 0x00 */
  52 #define HDMI_SYS_STATUS                 HDMI_BASE(0x0010)
  53 /* HDMI Phy Status */
  54 #define HDMI_PHY_STATUS                 HDMI_BASE(0x0014)
  55 /* HDMI System Status Enable Register 0x00 */
  56 #define HDMI_STATUS_EN                  HDMI_BASE(0x0020)
  57 /* Hot Plug Detection Control Register 0x00 */
  58 #define HDMI_HPD                                HDMI_BASE(0x0030)
  59 /* HDMI/DVI Mode Selection 0x00 */
  60 #define HDMI_MODE_SEL                   HDMI_BASE(0x0040)
  61 /* HDCP Encryption Enable Register 0x00 */
  62 #define HDMI_ENC_EN                             HDMI_BASE(0x0044)
  63
  64 /* Pixel Values for Blue Screen 0x00 */
  65 #define HDMI_BLUE_SCREEN_0                      HDMI_BASE(0x0050)
  66 /* Pixel Values for Blue Screen 0x00 */
  67 #define HDMI_BLUE_SCREEN_1                      HDMI_BASE(0x0054)
  68 /* Pixel Values for Blue Screen 0x00 */
  69 #define HDMI_BLUE_SCREEN_2                      HDMI_BASE(0x0058)
  70
  71 /* Maximum Y (or R,G,B) Pixel Value 0xEB */
  72 #define HDMI_YMAX                               HDMI_BASE(0x0060)
  73 /* Minimum Y (or R,G,B) Pixel Value 0x10 */
  74 #define HDMI_YMIN                               HDMI_BASE(0x0064)
  75 /* Maximum Cb/ Cr Pixel Value 0xF0 */
  76 #define HDMI_CMAX                               HDMI_BASE(0x0068)
  77 /* Minimum Cb/ Cr Pixel Value 0x10 */
  78 #define HDMI_CMIN                               HDMI_BASE(0x006C)
  79
  80 /* Horizontal Blanking Setting 0x00 */
  81 #define HDMI_H_BLANK_0                  HDMI_BASE(0x00A0)
  82 /* Horizontal Blanking Setting 0x00 */
  83 #define HDMI_H_BLANK_1                  HDMI_BASE(0x00A4)
  84 /* Vertical Blanking Setting 0x00 */
  85 #define HDMI_V_BLANK_0                  HDMI_BASE(0x00B0)
  86 /* Vertical Blanking Setting 0x00 */
  87 #define HDMI_V_BLANK_1                  HDMI_BASE(0x00B4)
  88 /* Vertical Blanking Setting 0x00 */
  89 #define HDMI_V_BLANK_2                  HDMI_BASE(0x00B8)
  90 /* Hori. Line and Ver. Line 0x00 */
  91 #define HDMI_H_V_LINE_0                 HDMI_BASE(0x00C0)
  92 /* Hori. Line and Ver. Line 0x00 */
  93 #define HDMI_H_V_LINE_1                 HDMI_BASE(0x00C4)
  94 /* Hori. Line and Ver. Line 0x00 */
  95 #define HDMI_H_V_LINE_2                 HDMI_BASE(0x00C8)
  96
  97 /* Vertical Sync Polarity Control Register 0x00 */
  98 #define HDMI_SYNC_MODE                  HDMI_BASE(0x00E4)
  99 /* Vertical Sync Polarity Control Register 0x00 */
 100 #define HDMI_VSYNC_POL                  HDMI_BASE(0x00E4)
 101 /* Interlace/ Progressive Control Register 0x00 */
 102 #define HDMI_INT_PRO_MODE                       HDMI_BASE(0x00E8)
 103
 104 /* Vertical Blanking Setting for Bottom Field 0x00 */
 105 #define HDMI_V_BLANK_F_0                        HDMI_BASE(0x0110)
 106 /* Vertical Blanking Setting for Bottom Field 0x00 */
 107 #define HDMI_V_BLANK_F_1                        HDMI_BASE(0x0114)
 108 /* Vertical Blanking Setting for Bottom Field 0x00 */
 109 #define HDMI_V_BLANK_F_2                        HDMI_BASE(0x0118)
 110 /* Horizontal Sync Generation Setting 0x00 */
 111 #define HDMI_H_SYNC_GEN_0                       HDMI_BASE(0x0120)
 112 /* Horizontal Sync Generation Setting 0x00 */
 113 #define HDMI_H_SYNC_GEN_1                       HDMI_BASE(0x0124)
 114 /* Horizontal Sync Generation Setting 0x00 */
 115 #define HDMI_H_SYNC_GEN_2                       HDMI_BASE(0x0128)
 116 /* Vertical Sync Generation for Top Field or Frame. 0x01 */
 117 #define HDMI_V_SYNC_GEN_1_0                     HDMI_BASE(0x0130)
 118 /* Vertical Sync Generation for Top Field or Frame. 0x10 */
 119 #define HDMI_V_SYNC_GEN_1_1                     HDMI_BASE(0x0134)
 120 /* Vertical Sync Generation for Top Field or Frame. 0x00 */
 121 #define HDMI_V_SYNC_GEN_1_2                     HDMI_BASE(0x0138)
 122 /* Vertical Sync Generation for Bottom field ? Vertical position. 0x01 */
 123 #define HDMI_V_SYNC_GEN_2_0                     HDMI_BASE(0x0140)
 124 /* Vertical Sync Generation for Bottom field ? Vertical position. 0x10 */
 125 #define HDMI_V_SYNC_GEN_2_1                     HDMI_BASE(0x0144)
 126 /* Vertical Sync Generation for Bottom field ? Vertical position. 0x00 */
 127 #define HDMI_V_SYNC_GEN_2_2                     HDMI_BASE(0x0148)
 128 /* Vertical Sync Generation for Bottom field ? Horizontal position. 0x01 */
 129 #define HDMI_V_SYNC_GEN_3_0                     HDMI_BASE(0x0150)
 130 /* Vertical Sync Generation for Bottom field ? Horizontal position. 0x10 */
 131 #define HDMI_V_SYNC_GEN_3_1                     HDMI_BASE(0x0154)
 132 /* Vertical Sync Generation for Bottom field ? Horizontal position. 0x00 */
 133 #define HDMI_V_SYNC_GEN_3_2                     HDMI_BASE(0x0158)
 134
 135 /* ASP Packet Control Register 0x00 */
 136 #define HDMI_ASP_CON                    HDMI_BASE(0x0160)
 137 /* ASP Packet sp_flat Bit Control 0x00 */
 138 #define HDMI_ASP_SP_FLAT                        HDMI_BASE(0x0164)
 139 /* ASP Audio Channel Configuration 0x04 */
 140 #define HDMI_ASP_CHCFG0                 HDMI_BASE(0x0170)
 141 /* ASP Audio Channel Configuration 0x1A */
 142 #define HDMI_ASP_CHCFG1                 HDMI_BASE(0x0174)
 143 /* ASP Audio Channel Configuration 0x2C */
 144 #define HDMI_ASP_CHCFG2                 HDMI_BASE(0x0178)
 145 /* ASP Audio Channel Configuration 0x3E */
 146 #define HDMI_ASP_CHCFG3                 HDMI_BASE(0x017C)
 147
 148 /* ACR Packet Control Register 0x00 */
 149 #define HDMI_ACR_CON                    HDMI_BASE(0x0180)
 150 /* Measured CTS Value 0x01 */
 151 #define HDMI_ACR_MCTS0                  HDMI_BASE(0x0184)
 152 /* Measured CTS Value 0x00 */
 153 #define HDMI_ACR_MCTS1                  HDMI_BASE(0x0188)
 154 /* Measured CTS Value 0x00 */
 155 #define HDMI_ACR_MCTS2                  HDMI_BASE(0x018C)
 156 /* CTS Value for Fixed CTS Transmission Mode. 0xE8 */
 157 #define HDMI_ACR_CTS0                   HDMI_BASE(0x0190)
 158 /* CTS Value for Fixed CTS Transmission Mode. 0x03 */
 159 #define HDMI_ACR_CTS1                   HDMI_BASE(0x0194)
 160 /* CTS Value for Fixed CTS Transmission Mode. 0x00 */
 161 #define HDMI_ACR_CTS2                   HDMI_BASE(0x0198)
 162 /* N Value for ACR Packet. 0xE8 */
 163 #define HDMI_ACR_N0                             HDMI_BASE(0x01A0)
 164 /* N Value for ACR Packet. 0x03 */
 165 #define HDMI_ACR_N1                             HDMI_BASE(0x01A4)
 166 /* N Value for ACR Packet. 0x00 */
 167 #define HDMI_ACR_N2                             HDMI_BASE(0x01A8)
 168 /* Altenate LSB for Fixed CTS Transmission Mode 0x00 */
 169 #define HDMI_ACR_LSB2                   HDMI_BASE(0x01B0)
 170 /* Number of ACR Packet Transmission per frame 0x1F */
 171 #define HDMI_ACR_TXCNT                  HDMI_BASE(0x01B4)
 172 /* Interval for ACR Packet Transmission 0x63 */
 173 #define HDMI_ACR_TXINTERVAL                     HDMI_BASE(0x01B8)
 174 /* CTS Offset for Measured CTS mode. 0x00 */
 175 #define HDMI_ACR_CTS_OFFSET                     HDMI_BASE(0x01BC)
 176
 177 /* ACR Packet Control register 0x00 */
 178 #define HDMI_GCP_CON                    HDMI_BASE(0x01C0)
 179 /* GCP Packet Body 0x00 */
 180 #define HDMI_GCP_BYTE1                  HDMI_BASE(0x01D0)
 181 /* GCP Packet Body 0x01 */
 182 #define HDMI_GCP_BYTE2                  HDMI_BASE(0x01D4)
 183 /* GCP Packet Body 0x02 */
 184 #define HDMI_GCP_BYTE3                  HDMI_BASE(0x01D8)
 185
 186 /* ACP Packet Control register 0x00 */
 187 #define HDMI_ACP_CON                    HDMI_BASE(0x01E0)
 188 /* ACP Packet Header 0x00 */
 189 #define HDMI_ACP_TYPE                   HDMI_BASE(0x01E4)
 190
 191 /* ACP Packet Body 0x00 */
 192 #define HDMI_ACP_DATA0                  HDMI_BASE(0x0200)
 193 /* ACP Packet Body 0x00 */
 194 #define HDMI_ACP_DATA1                  HDMI_BASE(0x0204)
 195 /* ACP Packet Body 0x00 */
 196 #define HDMI_ACP_DATA2                  HDMI_BASE(0x0208)
 197 /* ACP Packet Body 0x00 */
 198 #define HDMI_ACP_DATA3                  HDMI_BASE(0x020c)
 199 /* ACP Packet Body 0x00 */
 200 #define HDMI_ACP_DATA4                  HDMI_BASE(0x0210)
 201 /* ACP Packet Body 0x00 */
 202 #define HDMI_ACP_DATA5                  HDMI_BASE(0x0214)
 203 /* ACP Packet Body 0x00 */
 204 #define HDMI_ACP_DATA6                  HDMI_BASE(0x0218)
 205 /* ACP Packet Body 0x00 */
 206 #define HDMI_ACP_DATA7                  HDMI_BASE(0x021c)
 207 /* ACP Packet Body 0x00 */
 208 #define HDMI_ACP_DATA8                  HDMI_BASE(0x0220)
 209 /* ACP Packet Body 0x00 */
 210 #define HDMI_ACP_DATA9                  HDMI_BASE(0x0224)
 211 /* ACP Packet Body 0x00 */
 212 #define HDMI_ACP_DATA10                 HDMI_BASE(0x0228)
 213 /* ACP Packet Body 0x00 */
 214 #define HDMI_ACP_DATA11                 HDMI_BASE(0x022c)
 215 /* ACP Packet Body 0x00 */
 216 #define HDMI_ACP_DATA12                 HDMI_BASE(0x0230)
 217 /* ACP Packet Body 0x00 */
 218 #define HDMI_ACP_DATA13                 HDMI_BASE(0x0234)
 219 /* ACP Packet Body 0x00 */
 220 #define HDMI_ACP_DATA14                 HDMI_BASE(0x0238)
 221 /* ACP Packet Body 0x00 */
 222 #define HDMI_ACP_DATA15                 HDMI_BASE(0x023c)
 223 /* ACP Packet Body 0x00 */
 224 #define HDMI_ACP_DATA16                 HDMI_BASE(0x0240)
 225
 226 /* ACR Packet Control Register 0x00 */
 227 #define HDMI_ISRC_CON                   HDMI_BASE(0x0250)
 228 /* ISCR1 Packet Header 0x00 */
 229 #define HDMI_ISRC1_HEADER1                      HDMI_BASE(0x0264)
 230
 231 /* ISRC1 Packet Body 0x00 */
 232 #define HDMI_ISRC1_DATA0                        HDMI_BASE(0x0270)
 233 /* ISRC1 Packet Body 0x00 */
 234 #define HDMI_ISRC1_DATA1                        HDMI_BASE(0x0274)
 235 /* ISRC1 Packet Body 0x00 */
 236 #define HDMI_ISRC1_DATA2                        HDMI_BASE(0x0278)
 237 /* ISRC1 Packet Body 0x00 */
 238 #define HDMI_ISRC1_DATA3                        HDMI_BASE(0x027c)
 239 /* ISRC1 Packet Body 0x00 */
 240 #define HDMI_ISRC1_DATA4                        HDMI_BASE(0x0280)
 241 /* ISRC1 Packet Body 0x00 */
 242 #define HDMI_ISRC1_DATA5                        HDMI_BASE(0x0284)
 243 /* ISRC1 Packet Body 0x00 */
 244 #define HDMI_ISRC1_DATA6                        HDMI_BASE(0x0288)
 245 /* ISRC1 Packet Body 0x00 */
 246 #define HDMI_ISRC1_DATA7                        HDMI_BASE(0x028c)
 247 /* ISRC1 Packet Body 0x00 */
 248 #define HDMI_ISRC1_DATA8                        HDMI_BASE(0x0290)
 249 /* ISRC1 Packet Body 0x00 */
 250 #define HDMI_ISRC1_DATA9                        HDMI_BASE(0x0294)
 251 /* ISRC1 Packet Body 0x00 */
 252 #define HDMI_ISRC1_DATA10                       HDMI_BASE(0x0298)
 253 /* ISRC1 Packet Body 0x00 */
 254 #define HDMI_ISRC1_DATA11                       HDMI_BASE(0x029c)
 255 /* ISRC1 Packet Body 0x00 */
 256 #define HDMI_ISRC1_DATA12                       HDMI_BASE(0x02a0)
 257 /* ISRC1 Packet Body 0x00 */
 258 #define HDMI_ISRC1_DATA13                       HDMI_BASE(0x02a4)
 259 /* ISRC1 Packet Body 0x00 */
 260 #define HDMI_ISRC1_DATA14                       HDMI_BASE(0x02a8)
 261 /* ISRC1 Packet Body 0x00 */
 262 #define HDMI_ISRC1_DATA15                       HDMI_BASE(0x02ac)
 263
 264 /* ISRC2 Packet Body 0x00 */
 265 #define HDMI_ISRC2_DATA0                        HDMI_BASE(0x02b0)
 266 /* ISRC2 Packet Body 0x00 */
 267 #define HDMI_ISRC2_DATA1                        HDMI_BASE(0x02b4)
 268 /* ISRC2 Packet Body 0x00 */
 269 #define HDMI_ISRC2_DATA2                        HDMI_BASE(0x02b8)
 270 /* ISRC2 Packet Body 0x00 */
 271 #define HDMI_ISRC2_DATA3                        HDMI_BASE(0x02bc)
 272 /* ISRC2 Packet Body 0x00 */
 273 #define HDMI_ISRC2_DATA4                        HDMI_BASE(0x02c0)
 274 /* ISRC2 Packet Body 0x00 */
 275 #define HDMI_ISRC2_DATA5                        HDMI_BASE(0x02c4)
 276 /* ISRC2 Packet Body 0x00 */
 277 #define HDMI_ISRC2_DATA6                        HDMI_BASE(0x02c8)
 278 /* ISRC2 Packet Body 0x00 */
 279 #define HDMI_ISRC2_DATA7                        HDMI_BASE(0x02cc)
 280 /* ISRC2 Packet Body 0x00 */
 281 #define HDMI_ISRC2_DATA8                        HDMI_BASE(0x02d0)
 282 /* ISRC2 Packet Body 0x00 */
 283 #define HDMI_ISRC2_DATA9                        HDMI_BASE(0x02d4)
 284 /* ISRC2 Packet Body 0x00 */
 285 #define HDMI_ISRC2_DATA10                       HDMI_BASE(0x02d8)
 286 /* ISRC2 Packet Body 0x00 */
 287 #define HDMI_ISRC2_DATA11                       HDMI_BASE(0x02dc)
 288 /* ISRC2 Packet Body 0x00 */
 289 #define HDMI_ISRC2_DATA12                       HDMI_BASE(0x02e0)
 290 /* ISRC2 Packet Body 0x00 */
 291 #define HDMI_ISRC2_DATA13                       HDMI_BASE(0x02e4)
 292 /* ISRC2 Packet Body 0x00 */
 293 #define HDMI_ISRC2_DATA14                       HDMI_BASE(0x02e8)
 294 /* ISRC2 Packet Body 0x00 */
 295 #define HDMI_ISRC2_DATA15                       HDMI_BASE(0x02ec)
 296
 297 /* AVI Packet Control Register 0x00 */
 298 #define HDMI_AVI_CON                    HDMI_BASE(0x0300)
 299 /* AVI Packet Checksum 0x00 */
 300 #define HDMI_AVI_CHECK_SUM                      HDMI_BASE(0x0310)
 301
 302 /* AVI Packet Body 0x00 */
 303 #define HDMI_AVI_BYTE1                  HDMI_BASE(0x0320)
 304 /* AVI Packet Body 0x00 */
 305 #define HDMI_AVI_BYTE2                  HDMI_BASE(0x0324)
 306 /* AVI Packet Body 0x00 */
 307 #define HDMI_AVI_BYTE3                  HDMI_BASE(0x0328)
 308 /* AVI Packet Body 0x00 */
 309 #define HDMI_AVI_BYTE4                  HDMI_BASE(0x032c)
 310 /* AVI Packet Body 0x00 */
 311 #define HDMI_AVI_BYTE5                  HDMI_BASE(0x0330)
 312 /* AVI Packet Body 0x00 */
 313 #define HDMI_AVI_BYTE6                  HDMI_BASE(0x0334)
 314 /* AVI Packet Body 0x00 */
 315 #define HDMI_AVI_BYTE7                  HDMI_BASE(0x0338)
 316 /* AVI Packet Body 0x00 */
 317 #define HDMI_AVI_BYTE8                  HDMI_BASE(0x033c)
 318 /* AVI Packet Body 0x00 */
 319 #define HDMI_AVI_BYTE9                  HDMI_BASE(0x0340)
 320 /* AVI Packet Body 0x00 */
 321 #define HDMI_AVI_BYTE10                 HDMI_BASE(0x0344)
 322 /* AVI Packet Body 0x00 */
 323 #define HDMI_AVI_BYTE11                 HDMI_BASE(0x0348)
 324 /* AVI Packet Body 0x00 */
 325 #define HDMI_AVI_BYTE12                 HDMI_BASE(0x034c)
 326 /* AVI Packet Body 0x00  */
 327 #define HDMI_AVI_BYTE13                 HDMI_BASE(0x0350)
 328
 329 /* AUI Packet Control Register 0x00 */
 330 #define HDMI_AUI_CON                    HDMI_BASE(0x0360)
 331 /* AUI Packet Checksum 0x00 */
 332 #define HDMI_AUI_CHECK_SUM                      HDMI_BASE(0x0370)
 333
 334 /* AUI Packet Body 0x00 */
 335 #define HDMI_AUI_BYTE1                  HDMI_BASE(0x0380)
 336 /* AUI Packet Body 0x00 */
 337 #define HDMI_AUI_BYTE2                  HDMI_BASE(0x0384)
 338 /* AUI Packet Body 0x00 */
 339 #define HDMI_AUI_BYTE3                  HDMI_BASE(0x0388)
 340 /* AUI Packet Body 0x00 */
 341 #define HDMI_AUI_BYTE4                  HDMI_BASE(0x038c)
 342 /* AUI Packet Body 0x00 */
 343 #define HDMI_AUI_BYTE5                  HDMI_BASE(0x0390)
 344
 345 /* ACR Packet Control Register 0x00 */
 346 #define HDMI_MPG_CON                    HDMI_BASE(0x03A0)
 347 /* MPG Packet Checksum 0x00 */
 348 #define HDMI_MPG_CHECK_SUM                      HDMI_BASE(0x03B0)
 349
 350 /* MPEG Packet Body 0x00 */
 351 #define HDMI_MPEG_BYTE1                 HDMI_BASE(0x03c0)
 352 /* MPEG Packet Body 0x00 */
 353 #define HDMI_MPEG_BYTE2                 HDMI_BASE(0x03c4)
 354 /* MPEG Packet Body 0x00 */
 355 #define HDMI_MPEG_BYTE3                 HDMI_BASE(0x03c8)
 356 /* MPEG Packet Body 0x00 */
 357 #define HDMI_MPEG_BYTE4                 HDMI_BASE(0x03cc)
 358 /* MPEG Packet Body 0x00 */
 359 #define HDMI_MPEG_BYTE5                 HDMI_BASE(0x03d0)
 360
 361 /* SPD Packet Control Register 0x00 */
 362 #define HDMI_SPD_CON                    HDMI_BASE(0x0400)
 363 /* SPD Packet Header 0x00 */
 364 #define HDMI_SPD_HEADER0                        HDMI_BASE(0x0410)
 365 /* SPD Packet Header 0x00 */
 366 #define HDMI_SPD_HEADER1                        HDMI_BASE(0x0414)
 367 /* SPD Packet Header 0x00 */
 368 #define HDMI_SPD_HEADER2                        HDMI_BASE(0x0418)
 369
 370 /* SPD Packet Body 0x00 */
 371 #define HDMI_SPD_DATA0                  HDMI_BASE(0x0420)
 372 /* SPD Packet Body 0x00 */
 373 #define HDMI_SPD_DATA1                  HDMI_BASE(0x0424)
 374 /* SPD Packet Body 0x00 */
 375 #define HDMI_SPD_DATA2                  HDMI_BASE(0x0428)
 376 /* SPD Packet Body 0x00 */
 377 #define HDMI_SPD_DATA3                  HDMI_BASE(0x042c)
 378 /* SPD Packet Body 0x00 */
 379 #define HDMI_SPD_DATA4                  HDMI_BASE(0x0430)
 380 /* SPD Packet Body 0x00 */
 381 #define HDMI_SPD_DATA5                  HDMI_BASE(0x0434)
 382 /* SPD Packet Body 0x00 */
 383 #define HDMI_SPD_DATA6                  HDMI_BASE(0x0438)
 384 /* SPD Packet Body 0x00 */
 385 #define HDMI_SPD_DATA7                  HDMI_BASE(0x043c)
 386 /* SPD Packet Body 0x00 */
 387 #define HDMI_SPD_DATA8                  HDMI_BASE(0x0440)
 388 /* SPD Packet Body 0x00 */
 389 #define HDMI_SPD_DATA9                  HDMI_BASE(0x0444)
 390 /* SPD Packet Body 0x00 */
 391 #define HDMI_SPD_DATA10                 HDMI_BASE(0x0448)
 392 /* SPD Packet Body 0x00 */
 393 #define HDMI_SPD_DATA11                 HDMI_BASE(0x044c)
 394 /* SPD Packet Body 0x00 */
 395 #define HDMI_SPD_DATA12                 HDMI_BASE(0x0450)
 396 /* SPD Packet Body 0x00 */
 397 #define HDMI_SPD_DATA13                 HDMI_BASE(0x0454)
 398 /* SPD Packet Body 0x00 */
 399 #define HDMI_SPD_DATA14                 HDMI_BASE(0x0458)
 400 /* SPD Packet Body 0x00 */
 401 #define HDMI_SPD_DATA15                 HDMI_BASE(0x045c)
 402 /* SPD Packet Body 0x00 */
 403 #define HDMI_SPD_DATA16                 HDMI_BASE(0x0460)
 404 /* SPD Packet Body 0x00 */
 405 #define HDMI_SPD_DATA17                 HDMI_BASE(0x0464)
 406 /* SPD Packet Body 0x00 */
 407 #define HDMI_SPD_DATA18                 HDMI_BASE(0x0468)
 408 /* SPD Packet Body 0x00 */
 409 #define HDMI_SPD_DATA19                 HDMI_BASE(0x046c)
 410 /* SPD Packet Body 0x00 */
 411 #define HDMI_SPD_DATA20                 HDMI_BASE(0x0470)
 412 /* SPD Packet Body 0x00 */
 413 #define HDMI_SPD_DATA21                 HDMI_BASE(0x0474)
 414 /* SPD Packet Body 0x00 */
 415 #define HDMI_SPD_DATA22                 HDMI_BASE(0x0478)
 416 /* SPD Packet Body 0x00 */
 417 #define HDMI_SPD_DATA23                 HDMI_BASE(0x048c)
 418 /* SPD Packet Body 0x00 */
 419 #define HDMI_SPD_DATA24                 HDMI_BASE(0x0480)
 420 /* SPD Packet Body 0x00 */
 421 #define HDMI_SPD_DATA25                 HDMI_BASE(0x0484)
 422 /* SPD Packet Body 0x00 */
 423 #define HDMI_SPD_DATA26                 HDMI_BASE(0x0488)
 424 /* SPD Packet Body 0x00 */
 425 #define HDMI_SPD_DATA27                 HDMI_BASE(0x048c)
 426
 427 /* SHA-1 Value from Repeater 0x00 */
 428 #define HDMI_HDCP_RX_SHA1_0_0           HDMI_BASE(0x0600)
 429 /* SHA-1 Value from Repeater 0x00 */
 430 #define HDMI_HDCP_RX_SHA1_0_1           HDMI_BASE(0x0604)
 431 /* SHA-1 value from Repeater 0x00 */
 432 #define HDMI_HDCP_RX_SHA1_0_2           HDMI_BASE(0x0608)
 433 /* SHA-1 value from Repeater 0x00 */
 434 #define HDMI_HDCP_RX_SHA1_0_3           HDMI_BASE(0x060C)
 435 /* SHA-1 value from Repeater 0x00 */
 436 #define HDMI_HDCP_RX_SHA1_1_0           HDMI_BASE(0x0610)
 437 /* SHA-1 value from Repeater 0x00 */
 438 #define HDMI_HDCP_RX_SHA1_1_1           HDMI_BASE(0x0614)
 439 /* SHA-1 value from Repeater 0x00 */
 440 #define HDMI_HDCP_RX_SHA1_1_2           HDMI_BASE(0x0618)
 441 /* SHA-1 value from Repeater 0x00 */
 442 #define HDMI_HDCP_RX_SHA1_1_3           HDMI_BASE(0x061C)
 443 /* SHA-1 value from Repeater 0x00 */
 444 #define HDMI_HDCP_RX_SHA1_2_0           HDMI_BASE(0x0620)
 445 /* SHA-1 value from Repeater 0x00 */
 446 #define HDMI_HDCP_RX_SHA1_2_1           HDMI_BASE(0x0624)
 447 /* SHA-1 value from Repeater 0x00 */
 448 #define HDMI_HDCP_RX_SHA1_2_2           HDMI_BASE(0x0628)
 449 /* SHA-1 value from Repeater 0x00 */
 450 #define HDMI_HDCP_RX_SHA1_2_3           HDMI_BASE(0x062C)
 451 /* SHA-1 value from Repeater 0x00 */
 452 #define HDMI_HDCP_RX_SHA1_3_0           HDMI_BASE(0x0630)
 453 /* SHA-1 value from Repeater 0x00 */
 454 #define HDMI_HDCP_RX_SHA1_3_1           HDMI_BASE(0x0634)
 455 /* SHA-1 value from Repeater 0x00 */
 456 #define HDMI_HDCP_RX_SHA1_3_2           HDMI_BASE(0x0638)
 457 /* SHA-1 value from Repeater 0x00 */
 458 #define HDMI_HDCP_RX_SHA1_3_3           HDMI_BASE(0x063C)
 459 /* SHA-1 value from Repeater 0x00 */
 460 #define HDMI_HDCP_RX_SHA1_4_0           HDMI_BASE(0x0640)
 461 /* SHA-1 value from Repeater 0x00 */
 462 #define HDMI_HDCP_RX_SHA1_4_1           HDMI_BASE(0x0644)
 463 /* SHA-1 value from Repeater 0x00 */
 464 #define HDMI_HDCP_RX_SHA1_4_2           HDMI_BASE(0x0648)
 465 /* SHA-1 value from Repeater 0x00 */
 466 #define HDMI_HDCP_RX_SHA1_4_3           HDMI_BASE(0x064C)
 467
 468 /* Receiver KSV 0 0x00 */
 469 #define HDMI_HDCP_RX_KSV_0_0            HDMI_BASE(0x0650)
 470 /* Receiver KSV 0 0x00 */
 471 #define HDMI_HDCP_RX_KSV_0_1            HDMI_BASE(0x0654)
 472 /* Receiver KSV 0 0x00 */
 473 #define HDMI_HDCP_RX_KSV_0_2            HDMI_BASE(0x0658)
 474 /* Receiver KSV 0 0x00 */
 475 #define HDMI_HDCP_RX_KSV_0_3            HDMI_BASE(0x065C)
 476 /* Receiver KSV 1 0x00 */
 477 #define HDMI_HDCP_RX_KSV_0_4            HDMI_BASE(0x0660)
 478
 479 /* Receiver KSV 1 0x00 */
 480 #define HDMI_HDCP_KSV_LIST_CON          HDMI_BASE(0x0664)
 481 /* 2nd authentication status 0x00 */
 482 #define HDMI_HDCP_SHA_RESULT            HDMI_BASE(0x0670)
 483 /* HDCP Control 0x00 */
 484 #define HDMI_HDCP_CTRL1                 HDMI_BASE(0x0680)
 485 /* HDCP Control 0x00 */
 486 #define HDMI_HDCP_CTRL2                 HDMI_BASE(0x0684)
 487 /* HDCP Ri, Pj, V result 0x00 */
 488 #define HDMI_HDCP_CHECK_RESULT          HDMI_BASE(0x0690)
 489
 490 /* Receiver BKSV 0x00 */
 491 #define HDMI_HDCP_BKSV_0_0                      HDMI_BASE(0x06A0)
 492 /* Receiver BKSV 0x00 */
 493 #define HDMI_HDCP_BKSV_0_1                      HDMI_BASE(0x06A4)
 494 /* Receiver BKSV 0x00 */
 495 #define HDMI_HDCP_BKSV_0_2                      HDMI_BASE(0x06A8)
 496 /* Receiver BKSV 0x00 */
 497 #define HDMI_HDCP_BKSV_0_3                      HDMI_BASE(0x06AC)
 498 /* Receiver BKSV 0x00 */
 499 #define HDMI_HDCP_BKSV_1                        HDMI_BASE(0x06B0)
 500
 501 /* Transmitter AKSV 0x00 */
 502 #define HDMI_HDCP_AKSV_0_0                      HDMI_BASE(0x06C0)
 503 /* Transmitter AKSV 0x00 */
 504 #define HDMI_HDCP_AKSV_0_1                      HDMI_BASE(0x06C4)
 505 /* Transmitter AKSV 0x00 */
 506 #define HDMI_HDCP_AKSV_0_2                      HDMI_BASE(0x06C8)
 507 /* Transmitter AKSV 0x00 */
 508 #define HDMI_HDCP_AKSV_0_3                      HDMI_BASE(0x06CC)
 509 /* Transmitter AKSV 0x00 */
 510 #define HDMI_HDCP_AKSV_1                        HDMI_BASE(0x06D0)
 511
 512 /* Transmitter An 0x00 */
 513 #define HDMI_HDCP_An_0_0                        HDMI_BASE(0x06E0)
 514 /* Transmitter An 0x00 */
 515 #define HDMI_HDCP_An_0_1                        HDMI_BASE(0x06E4)
 516 /* Transmitter An 0x00 */
 517 #define HDMI_HDCP_An_0_2                        HDMI_BASE(0x06E8)
 518 /* Transmitter An 0x00 */
 519 #define HDMI_HDCP_An_0_3                        HDMI_BASE(0x06EC)
 520 /* Transmitter An 0x00 */
 521 #define HDMI_HDCP_An_1_0                        HDMI_BASE(0x06F0)
 522 /* Transmitter An 0x00 */
 523 #define HDMI_HDCP_An_1_1                        HDMI_BASE(0x06F4)
 524 /* Transmitter An 0x00 */
 525 #define HDMI_HDCP_An_1_2                        HDMI_BASE(0x06F8)
 526 /* Transmitter An 0x00 */
 527 #define HDMI_HDCP_An_1_3                        HDMI_BASE(0x06FC)
 528
 529 /* Receiver BCAPS 0x00 */
 530 #define HDMI_HDCP_BCAPS                 HDMI_BASE(0x0700)
 531 /* Receiver BSTATUS 0x00 */
 532 #define HDMI_HDCP_BSTATUS_0                     HDMI_BASE(0x0710)
 533 /* Receiver BSTATUS 0x00 */
 534 #define HDMI_HDCP_BSTATUS_1                     HDMI_BASE(0x0714)
 535 /* Transmitter Ri 0x00 */
 536 #define HDMI_HDCP_Ri_0                  HDMI_BASE(0x0740)
 537 /* Transmitter Ri 0x00 */
 538 #define HDMI_HDCP_Ri_1                  HDMI_BASE(0x0744)
 539
 540 /* HDCP I2C interrupt status */
 541 #define HDMI_HDCP_I2C_INT                       HDMI_BASE(0x0780)
 542 /* HDCP An interrupt status */
 543 #define HDMI_HDCP_AN_INT                        HDMI_BASE(0x0790)
 544 /* HDCP Watchdog interrupt status */
 545 #define HDMI_HDCP_WDT_INT                       HDMI_BASE(0x07a0)
 546 /* HDCP RI interrupt status */
 547 #define HDMI_HDCP_RI_INT                        HDMI_BASE(0x07b0)
 548
 549 /* HDCP Ri Interrupt Frame number index register 0 */
 550 #define HDMI_HDCP_RI_COMPARE_0          HDMI_BASE(0x07d0)
 551 /* HDCP Ri Interrupt Frame number index register 1 */
 552 #define HDMI_HDCP_RI_COMPARE_1          HDMI_BASE(0x07d4)
 553 /* Current value of the frame count index in the hardware */
 554 #define HDMI_HDCP_FRAME_COUNT           HDMI_BASE(0x07e0)
 555
 556 /* Gamut Metadata packet transmission control register */
 557 #define HDMI_GAMUT_CON                  HDMI_BASE(0x0500)
 558 /* Gamut metadata packet header */
 559 #define HDMI_GAMUT_HEADER0                      HDMI_BASE(0x0504)
 560 /* Gamut metadata packet header */
 561 #define HDMI_GAMUT_HEADER1                      HDMI_BASE(0x0508)
 562 /* Gamut metadata packet header */
 563 #define HDMI_GAMUT_HEADER2                      HDMI_BASE(0x050c)
 564 /* Gamut Metadata packet body data */
 565 #define HDMI_GAMUT_DATA00                       HDMI_BASE(0x0510)
 566 /* Gamut Metadata packet body data */
 567 #define HDMI_GAMUT_DATA01                       HDMI_BASE(0x0514)
 568 /* Gamut Metadata packet body data */
 569 #define HDMI_GAMUT_DATA02                       HDMI_BASE(0x0518)
 570 /* Gamut Metadata packet body data */
 571 #define HDMI_GAMUT_DATA03                       HDMI_BASE(0x051c)
 572 /* Gamut Metadata packet body data */
 573 #define HDMI_GAMUT_DATA04                       HDMI_BASE(0x0520)
 574 /* Gamut Metadata packet body data */
 575 #define HDMI_GAMUT_DATA05                       HDMI_BASE(0x0524)
 576 /* Gamut Metadata packet body data */
 577 #define HDMI_GAMUT_DATA06                       HDMI_BASE(0x0528)
 578 /* Gamut Metadata packet body data */
 579 #define HDMI_GAMUT_DATA07                       HDMI_BASE(0x052c)
 580 /* Gamut Metadata packet body data */
 581 #define HDMI_GAMUT_DATA08                       HDMI_BASE(0x0530)
 582 /* Gamut Metadata packet body data */
 583 #define HDMI_GAMUT_DATA09                       HDMI_BASE(0x0534)
 584 /* Gamut Metadata packet body data */
 585 #define HDMI_GAMUT_DATA10                       HDMI_BASE(0x0538)
 586 /* Gamut Metadata packet body data */
 587 #define HDMI_GAMUT_DATA11                       HDMI_BASE(0x053c)
 588 /* Gamut Metadata packet body data */
 589 #define HDMI_GAMUT_DATA12                       HDMI_BASE(0x0540)
 590 /* Gamut Metadata packet body data */
 591 #define HDMI_GAMUT_DATA13                       HDMI_BASE(0x0544)
 592 /* Gamut Metadata packet body data */
 593 #define HDMI_GAMUT_DATA14                       HDMI_BASE(0x0548)
 594 /* Gamut Metadata packet body data */
 595 #define HDMI_GAMUT_DATA15                       HDMI_BASE(0x054c)
 596 /* Gamut Metadata packet body data */
 597 #define HDMI_GAMUT_DATA16                       HDMI_BASE(0x0550)
 598 /* Gamut Metadata packet body data */
 599 #define HDMI_GAMUT_DATA17                       HDMI_BASE(0x0554)
 600 /* Gamut Metadata packet body data */
 601 #define HDMI_GAMUT_DATA18                       HDMI_BASE(0x0558)
 602 /* Gamut Metadata packet body data */
 603 #define HDMI_GAMUT_DATA19                       HDMI_BASE(0x055c)
 604 /* Gamut Metadata packet body data */
 605 #define HDMI_GAMUT_DATA20                       HDMI_BASE(0x0560)
 606 /* Gamut Metadata packet body data */
 607 #define HDMI_GAMUT_DATA21                       HDMI_BASE(0x0564)
 608 /* Gamut Metadata packet body data */
 609 #define HDMI_GAMUT_DATA22                       HDMI_BASE(0x0568)
 610 /* Gamut Metadata packet body data */
 611 #define HDMI_GAMUT_DATA23                       HDMI_BASE(0x056c)
 612 /* Gamut Metadata packet body data */
 613 #define HDMI_GAMUT_DATA24                       HDMI_BASE(0x0570)
 614 /* Gamut Metadata packet body data */
 615 #define HDMI_GAMUT_DATA25                       HDMI_BASE(0x0574)
 616 /* Gamut Metadata packet body data */
 617 #define HDMI_GAMUT_DATA26                       HDMI_BASE(0x0578)
 618 /* Gamut Metadata packet body data */
 619 #define HDMI_GAMUT_DATA27                       HDMI_BASE(0x057c)
 620
 621 /* Gamut Metadata packet body data */
 622 #define HDMI_DC_CONTROL                 HDMI_BASE(0x05C0)
 623 /* Gamut Metadata packet body data */
 624 #define HDMI_VIDEO_PATTERN_GEN          HDMI_BASE(0x05C4)
 625 /* Gamut Metadata packet body data */
 626 #define HDMI_HPD_GEN                    HDMI_BASE(0x05C8)
 627
 628
 629 /* SPDIFIN_CLK_CTRL [1:0] 0x02 */
 630 #define HDMI_SPDIFIN_CLK_CTRL           HDMI_SPDIF_BASE(0x0000)
 631 /* SPDIFIN_OP_CTRL [1:0] 0x00 */
 632 #define HDMI_SPDIFIN_OP_CTRL            HDMI_SPDIF_BASE(0x0004)
 633 /* SPDIFIN_IRQ_MASK[7:0] 0x00 */
 634 #define HDMI_SPDIFIN_IRQ_MASK           HDMI_SPDIF_BASE(0x0008)
 635 /* SPDIFIN_IRQ_STATUS [7:0] 0x00 */
 636 #define HDMI_SPDIFIN_IRQ_STATUS         HDMI_SPDIF_BASE(0x000C)
 637 /* SPDIFIN_CONFIG [7:0] 0x00 */
 638 #define HDMI_SPDIFIN_CONFIG_1           HDMI_SPDIF_BASE(0x0010)
 639 /* SPDIFIN_CONFIG [11:8] 0x00 */
 640 #define HDMI_SPDIFIN_CONFIG_2           HDMI_SPDIF_BASE(0x0014)
 641 /* SPDIFIN_USER_VALUE [7:0] 0x00 */
 642 #define HDMI_SPDIFIN_USER_VALUE_1               HDMI_SPDIF_BASE(0x0020)
 643 /* SPDIFIN_USER_VALUE [15:8] 0x00 */
 644 #define HDMI_SPDIFIN_USER_VALUE_2               HDMI_SPDIF_BASE(0x0024)
 645 /* SPDIFIN_USER_VALUE [23:16] 0x00 */
 646 #define HDMI_SPDIFIN_USER_VALUE_3               HDMI_SPDIF_BASE(0x0028)
 647 /* SPDIFIN_USER_VALUE [31:24] 0x00 */
 648 #define HDMI_SPDIFIN_USER_VALUE_4               HDMI_SPDIF_BASE(0x002C)
 649 /* SPDIFIN_CH_STATUS_0 [7:0] 0x00 */
 650 #define HDMI_SPDIFIN_CH_STATUS_0_1              HDMI_SPDIF_BASE(0x0030)
 651 /* SPDIFIN_CH_STATUS_0 [15:8] 0x00 */
 652 #define HDMI_SPDIFIN_CH_STATUS_0_2              HDMI_SPDIF_BASE(0x0034)
 653 /* SPDIFIN_CH_STATUS_0 [23:16] 0x00 */
 654 #define HDMI_SPDIFIN_CH_STATUS_0_3              HDMI_SPDIF_BASE(0x0038)
 655 /* SPDIFIN_CH_STATUS_0 [31:24] 0x00 */
 656 #define HDMI_SPDIFIN_CH_STATUS_0_4              HDMI_SPDIF_BASE(0x003C)
 657 /* SPDIFIN_CH_STATUS_1 0x00 */
 658 #define HDMI_SPDIFIN_CH_STATUS_1                HDMI_SPDIF_BASE(0x0040)
 659 /* SPDIF_FRAME_PERIOD [7:0] 0x00 */
 660 #define HDMI_SPDIFIN_FRAME_PERIOD_1             HDMI_SPDIF_BASE(0x0048)
 661 /* SPDIF_FRAME_PERIOD [15:8] 0x00 */
 662 #define HDMI_SPDIFIN_FRAME_PERIOD_2             HDMI_SPDIF_BASE(0x004C)
 663 /* SPDIFIN_Pc_INFO [7:0] 0x00 */
 664 #define HDMI_SPDIFIN_Pc_INFO_1          HDMI_SPDIF_BASE(0x0050)
 665 /* SPDIFIN_Pc_INFO [15:8] 0x00 */
 666 #define HDMI_SPDIFIN_Pc_INFO_2          HDMI_SPDIF_BASE(0x0054)
 667 /* SPDIFIN_Pd_INFO [7:0] 0x00 */
 668 #define HDMI_SPDIFIN_Pd_INFO_1          HDMI_SPDIF_BASE(0x0058)
 669 /* SPDIFIN_Pd_INFO [15:8] 0x00 */
 670 #define HDMI_SPDIFIN_Pd_INFO_2          HDMI_SPDIF_BASE(0x005C)
 671 /* SPDIFIN_DATA_BUF_0 [7:0] 0x00 */
 672 #define HDMI_SPDIFIN_DATA_BUF_0_1               HDMI_SPDIF_BASE(0x0060)
 673 /* SPDIFIN_DATA_BUF_0 [15:8] 0x00 */
 674 #define HDMI_SPDIFIN_DATA_BUF_0_2               HDMI_SPDIF_BASE(0x0064)
 675 /* SPDIFIN_DATA_BUF_0 [23:16] 0x00 */
 676 #define HDMI_SPDIFIN_DATA_BUF_0_3               HDMI_SPDIF_BASE(0x0068)
 677 /* SPDIFIN_DATA_BUF_0 [31:28] 0x00 */
 678 #define HDMI_SPDIFIN_USER_BUF_0         HDMI_SPDIF_BASE(0x006C)
 679 /* SPDIFIN_DATA_BUF_1 [7:0] 0x00 */
 680 #define HDMI_SPDIFIN_DATA_BUF_1_1               HDMI_SPDIF_BASE(0x0070)
 681 /* SPDIFIN_DATA_BUF_1 [15:8] 0x00 */
 682 #define HDMI_SPDIFIN_DATA_BUF_1_2               HDMI_SPDIF_BASE(0x0074)
 683 /* SPDIFIN_DATA_BUF_1 [23:16] 0x00 */
 684 #define HDMI_SPDIFIN_DATA_BUF_1_3               HDMI_SPDIF_BASE(0x0078)
 685 /* SPDIFIN_DATA_BUF_1 [31:28] 0x00 */
 686 #define HDMI_SPDIFIN_USER_BUF_1         HDMI_SPDIF_BASE(0x007C)
 687
 688
 689 /* I2S Clock Enable Register0x00  */
 690 #define HDMI_I2S_CLK_CON                        HDMI_I2S_BASE(0x0000)
 691 /* I2S Control Register 10x00  */
 692 #define HDMI_I2S_CON_1                  HDMI_I2S_BASE(0x0004)
 693 /* I2S Control Register 20x00  */
 694 #define HDMI_I2S_CON_2                  HDMI_I2S_BASE(0x0008)
 695 /* I2S Input Pin Selection Register 0 0x77  */
 696 #define HDMI_I2S_PIN_SEL_0                      HDMI_I2S_BASE(0x000C)
 697 /* I2S Input Pin Selection Register 1 0x77  */
 698 #define HDMI_I2S_PIN_SEL_1                      HDMI_I2S_BASE(0x0010)
 699 /* I2S Input Pin Selection Register 2 0x77  */
 700 #define HDMI_I2S_PIN_SEL_2                      HDMI_I2S_BASE(0x0014)
 701 /* I2S Input Pin Selection Register 30x07  */
 702 #define HDMI_I2S_PIN_SEL_3                      HDMI_I2S_BASE(0x0018)
 703 /* I2S DSD Control Register0x02  */
 704 #define HDMI_I2S_DSD_CON                        HDMI_I2S_BASE(0x001C)
 705 /* I2S In/Mux Control Register 0x60  */
 706 #define HDMI_I2S_MUX_CON                        HDMI_I2S_BASE(0x0020)
 707 /* I2S Channel Status Control Register0x00  */
 708 #define HDMI_I2S_CH_ST_CON                      HDMI_I2S_BASE(0x0024)
 709 /* I2S Channel Status Block 00x00  */
 710 #define HDMI_I2S_CH_ST_0                        HDMI_I2S_BASE(0x0028)
 711 /* I2S Channel Status Block 10x00  */
 712 #define HDMI_I2S_CH_ST_1                        HDMI_I2S_BASE(0x002C)
 713 /* I2S Channel Status Block 20x00  */
 714 #define HDMI_I2S_CH_ST_2                        HDMI_I2S_BASE(0x0030)
 715 /* I2S Channel Status Block 30x00  */
 716 #define HDMI_I2S_CH_ST_3                        HDMI_I2S_BASE(0x0034)
 717 /* I2S Channel Status Block 40x00  */
 718 #define HDMI_I2S_CH_ST_4                        HDMI_I2S_BASE(0x0038)
 719 /* I2S Channel Status Block Shadow Register 00x00  */
 720 #define HDMI_I2S_CH_ST_SH_0                     HDMI_I2S_BASE(0x003C)
 721 /* I2S Channel Status Block Shadow Register 10x00  */
 722 #define HDMI_I2S_CH_ST_SH_1                     HDMI_I2S_BASE(0x0040)
 723 /* I2S Channel Status Block Shadow Register 20x00  */
 724 #define HDMI_I2S_CH_ST_SH_2                     HDMI_I2S_BASE(0x0044)
 725 /* I2S Channel Status Block Shadow Register 30x00  */
 726 #define HDMI_I2S_CH_ST_SH_3                     HDMI_I2S_BASE(0x0048)
 727 /* I2S Channel Status Block Shadow Register 40x00  */
 728 #define HDMI_I2S_CH_ST_SH_4                     HDMI_I2S_BASE(0x004C)
 729 /* I2S Audio Sample Validity Register0x00  */
 730 #define HDMI_I2S_VD_DATA                        HDMI_I2S_BASE(0x0050)
 731 /* I2S Channel Enable Register0x03  */
 732 #define HDMI_I2S_MUX_CH                 HDMI_I2S_BASE(0x0054)
 733 /* I2S CUV Enable Register0x03  */
 734 #define HDMI_I2S_MUX_CUV                        HDMI_I2S_BASE(0x0058)
 735 /* I2S Interrupt Request Mask Register0x03  */
 736 #define HDMI_I2S_IRQ_MASK                       HDMI_I2S_BASE(0x005C)
 737 /* I2S Interrupt Request Status Register0x00  */
 738 #define HDMI_I2S_IRQ_STATUS                     HDMI_I2S_BASE(0x0060)
 739 /* I2S PCM Output Data Register0x00  */
 740 #define HDMI_I2S_CH0_L_0                        HDMI_I2S_BASE(0x0064)
 741 /* I2S PCM Output Data Register0x00  */
 742 #define HDMI_I2S_CH0_L_1                        HDMI_I2S_BASE(0x0068)
 743 /* I2S PCM Output Data Register0x00  */
 744 #define HDMI_I2S_CH0_L_2                        HDMI_I2S_BASE(0x006C)
 745 /* I2S PCM Output Data Register0x00  */
 746 #define HDMI_I2S_CH0_L_3                        HDMI_I2S_BASE(0x0070)
 747 /* I2S PCM Output Data Register0x00  */
 748 #define HDMI_I2S_CH0_R_0                        HDMI_I2S_BASE(0x0074)
 749 /* I2S PCM Output Data Register0x00  */
 750 #define HDMI_I2S_CH0_R_1                        HDMI_I2S_BASE(0x0078)
 751 /* I2S PCM Output Data Register0x00  */
 752 #define HDMI_I2S_CH0_R_2                        HDMI_I2S_BASE(0x007C)
 753 /* I2S PCM Output Data Register0x00  */
 754 #define HDMI_I2S_CH0_R_3                        HDMI_I2S_BASE(0x0080)
 755 /* I2S PCM Output Data Register0x00  */
 756 #define HDMI_I2S_CH1_L_0                        HDMI_I2S_BASE(0x0084)
 757 /* I2S PCM Output Data Register0x00  */
 758 #define HDMI_I2S_CH1_L_1                        HDMI_I2S_BASE(0x0088)
 759 /* I2S PCM Output Data Register0x00  */
 760 #define HDMI_I2S_CH1_L_2                        HDMI_I2S_BASE(0x008C)
 761 /* I2S PCM Output Data Register0x00  */
 762 #define HDMI_I2S_CH1_L_3                        HDMI_I2S_BASE(0x0090)
 763 /* I2S PCM Output Data Register0x00  */
 764 #define HDMI_I2S_CH1_R_0                        HDMI_I2S_BASE(0x0094)
 765 /* I2S PCM Output Data Register0x00  */
 766 #define HDMI_I2S_CH1_R_1                        HDMI_I2S_BASE(0x0098)
 767 /* I2S PCM Output Data Register0x00  */
 768 #define HDMI_I2S_CH1_R_2                        HDMI_I2S_BASE(0x009C)
 769 /* I2S PCM Output Data Register0x00  */
 770 #define HDMI_I2S_CH1_R_3                        HDMI_I2S_BASE(0x00A0)
 771 /* I2S PCM Output Data Register0x00  */
 772 #define HDMI_I2S_CH2_L_0                        HDMI_I2S_BASE(0x00A4)
 773 /* I2S PCM Output Data Register0x00  */
 774 #define HDMI_I2S_CH2_L_1                        HDMI_I2S_BASE(0x00A8)
 775 /* I2S PCM Output Data Register0x00  */
 776 #define HDMI_I2S_CH2_L_2                        HDMI_I2S_BASE(0x00AC)
 777 /* I2S PCM Output Data Register0x00  */
 778 #define HDMI_I2S_CH2_L_3                        HDMI_I2S_BASE(0x00B0)
 779 /* I2S PCM Output Data Register0x00  */
 780 #define HDMI_I2S_CH2_R_0                        HDMI_I2S_BASE(0x00B4)
 781 /* I2S PCM Output Data Register0x00  */
 782 #define HDMI_I2S_CH2_R_1                        HDMI_I2S_BASE(0x00B8)
 783 /* I2S PCM Output Data Register0x00  */
 784 #define HDMI_I2S_CH2_R_2                        HDMI_I2S_BASE(0x00BC)
 785 /* I2S PCM Output Data Register0x00  */
 786 #define HDMI_I2S_Ch2_R_3                        HDMI_I2S_BASE(0x00C0)
 787 /* I2S PCM Output Data Register0x00  */
 788 #define HDMI_I2S_CH3_L_0                        HDMI_I2S_BASE(0x00C4)
 789 /* I2S PCM Output Data Register0x00  */
 790 #define HDMI_I2S_CH3_L_1                        HDMI_I2S_BASE(0x00C8)
 791 /* I2S PCM Output Data Register0x00  */
 792 #define HDMI_I2S_CH3_L_2                        HDMI_I2S_BASE(0x00CC)
 793 /* I2S PCM Output Data Register0x00  */
 794 #define HDMI_I2S_CH3_R_0                        HDMI_I2S_BASE(0x00D0)
 795 /* I2S PCM Output Data Register0x00  */
 796 #define HDMI_I2S_CH3_R_1                        HDMI_I2S_BASE(0x00D4)
 797 /* I2S PCM Output Data Register0x00  */
 798 #define HDMI_I2S_CH3_R_2                        HDMI_I2S_BASE(0x00D8)
 799 /* I2S CUV Output Data Register0x00  */
 800 #define HDMI_I2S_CUV_L_R                        HDMI_I2S_BASE(0x00DC)
 801
 802
 803 /* Command Register 0x00 */
 804 #define HDMI_TG_CMD                             HDMI_TG_BASE(0x0000)
 805 /* Horizontal Full Size 0x72 */
 806 #define HDMI_TG_H_FSZ_L                 HDMI_TG_BASE(0x0018)
 807 /* Horizontal Full Size 0x06 */
 808 #define HDMI_TG_H_FSZ_H                 HDMI_TG_BASE(0x001C)
 809 /* Horizontal Active Start 0x05 */
 810 #define HDMI_TG_HACT_ST_L                       HDMI_TG_BASE(0x0020)
 811 /* Horizontal Active Start 0x01 */
 812 #define HDMI_TG_HACT_ST_H                       HDMI_TG_BASE(0x0024)
 813 /* Horizontal Active Size 0x00 */
 814 #define HDMI_TG_HACT_SZ_L                       HDMI_TG_BASE(0x0028)
 815 /* Horizontal Active Size 0x05 */
 816 #define HDMI_TG_HACT_SZ_H                       HDMI_TG_BASE(0x002C)
 817 /* Vertical Full Line Size 0xEE */
 818 #define HDMI_TG_V_FSZ_L                 HDMI_TG_BASE(0x0030)
 819 /* Vertical Full Line Size 0x02 */
 820 #define HDMI_TG_V_FSZ_H                 HDMI_TG_BASE(0x0034)
 821 /* Vertical Sync Position 0x01 */
 822 #define HDMI_TG_VSYNC_L                 HDMI_TG_BASE(0x0038)
 823 /* Vertical Sync Position 0x00 */
 824 #define HDMI_TG_VSYNC_H                 HDMI_TG_BASE(0x003C)
 825 /* Vertical Sync Position for Bottom Field 0x33 */
 826 #define HDMI_TG_VSYNC2_L                        HDMI_TG_BASE(0x0040)
 827 /* Vertical Sync Position for Bottom Field 0x02 */
 828 #define HDMI_TG_VSYNC2_H                        HDMI_TG_BASE(0x0044)
 829 /* Vertical Sync Active Start Position 0x1a */
 830 #define HDMI_TG_VACT_ST_L                       HDMI_TG_BASE(0x0048)
 831 /* Vertical Sync Active Start Position 0x00 */
 832 #define HDMI_TG_VACT_ST_H                       HDMI_TG_BASE(0x004C)
 833 /* Vertical Active Size 0xd0 */
 834 #define HDMI_TG_VACT_SZ_L                       HDMI_TG_BASE(0x0050)
 835 /* Vertical Active Size 0x02 */
 836 #define HDMI_TG_VACT_SZ_H                       HDMI_TG_BASE(0x0054)
 837 /* Field Change Position 0x33 */
 838 #define HDMI_TG_FIELD_CHG_L                     HDMI_TG_BASE(0x0058)
 839 /* Field Change Position 0x02 */
 840 #define HDMI_TG_FIELD_CHG_H                     HDMI_TG_BASE(0x005C)
 841 /* Vertical Sync Active Start Position for Bottom Field 0x48 */
 842 #define HDMI_TG_VACT_ST2_L                      HDMI_TG_BASE(0x0060)
 843 /* Vertical Sync Active Start Position for Bottom Field 0x02 */
 844 #define HDMI_TG_VACT_ST2_H                      HDMI_TG_BASE(0x0064)
 845
 846 /* HDMI Vsync Positon for Top Field 0x01 */
 847 #define HDMI_TG_VSYNC_TOP_HDMI_L                HDMI_TG_BASE(0x0078)
 848 /* HDMI Vsync Positon for Top Field 0x00 */
 849 #define HDMI_TG_VSYNC_TOP_HDMI_H                HDMI_TG_BASE(0x007C)
 850 /* HDMI Vsync Positon for Bottom Field 0x33 */
 851 #define HDMI_TG_VSYNC_BOT_HDMI_L                HDMI_TG_BASE(0x0080)
 852 /* HDMI Vsync Positon for Bottom Field 0x02 */
 853 #define HDMI_TG_VSYNC_BOT_HDMI_H                HDMI_TG_BASE(0x0084)
 854 /* HDMI Top Field Start Position 0x01 */
 855 #define HDMI_TG_FIELD_TOP_HDMI_L                HDMI_TG_BASE(0x0088)
 856 /* HDMI Top Field Start Position 0x00 */
 857 #define HDMI_TG_FIELD_TOP_HDMI_H                HDMI_TG_BASE(0x008C)
 858 /* HDMI Bottom Field Start Position 0x33 */
 859 #define HDMI_TG_FIELD_BOT_HDMI_L                HDMI_TG_BASE(0x0090)
 860 /* HDMI Bottom Field Start Position 0x02 */
 861 #define HDMI_TG_FIELD_BOT_HDMI_H                HDMI_TG_BASE(0x0094)
 862
 863 #define HDMI_EFUSE_CTRL                 HDMI_EFUSE_BASE(0x0000)
 864 #define HDMI_EFUSE_STATUS                       HDMI_EFUSE_BASE(0x0004)
 865 #define HDMI_EFUSE_ADDR_WIDTH           HDMI_EFUSE_BASE(0x0008)
 866 #define HDMI_EFUSE_SIGDEV_ASSERT                HDMI_EFUSE_BASE(0x000c)
 867 #define HDMI_EFUSE_SIGDEV_DEASSERT              HDMI_EFUSE_BASE(0x0010)
 868 #define HDMI_EFUSE_PRCHG_ASSERT         HDMI_EFUSE_BASE(0x0014)
 869 #define HDMI_EFUSE_PRCHG_DEASSERT               HDMI_EFUSE_BASE(0x0018)
 870 #define HDMI_EFUSE_FSET_ASSERT          HDMI_EFUSE_BASE(0x001c)
 871 #define HDMI_EFUSE_FSET_DEASSERT                HDMI_EFUSE_BASE(0x0020)
 872 #define HDMI_EFUSE_SENSING                      HDMI_EFUSE_BASE(0x0024)
 873 #define HDMI_EFUSE_SCK_ASSERT           HDMI_EFUSE_BASE(0x0028)
 874 #define HDMI_EFUSE_SCK_DEASSERT         HDMI_EFUSE_BASE(0x002c)
 875 #define HDMI_EFUSE_SDOUT_OFFSET         HDMI_EFUSE_BASE(0x0030)
 876 #define HDMI_EFUSE_READ_OFFSET          HDMI_EFUSE_BASE(0x0034)
 877
 878 #define HDMI_AUI_SZ                             5
 879 #define HDMI_GCP_SZ                             3
 880 #define HDMI_SPD_SZ                             28
 881 #define HDMI_AVI_SZ                             13
 882 #define HDMI_MPG_SZ                             5
 883 #define HDMI_GMU_SX                             28
 884 #define HDMI_ISRC_SZ                    16
 885 #define HDMI_ACP_SZ                             17
 886
 887 /*
 888  * Bit definition part
 889  */
 890
 891 /* Control Register */
 892
 893 /* INTC_CON */
 894 #define HDMI_INTC_ACT_HI                        (1 << 7)
 895 #define HDMI_INTC_ACT_LOW                       (0 << 7)
 896 #define HDMI_INTC_EN_GLOBAL                     (1 << 6)
 897 #define HDMI_INTC_DIS_GLOBAL            (0 << 6)
 898 #define HDMI_INTC_EN_I2S                        (1 << 5)
 899 #define HDMI_INTC_DIS_I2S                       (0 << 5)
 900 #define HDMI_INTC_EN_CEC                        (1 << 4)
 901 #define HDMI_INTC_DIS_CEC                       (0 << 4)
 902 #define HDMI_INTC_EN_HPD_PLUG           (1 << 3)
 903 #define HDMI_INTC_DIS_HPD_PLUG          (0 << 3)
 904 #define HDMI_INTC_EN_HPD_UNPLUG         (1 << 2)
 905 #define HDMI_INTC_DIS_HPD_UNPLUG                (0 << 2)
 906 #define HDMI_INTC_EN_SPDIF                      (1 << 1)
 907 #define HDMI_INTC_DIS_SPDIF                     (0 << 1)
 908 #define HDMI_INTC_EN_HDCP                       (1 << 0)
 909 #define HDMI_INTC_DIS_HDCP                      (0 << 0)
 910
 911 /* INTC_FLAG */
 912 #define HDMI_INTC_FLAG_I2S                      (1 << 5)
 913 #define HDMI_INTC_FLAG_CEC                      (1 << 4)
 914 #define HDMI_INTC_FLAG_HPD_PLUG         (1 << 3)
 915 #define HDMI_INTC_FLAG_HPD_UNPLUG               (1 << 2)
 916 #define HDMI_INTC_FLAG_SPDIF            (1 << 1)
 917 #define HDMI_INTC_FLAG_HDCP                     (1 << 0)
 918
 919 /* HDCP_KEY_LOAD_DONE */
 920 #define HDMI_HDCP_KEY_LOAD_DONE         (1 << 0)
 921
 922 /* HPD_STATUS */
 923 #define HDMI_HPD_PLUGED                 (1 << 0)
 924
 925 /* AUDIO_CLKSEL */
 926 #define HDMI_AUDIO_SPDIF_CLK            (1 << 0)
 927 #define HDMI_AUDIO_PCLK                 (0 << 0)
 928
 929 /* HDMI_PHY_RSTOUT */
 930 #define HDMI_PHY_SW_RSTOUT                      (1 << 0)
 931
 932 /* HDMI_PHY_VPLL */
 933 #define HDMI_PHY_VPLL_LOCK                      (1 << 7)
 934 #define HDMI_PHY_VPLL_CODE_MASK         (0x7 << 0)
 935
 936 /* HDMI_PHY_CMU */
 937 #define HDMI_PHY_CMU_LOCK                       (1 << 7)
 938 #define HDMI_PHY_CMU_CODE_MASK          (0x7 << 0)
 939
 940 /* HDMI_CORE_RSTOUT */
 941 #define HDMI_CORE_SW_RSTOUT                     (1 << 0)
 942
 943
 944 /* Core Register */
 945
 946 /* HDMI_CON_0 */
 947 #define HDMI_BLUE_SCR_EN                        (1 << 5)
 948 #define HDMI_BLUE_SCR_DIS                       (0 << 5)
 949 #define HDMI_ENC_OPTION                 (1 << 4)
 950 #define HDMI_ASP_EN                             (1 << 2)
 951 #define HDMI_ASP_DIS                    (0 << 2)
 952 #define HDMI_PWDN_ENB_NORMAL            (1 << 1)
 953 #define HDMI_PWDN_ENB_PD                        (0 << 1)
 954 #define HDMI_EN                         (1 << 0)
 955 #define HDMI_DIS                                (~(1 << 0))
 956
 957 /* HDMI_CON_1 */
 958 #define HDMI_PX_LMT_CTRL_BYPASS         (0 << 5)
 959 #define HDMI_PX_LMT_CTRL_RGB            (1 << 5)
 960 #define HDMI_PX_LMT_CTRL_YPBPR          (2 << 5)
 961 #define HDMI_PX_LMT_CTRL_RESERVED               (3 << 5)
 962 /*Not support in S5PV210 */
 963 #define HDMI_CON_PXL_REP_RATIO_MASK             (1 << 1 | 1 << 0)
 964 /*Not support in S5PV210 */
 965 #define HDMI_DOUBLE_PIXEL_REPETITION    (0x01)
 966
 967 /* HDMI_CON_2 */
 968 #define HDMI_VID_PREAMBLE_EN            (0 << 5)
 969 #define HDMI_VID_PREAMBLE_DIS           (1 << 5)
 970 #define HDMI_GUARD_BAND_EN                      (0 << 1)
 971 #define HDMI_GUARD_BAND_DIS                     (1 << 1)
 972
 973 /* STATUS */
 974 #define HDMI_AUTHEN_ACK_AUTH            (1 << 7)
 975 #define HDMI_AUTHEN_ACK_NOT                     (0 << 7)
 976 #define HDMI_AUD_FIFO_OVF_FULL          (1 << 6)
 977 #define HDMI_AUD_FIFO_OVF_NOT           (0 << 6)
 978 #define HDMI_UPDATE_RI_INT_OCC          (1 << 4)
 979 #define HDMI_UPDATE_RI_INT_NOT          (0 << 4)
 980 #define HDMI_UPDATE_RI_INT_CLEAR                (1 << 4)
 981 #define HDMI_UPDATE_PJ_INT_OCC          (1 << 3)
 982 #define HDMI_UPDATE_PJ_INT_NOT          (0 << 3)
 983 #define HDMI_UPDATE_PJ_INT_CLEAR                (1 << 3)
 984 #define HDMI_WRITE_INT_OCC                      (1 << 2)
 985 #define HDMI_WRITE_INT_NOT                      (0 << 2)
 986 #define HDMI_WRITE_INT_CLEAR            (1 << 2)
 987 #define HDMI_WATCHDOG_INT_OCC           (1 << 1)
 988 #define HDMI_WATCHDOG_INT_NOT           (0 << 1)
 989 #define HDMI_WATCHDOG_INT_CLEAR         (1 << 1)
 990 #define HDMI_WTFORACTIVERX_INT_OCC              (1)
 991 #define HDMI_WTFORACTIVERX_INT_NOT              (0)
 992 #define HDMI_WTFORACTIVERX_INT_CLEAR    (1)
 993
 994 /* PHY_STATUS */
 995 #define HDMI_PHY_STATUS_READY           (1)
 996
 997 /* STATUS_EN */
 998 #define HDMI_AUD_FIFO_OVF_EN            (1 << 6)
 999 #define HDMI_AUD_FIFO_OVF_DIS           (0 << 6)
1000 #define HDMI_UPDATE_RI_INT_EN           (1 << 4)
1001 #define HDMI_UPDATE_RI_INT_DIS          (0 << 4)
1002 #define HDMI_UPDATE_PJ_INT_EN           (1 << 3)
1003 #define HDMI_UPDATE_PJ_INT_DIS          (0 << 3)
1004 #define HDMI_WRITE_INT_EN                       (1 << 2)
1005 #define HDMI_WRITE_INT_DIS                      (0 << 2)
1006 #define HDMI_WATCHDOG_INT_EN            (1 << 1)
1007 #define HDMI_WATCHDOG_INT_DIS           (0 << 1)
1008 #define HDMI_WTFORACTIVERX_INT_EN               (1)
1009 #define HDMI_WTFORACTIVERX_INT_DIS              (0)
1010 #define HDMI_INT_EN_ALL                         (HDMI_UPDATE_RI_INT_EN|\
1011                                                 HDMI_UPDATE_PJ_INT_DIS|\
1012                                                 HDMI_WRITE_INT_EN|\
1013                                                 HDMI_WATCHDOG_INT_EN|\
1014                                                 HDMI_WTFORACTIVERX_INT_EN)
1015 #define HDMI_INT_DIS_ALL                        (~0x1F)
1016
1017 /* HPD */
1018 #define HDMI_SW_HPD_PLUGGED                     (1 << 1)
1019 #define HDMI_SW_HPD_UNPLUGGED           (0 << 1)
1020 #define HDMI_HPD_SEL_I_HPD                      (1)
1021 #define HDMI_HPD_SEL_SW_HPD                     (0)
1022
1023 /* MODE_SEL */
1024 #define HDMI_MODE_HDMI_EN                       (1 << 1)
1025 #define HDMI_MODE_HDMI_DIS                      (0 << 1)
1026 #define HDMI_MODE_DVI_EN                        (1)
1027 #define HDMI_MODE_DVI_DIS                       (0)
1028 #define HDMI_MODE_MASK                          (3)
1029
1030 /* ENC_EN */
1031 #define HDMI_HDCP_ENC_ENABLE            (1)
1032 #define HDMI_HDCP_ENC_DISABLE           (0)
1033
1034
1035 /* Video Related Register */
1036
1037 /* BLUESCREEN_0/1/2 */
1038 #define HDMI_SET_BLUESCREEN_0(x)                ((x) & 0xFF)
1039 #define HDMI_SET_BLUESCREEN_1(x)                ((x) & 0xFF)
1040 #define HDMI_SET_BLUESCREEN_2(x)                ((x) & 0xFF)
1041
1042 /* HDMI_YMAX/YMIN/CMAX/CMIN */
1043 #define HDMI_SET_YMAX(x)                        ((x) & 0xFF)
1044 #define HDMI_SET_YMIN(x)                        ((x) & 0xFF)
1045 #define HDMI_SET_CMAX(x)                        ((x) & 0xFF)
1046 #define HDMI_SET_CMIN(x)                        ((x) & 0xFF)
1047
1048 /* H_BLANK_0/1 */
1049 #define HDMI_SET_H_BLANK_0(x)           ((x) & 0xFF)
1050 #define HDMI_SET_H_BLANK_1(x)           (((x) >> 8) & 0x3FF)
1051
1052 /* V_BLANK_0/1/2 */
1053 #define HDMI_SET_V_BLANK_0(x)           ((x) & 0xFF)
1054 #define HDMI_SET_V_BLANK_1(x)           (((x) >> 8) & 0xFF)
1055 #define HDMI_SET_V_BLANK_2(x)           (((x) >> 16) & 0xFF)
1056
1057 /* H_V_LINE_0/1/2 */
1058 #define HDMI_SET_H_V_LINE_0(x)          ((x) & 0xFF)
1059 #define HDMI_SET_H_V_LINE_1(x)          (((x) >> 8) & 0xFF)
1060 #define HDMI_SET_H_V_LINE_2(x)          (((x) >> 16) & 0xFF)
1061
1062 /* VSYNC_POL */
1063 #define HDMI_V_SYNC_POL_ACT_LOW         (1)
1064 #define HDMI_V_SYNC_POL_ACT_HIGH                (0)
1065
1066 /* INT_PRO_MODE */
1067 #define HDMI_INTERLACE_MODE                     (1)
1068 #define HDMI_PROGRESSIVE_MODE           (0)
1069
1070 /* V_BLANK_F_0/1/2 */
1071 #define HDMI_SET_V_BLANK_F_0(x)         ((x) & 0xFF)
1072 #define HDMI_SET_V_BLANK_F_1(x)         (((x) >> 8) & 0xFF)
1073 #define HDMI_SET_V_BLANK_F_2(x)         (((x) >> 16) & 0xFF)
1074
1075
1076 /* H_SYNC_GEN_0/1/2 */
1077 #define HDMI_SET_H_SYNC_GEN_0(x)                ((x) & 0xFF)
1078 #define HDMI_SET_H_SYNC_GEN_1(x)                (((x) >> 8) & 0xFF)
1079 #define HDMI_SET_H_SYNC_GEN_2(x)                (((x) >> 16) & 0xFF)
1080
1081
1082 /* V_SYNC_GEN1_0/1/2 */
1083 #define HDMI_SET_V_SYNC_GEN1_0(x)               ((x) & 0xFF)
1084 #define HDMI_SET_V_SYNC_GEN1_1(x)               (((x) >> 8) & 0xFF)
1085 #define HDMI_SET_V_SYNC_GEN1_2(x)               (((x) >> 16) & 0xFF)
1086
1087 /* V_SYNC_GEN2_0/1/2 */
1088 #define HDMI_SET_V_SYNC_GEN2_0(x)               ((x) & 0xFF)
1089 #define HDMI_SET_V_SYNC_GEN2_1(x)               (((x) >> 8) & 0xFF)
1090 #define HDMI_SET_V_SYNC_GEN2_2(x)               (((x) >> 16) & 0xFF)
1091
1092 /* V_SYNC_GEN3_0/1/2 */
1093 #define HDMI_SET_V_SYNC_GEN3_0(x)               ((x) & 0xFF)
1094 #define HDMI_SET_V_SYNC_GEN3_1(x)               (((x) >> 8) & 0xFF)
1095 #define HDMI_SET_V_SYNC_GEN3_2(x)               (((x) >> 16) & 0xFF)
1096
1097
1098 /* Audio Related Packet Register */
1099
1100 /* ASP_CON */
1101 #define HDMI_AUD_DST_DOUBLE                     (1 << 7)
1102 #define HDMI_AUD_NO_DST_DOUBLE          (0 << 7)
1103 #define HDMI_AUD_TYPE_SAMPLE            (0 << 5)
1104 #define HDMI_AUD_TYPE_ONE_BIT           (1 << 5)
1105 #define HDMI_AUD_TYPE_HBR                       (2 << 5)
1106 #define HDMI_AUD_TYPE_DST                       (3 << 5)
1107 #define HDMI_AUD_MODE_TWO_CH            (0 << 4)
1108 #define HDMI_AUD_MODE_MULTI_CH          (1 << 4)
1109 #define HDMI_AUD_SP_AUD3_EN                     (1 << 3)
1110 #define HDMI_AUD_SP_AUD2_EN                     (1 << 2)
1111 #define HDMI_AUD_SP_AUD1_EN                     (1 << 1)
1112 #define HDMI_AUD_SP_AUD0_EN                     (1 << 0)
1113 #define HDMI_AUD_SP_ALL_DIS                     (0 << 0)
1114
1115 #define HDMI_AUD_SET_SP_PRE(x)          ((x) & 0xF)
1116
1117 /* ASP_SP_FLAT */
1118 #define HDMI_ASP_SP_FLAT_AUD_SAMPLE             (0)
1119
1120 /* ASP_CHCFG0/1/2/3 */
1121 #define HDMI_SPK3R_SEL_I_PCM0L          (0 << 27)
1122 #define HDMI_SPK3R_SEL_I_PCM0R          (1 << 27)
1123 #define HDMI_SPK3R_SEL_I_PCM1L          (2 << 27)
1124 #define HDMI_SPK3R_SEL_I_PCM1R          (3 << 27)
1125 #define HDMI_SPK3R_SEL_I_PCM2L          (4 << 27)
1126 #define HDMI_SPK3R_SEL_I_PCM2R          (5 << 27)
1127 #define HDMI_SPK3R_SEL_I_PCM3L          (6 << 27)
1128 #define HDMI_SPK3R_SEL_I_PCM3R          (7 << 27)
1129 #define HDMI_SPK3L_SEL_I_PCM0L          (0 << 24)
1130 #define HDMI_SPK3L_SEL_I_PCM0R          (1 << 24)
1131 #define HDMI_SPK3L_SEL_I_PCM1L          (2 << 24)
1132 #define HDMI_SPK3L_SEL_I_PCM1R          (3 << 24)
1133 #define HDMI_SPK3L_SEL_I_PCM2L          (4 << 24)
1134 #define HDMI_SPK3L_SEL_I_PCM2R          (5 << 24)
1135 #define HDMI_SPK3L_SEL_I_PCM3L          (6 << 24)
1136 #define HDMI_SPK3L_SEL_I_PCM3R          (7 << 24)
1137 #define HDMI_SPK2R_SEL_I_PCM0L          (0 << 19)
1138 #define HDMI_SPK2R_SEL_I_PCM0R          (1 << 19)
1139 #define HDMI_SPK2R_SEL_I_PCM1L          (2 << 19)
1140 #define HDMI_SPK2R_SEL_I_PCM1R          (3 << 19)
1141 #define HDMI_SPK2R_SEL_I_PCM2L          (4 << 19)
1142 #define HDMI_SPK2R_SEL_I_PCM2R          (5 << 19)
1143 #define HDMI_SPK2R_SEL_I_PCM3L          (6 << 19)
1144 #define HDMI_SPK2R_SEL_I_PCM3R          (7 << 19)
1145 #define HDMI_SPK2L_SEL_I_PCM0L          (0 << 16)
1146 #define HDMI_SPK2L_SEL_I_PCM0R          (1 << 16)
1147 #define HDMI_SPK2L_SEL_I_PCM1L          (2 << 16)
1148 #define HDMI_SPK2L_SEL_I_PCM1R          (3 << 16)
1149 #define HDMI_SPK2L_SEL_I_PCM2L          (4 << 16)
1150 #define HDMI_SPK2L_SEL_I_PCM2R          (5 << 16)
1151 #define HDMI_SPK2L_SEL_I_PCM3L          (6 << 16)
1152 #define HDMI_SPK2L_SEL_I_PCM3R          (7 << 16)
1153 #define HDMI_SPK1R_SEL_I_PCM0L          (0 << 11)
1154 #define HDMI_SPK1R_SEL_I_PCM0R          (1 << 11)
1155 #define HDMI_SPK1R_SEL_I_PCM1L          (2 << 11)
1156 #define HDMI_SPK1R_SEL_I_PCM1R          (3 << 11)
1157 #define HDMI_SPK1R_SEL_I_PCM2L          (4 << 11)
1158 #define HDMI_SPK1R_SEL_I_PCM2R          (5 << 11)
1159 #define HDMI_SPK1R_SEL_I_PCM3L          (6 << 11)
1160 #define HDMI_SPK1R_SEL_I_PCM3R          (7 << 11)
1161 #define HDMI_SPK1L_SEL_I_PCM0L          (0 << 8)
1162 #define HDMI_SPK1L_SEL_I_PCM0R          (1 << 8)
1163 #define HDMI_SPK1L_SEL_I_PCM1L          (2 << 8)
1164 #define HDMI_SPK1L_SEL_I_PCM1R          (3 << 8)
1165 #define HDMI_SPK1L_SEL_I_PCM2L          (4 << 8)
1166 #define HDMI_SPK1L_SEL_I_PCM2R          (5 << 8)
1167 #define HDMI_SPK1L_SEL_I_PCM3L          (6 << 8)
1168 #define HDMI_SPK1L_SEL_I_PCM3R          (7 << 8)
1169 #define HDMI_SPK0R_SEL_I_PCM0L          (0 << 3)
1170 #define HDMI_SPK0R_SEL_I_PCM0R          (1 << 3)
1171 #define HDMI_SPK0R_SEL_I_PCM1L          (2 << 3)
1172 #define HDMI_SPK0R_SEL_I_PCM1R          (3 << 3)
1173 #define HDMI_SPK0R_SEL_I_PCM2L          (4 << 3)
1174 #define HDMI_SPK0R_SEL_I_PCM2R          (5 << 3)
1175 #define HDMI_SPK0R_SEL_I_PCM3L          (6 << 3)
1176 #define HDMI_SPK0R_SEL_I_PCM3R          (7 << 3)
1177 #define HDMI_SPK0L_SEL_I_PCM0L          (0)
1178 #define HDMI_SPK0L_SEL_I_PCM0R          (1)
1179 #define HDMI_SPK0L_SEL_I_PCM1L          (2)
1180 #define HDMI_SPK0L_SEL_I_PCM1R          (3)
1181 #define HDMI_SPK0L_SEL_I_PCM2L          (4)
1182 #define HDMI_SPK0L_SEL_I_PCM2R          (5)
1183 #define HDMI_SPK0L_SEL_I_PCM3L          (6)
1184 #define HDMI_SPK0L_SEL_I_PCM3R          (7)
1185
1186 /* ACR_CON */
1187 #define HDMI_ALT_CTS_RATE_CTS_1         (0 << 3)
1188 #define HDMI_ALT_CTS_RATE_CTS_11                (1 << 3)
1189 #define HDMI_ALT_CTS_RATE_CTS_21                (2 << 3)
1190 #define HDMI_ALT_CTS_RATE_CTS_31                (3 << 3)
1191 #define HDMI_ACR_TX_MODE_NO_TX          (0)
1192 #define HDMI_ACR_TX_MODE_TX_ONCE                (1)
1193 #define HDMI_ACR_TX_MODE_TXCNT_VBI              (2)
1194 #define HDMI_ACR_TX_MODE_TX_VPC         (3)
1195 #define HDMI_ACR_TX_MODE_MESURE_CTS             (4)
1196
1197 /* ACR_MCTS0/1/2 */
1198 #define HDMI_SET_ACR_MCTS_0(x)          ((x) & 0xFF)
1199 #define HDMI_SET_ACR_MCTS_1(x)          (((x) >> 8) & 0xFF)
1200 #define HDMI_SET_ACR_MCTS_2(x)          (((x) >> 16) & 0xFF)
1201
1202 /* ACR_CTS0/1/2 */
1203 #define HDMI_SET_ACR_CTS_0(x)           ((x) & 0xFF)
1204 #define HDMI_SET_ACR_CTS_1(x)           (((x) >> 8) & 0xFF)
1205 #define HDMI_SET_ACR_CTS_2(x)           (((x) >> 16) & 0xFF)
1206
1207 /* ACR_N0/1/2 */
1208 #define HDMI_SET_ACR_N_0(x)                     ((x) & 0xFF)
1209 #define HDMI_SET_ACR_N_1(x)                     (((x) >> 8) & 0xFF)
1210 #define HDMI_SET_ACR_N_2(x)                     (((x) >> 16) & 0xFF)
1211
1212
1213 /* ACR_LSB2 */
1214 #define HDMI_ACR_LSB2_MASK                      (0xFF)
1215
1216 /* ACR_TXCNT */
1217 #define HDMI_ACR_TXCNT_MASK                     (0x1F)
1218
1219 /* ACR_TXINTERNAL */
1220 #define HDMI_ACR_TX_INTERNAL_MASK               (0xFF)
1221
1222 /* ACR_CTS_OFFSET */
1223 #define HDMI_ACR_CTS_OFFSET_MASK                (0xFF)
1224
1225 /* GCP_CON */
1226 #define HDMI_GCP_CON_EN_1ST_VSYNC               (1 << 3)
1227 #define HDMI_GCP_CON_EN_2ST_VSYNC               (1 << 2)
1228 #define HDMI_GCP_CON_TRANS_EVERY_VSYNC  (2)
1229 #define HDMI_GCP_CON_NO_TRAN            (0)
1230 #define HDMI_GCP_CON_TRANS_ONCE         (1)
1231 #define HDMI_GCP_CON_TRANS_EVERY_VSYNC  (2)
1232
1233 /* GCP_BYTE1 */
1234 #define HDMI_GCP_BYTE1_MASK                     (0xFF)
1235
1236 /* GCP_BYTE2 */
1237 #define HDMI_GCP_BYTE2_PP_MASK          (0xF << 4)
1238 #define HDMI_GCP_BYTE2_CD_24BPP         (1 << 2)
1239 /*Not support in S5PV210 */
1240 #define HDMI_GCP_BYTE2_CD_30BPP         (1 << 0 | 1 << 2)
1241 /*Not support in S5PV210 */
1242 #define HDMI_GCP_BYTE2_CD_36BPP         (1 << 1 | 1 << 2)
1243 /*Not support in S5PV210 */
1244 #define HDMI_GCP_BYTE2_CD_48BPP         (1 << 0 | 1 << 1 | 1 << 2)
1245
1246
1247 /* GCP_BYTE3 */
1248 #define HDMI_GCP_BYTE3_MASK                     (0xFF)
1249
1250
1251 /* ACP Packet Register */
1252
1253 /* ACP_CON */
1254 #define HDMI_ACP_FR_RATE_MASK           (0x1F << 3)
1255 #define HDMI_ACP_CON_NO_TRAN            (0)
1256 #define HDMI_ACP_CON_TRANS_ONCE         (1)
1257 #define HDMI_ACP_CON_TRANS_EVERY_VSYNC  (2)
1258
1259 /* ACP_TYPE */
1260 #define HDMI_ACP_TYPE_MASK                      (0xFF)
1261
1262 /* ACP_DATA00~16 */
1263 #define HDMI_ACP_DATA_MASK                      (0xFF)
1264
1265
1266 /* ISRC1/2 Packet Register */
1267
1268 /* ISRC_CON */
1269 #define HDMI_ISRC_FR_RATE_MASK          (0x1F << 3)
1270 #define HDMI_ISRC_EN                    (1 << 2)
1271 #define HDMI_ISRC_DIS                   (0 << 2)
1272
1273
1274 /* ISRC1_HEADER1 */
1275 #define HDMI_ISRC1_HEADER_MASK          (0xFF)
1276
1277 /* ISRC1_DATA 00~15 */
1278 #define HDMI_ISRC1_DATA_MASK            (0xFF)
1279
1280 /* ISRC2_DATA 00~15 */
1281 #define HDMI_ISRC2_DATA_MASK            (0xFF)
1282
1283
1284 /* AVI InfoFrame Register */
1285
1286 /* AVI_CON */
1287
1288 /* AVI_CHECK_SUM */
1289 #define HDMI_SET_AVI_CHECK_SUM(x)               ((x) & 0xFF)
1290
1291 /* AVI_DATA01~13 */
1292 #define HDMI_SET_AVI_DATA(x)            ((x) & 0xFF)
1293 #define HDMI_AVI_PIXEL_REPETITION_DOUBLE        (1<<0)
1294 #define HDMI_AVI_PICTURE_ASPECT_4_3             (1<<4)
1295 #define HDMI_AVI_PICTURE_ASPECT_16_9    (1<<5)
1296
1297
1298 /* Audio InfoFrame Register */
1299
1300 /* AUI_CON */
1301
1302 /* AUI_CHECK_SUM */
1303 #define HDMI_SET_AUI_CHECK_SUM(x)               ((x) & 0xFF)
1304
1305 /* AUI_DATA1~5 */
1306 #define HDMI_SET_AUI_DATA(x)            ((x) & 0xFF)
1307
1308
1309 /* MPEG Source InfoFrame registers */
1310
1311 /* MPG_CON */
1312
1313 /* HDMI_MPG_CHECK_SUM */
1314 #define HDMI_SET_MPG_CHECK_SUM(x)               ((x) & 0xFF)
1315
1316 /* MPG_DATA1~5 */
1317 #define HDMI_SET_MPG_DATA(x)            ((x) & 0xFF)
1318
1319
1320 /* Source Product Descriptor Infoframe registers */
1321
1322 /* SPD_CON */
1323
1324 /* SPD_HEADER0/1/2 */
1325 #define HDMI_SET_SPD_HEADER(x)          ((x) & 0xFF)
1326
1327
1328 /* SPD_DATA0~27 */
1329 #define HDMI_SET_SPD_DATA(x)            ((x) & 0xFF)
1330
1331
1332 /* HDCP Register */
1333
1334 /* HDCP_SHA1_00~19 */
1335 #define HDMI_SET_HDCP_SHA1(x)           ((x) & 0xFF)
1336
1337 /* HDCP_KSV_LIST_0~4 */
1338
1339 /* HDCP_KSV_LIST_CON */
1340 #define HDMI_HDCP_KSV_WRITE_DONE                (0x1 << 3)
1341 #define HDMI_HDCP_KSV_LIST_EMPTY                (0x1 << 2)
1342 #define HDMI_HDCP_KSV_END                       (0x1 << 1)
1343 #define HDMI_HDCP_KSV_READ                      (0x1 << 0)
1344
1345 /* HDCP_CTRL1 */
1346 #define HDMI_HDCP_EN_PJ_EN                      (1 << 4)
1347 #define HDMI_HDCP_EN_PJ_DIS                     (~(1 << 4))
1348 #define HDMI_HDCP_SET_REPEATER_TIMEOUT  (1 << 2)
1349 #define HDMI_HDCP_CLEAR_REPEATER_TIMEOUT        (~(1 << 2))
1350 #define HDMI_HDCP_CP_DESIRED_EN         (1 << 1)
1351 #define HDMI_HDCP_CP_DESIRED_DIS                (~(1 << 1))
1352 #define HDMI_HDCP_ENABLE_1_1_FEATURE_EN (1)
1353 #define HDMI_HDCP_ENABLE_1_1_FEATURE_DIS        (~(1))
1354
1355 /* HDCP_CHECK_RESULT */
1356 #define HDMI_HDCP_Pi_MATCH_RESULT_Y             ((0x1 << 3) | (0x1 << 2))
1357 #define HDMI_HDCP_Pi_MATCH_RESULT_N             ((0x1 << 3) | (0x0 << 2))
1358 #define HDMI_HDCP_Ri_MATCH_RESULT_Y             ((0x1 << 1) | (0x1 << 0))
1359 #define HDMI_HDCP_Ri_MATCH_RESULT_N             ((0x1 << 1) | (0x0 << 0))
1360 #define HDMI_HDCP_CLR_ALL_RESULTS               (0)
1361
1362 /* HDCP_BKSV0~4 */
1363 /* HDCP_AKSV0~4 */
1364
1365 /* HDCP_BCAPS */
1366 #define HDMI_HDCP_BCAPS_REPEATER                (1 << 6)
1367 #define HDMI_HDCP_BCAPS_READY           (1 << 5)
1368 #define HDMI_HDCP_BCAPS_FAST            (1 << 4)
1369 #define HDMI_HDCP_BCAPS_1_1_FEATURES    (1 << 1)
1370 #define HDMI_HDCP_BCAPS_FAST_REAUTH             (1)
1371
1372 /* HDCP_BSTATUS_0/1 */
1373 /* HDCP_Ri_0/1 */
1374 /* HDCP_I2C_INT */
1375 /* HDCP_AN_INT */
1376 /* HDCP_WATCHDOG_INT */
1377 /* HDCP_RI_INT/1 */
1378 /* HDCP_Ri_Compare_0 */
1379 /* HDCP_Ri_Compare_1 */
1380 /* HDCP_Frame_Count */
1381
1382
1383 /* Gamut Metadata Packet Register */
1384
1385 /* GAMUT_CON */
1386 /* GAMUT_HEADER0 */
1387 /* GAMUT_HEADER1 */
1388 /* GAMUT_HEADER2 */
1389 /* GAMUT_METADATA0~27 */
1390
1391
1392 /* Video Mode Register */
1393
1394 /* VIDEO_PATTERN_GEN */
1395 /* HPD_GEN */
1396 /* HDCP_Ri_Compare_0 */
1397 /* HDCP_Ri_Compare_0 */
1398 /* HDCP_Ri_Compare_0 */
1399 /* HDCP_Ri_Compare_0 */
1400 /* HDCP_Ri_Compare_0 */
1401 /* HDCP_Ri_Compare_0 */
1402 /* HDCP_Ri_Compare_0 */
1403 /* HDCP_Ri_Compare_0 */
1404 /* HDCP_Ri_Compare_0 */
1405 /* HDCP_Ri_Compare_0 */
1406
1407
1408 /* SPDIF Register */
1409
1410 /* SPDIFIN_CLK_CTRL */
1411 #define HDMI_SPDIFIN_READY_CLK_DOWN             (1 << 1)
1412 #define HDMI_SPDIFIN_CLK_ON                     (1)
1413
1414 /* SPDIFIN_OP_CTRL */
1415 #define HDMI_SPDIFIN_SW_RESET           (0)
1416 #define HDMI_SPDIFIN_STATUS_CHECK_MODE  (1)
1417 #define HDMI_SPDIFIN_STATUS_CHK_OP_MODE (3)
1418
1419 /* SPDIFIN_IRQ_MASK */
1420
1421 /* SPDIFIN_IRQ_STATUS */
1422 #define HDMI_SPDIFIN_IRQ_OVERFLOW_EN                    (1 << 7)
1423 #define HDMI_SPDIFIN_IRQ_ABNORMAL_PD_EN                 (1 << 6)
1424 #define HDMI_SPDIFIN_IRQ_SH_NOT_DETECTED_RIGHTTIME_EN   (1 << 5)
1425 #define HDMI_SPDIFIN_IRQ_SH_DETECTED_EN                 (1 << 4)
1426 #define HDMI_SPDIFIN_IRQ_SH_NOT_DETECTED_EN                     (1 << 3)
1427 #define HDMI_SPDIFIN_IRQ_WRONG_PREAMBLE_EN                      (1 << 2)
1428 #define HDMI_SPDIFIN_IRQ_CH_STATUS_RECOVERED_EN         (1 << 1)
1429 #define HDMI_SPDIFIN_IRQ_WRONG_SIG_EN                   (1 << 0)
1430
1431 /* SPDIFIN_CONFIG_1 */
1432 #define HDMI_SPDIFIN_CFG_FILTER_3_SAMPLE                        (0 << 6)
1433 #define HDMI_SPDIFIN_CFG_FILTER_2_SAMPLE                        (1 << 6)
1434 #define HDMI_SPDIFIN_CFG_LINEAR_PCM_TYPE                        (0 << 5)
1435 #define HDMI_SPDIFIN_CFG_NO_LINEAR_PCM_TYPE                     (1 << 5)
1436 #define HDMI_SPDIFIN_CFG_PCPD_AUTO_SET                  (0 << 4)
1437 #define HDMI_SPDIFIN_CFG_PCPD_MANUAL_SET                        (1 << 4)
1438 #define HDMI_SPDIFIN_CFG_WORD_LENGTH_A_SET                      (0 << 3)
1439 #define HDMI_SPDIFIN_CFG_WORD_LENGTH_M_SET                      (1 << 3)
1440 #define HDMI_SPDIFIN_CFG_U_V_C_P_NEGLECT                        (0 << 2)
1441 #define HDMI_SPDIFIN_CFG_U_V_C_P_REPORT                 (1 << 2)
1442 #define HDMI_SPDIFIN_CFG_BURST_SIZE_1                   (0 << 1)
1443 #define HDMI_SPDIFIN_CFG_BURST_SIZE_2                   (1 << 1)
1444 #define HDMI_SPDIFIN_CFG_DATA_ALIGN_16BIT                       (0 << 0)
1445 #define HDMI_SPDIFIN_CFG_DATA_ALIGN_32BIT                       (1 << 0)
1446
1447 /* SPDIFIN_CONFIG_2 */
1448 #define HDMI_SPDIFIN_CFG2_NO_CLK_DIV                    (0)
1449
1450 /* SPDIFIN_USER_VALUE_1 */
1451 /* SPDIFIN_USER_VALUE_2 */
1452 /* SPDIFIN_USER_VALUE_3 */
1453 /* SPDIFIN_USER_VALUE_4 */
1454 /* SPDIFIN_CH_STATUS_0_1 */
1455 /* SPDIFIN_CH_STATUS_0_2 */
1456 /* SPDIFIN_CH_STATUS_0_3 */
1457 /* SPDIFIN_CH_STATUS_0_4 */
1458 /* SPDIFIN_CH_STATUS_1 */
1459 /* SPDIFIN_FRAME_PERIOD_1 */
1460 /* SPDIFIN_FRAME_PERIOD_2 */
1461 /* SPDIFIN_PC_INFO_1 */
1462 /* SPDIFIN_PC_INFO_2 */
1463 /* SPDIFIN_PD_INFO_1 */
1464 /* SPDIFIN_PD_INFO_2 */
1465 /* SPDIFIN_DATA_BUF_0_1 */
1466 /* SPDIFIN_DATA_BUF_0_2 */
1467 /* SPDIFIN_DATA_BUF_0_3 */
1468 /* SPDIFIN_USER_BUF_0 */
1469 /* SPDIFIN_USER_BUF_1_1 */
1470 /* SPDIFIN_USER_BUF_1_2 */
1471 /* SPDIFIN_USER_BUF_1_3 */
1472 /* SPDIFIN_USER_BUF_1 */
1473
1474
1475 /* I2S Register */
1476
1477 /* I2S_CLK_CON */
1478 #define HDMI_I2S_CLK_DIS                        (0)
1479 #define HDMI_I2S_CLK_EN                 (1)
1480
1481 /* I2S_CON_1 */
1482 #define HDMI_I2S_SCLK_FALLING_EDGE              (0 << 1)
1483 #define HDMI_I2S_SCLK_RISING_EDGE               (1 << 1)
1484 #define HDMI_I2S_L_CH_LOW_POL           (0)
1485 #define HDMI_I2S_L_CH_HIGH_POL          (1)
1486
1487 /* I2S_CON_2 */
1488 #define HDMI_I2S_MSB_FIRST_MODE         (0 << 6)
1489 #define HDMI_I2S_LSB_FIRST_MODE         (1 << 6)
1490 #define HDMI_I2S_BIT_CH_32FS            (0 << 4)
1491 #define HDMI_I2S_BIT_CH_48FS            (1 << 4)
1492 #define HDMI_I2S_BIT_CH_RESERVED                (2 << 4)
1493 #define HDMI_I2S_SDATA_16BIT            (1 << 2)
1494 #define HDMI_I2S_SDATA_20BIT            (2 << 2)
1495 #define HDMI_I2S_SDATA_24BIT            (3 << 2)
1496 #define HDMI_I2S_BASIC_FORMAT           (0)
1497 #define HDMI_I2S_L_JUST_FORMAT          (2)
1498 #define HDMI_I2S_R_JUST_FORMAT          (3)
1499 #define HDMI_I2S_CON_2_CLR                      (~0xFF)
1500 #define HDMI_I2S_SET_BIT_CH(x)          (((x) & 0x7) << 4)
1501 #define HDMI_I2S_SET_SDATA_BIT(x)               (((x) & 0x7) << 2)
1502
1503 /* I2S_PIN_SEL_0 */
1504 #define HDMI_I2S_SEL_SCLK(x)            (((x) & 0x7) << 4)
1505 #define HDMI_I2S_SEL_SCLK_DEFAULT_1             (0x7 << 4)
1506 #define HDMI_I2S_SEL_LRCK(x)            ((x) & 0x7)
1507 #define HDMI_I2S_SEL_LRCK_DEFAULT_0             (0x7)
1508
1509 /* I2S_PIN_SEL_1 */
1510 #define HDMI_I2S_SEL_SDATA1(x)          (((x) & 0x7) << 4)
1511 #define HDMI_I2S_SEL_SDATA1_DEFAULT_3   (0x7 << 4)
1512 #define HDMI_I2S_SEL_SDATA2(x)          ((x) & 0x7)
1513 #define HDMI_I2S_SEL_SDATA2_DEFAULT_2   (0x7)
1514
1515 /* I2S_PIN_SEL_2 */
1516 #define HDMI_I2S_SEL_SDATA3(x)          (((x) & 0x7) << 4)
1517 #define HDMI_I2S_SEL_SDATA3_DEFAULT_5   (0x7 << 4)
1518 #define HDMI_I2S_SEL_SDATA2(x)          ((x) & 0x7)
1519 #define HDMI_I2S_SEL_SDATA2_DEFAULT_4   (0x7)
1520
1521 /* I2S_PIN_SEL_3 */
1522 #define HDMI_I2S_SEL_DSD(x)                     ((x) & 0x7)
1523 #define HDMI_I2S_SEL_DSD_DEFAULT_6              (0x7)
1524
1525 /* I2S_DSD_CON */
1526 #define HDMI_I2S_DSD_CLK_RI_EDGE                (1 << 1)
1527 #define HDMI_I2S_DSD_CLK_FA_EDGE                (0 << 1)
1528 #define HDMI_I2S_DSD_ENABLE                     (1)
1529 #define HDMI_I2S_DSD_DISABLE            (0)
1530
1531 /* I2S_MUX_CON */
1532 #define HDMI_I2S_NOISE_FILTER_ZERO              (0 << 5)
1533 #define HDMI_I2S_NOISE_FILTER_2_STAGE   (1 << 5)
1534 #define HDMI_I2S_NOISE_FILTER_3_STAGE   (2 << 5)
1535 #define HDMI_I2S_NOISE_FILTER_4_STAGE   (3 << 5)
1536 #define HDMI_I2S_NOISE_FILTER_5_STAGE   (4 << 5)
1537 #define HDMI_I2S_IN_DISABLE                     (1 << 4)
1538 #define HDMI_I2S_IN_ENABLE                      (0 << 4)
1539 #define HDMI_I2S_AUD_SPDIF                      (0 << 2)
1540 #define HDMI_I2S_AUD_I2S                        (1 << 2)
1541 #define HDMI_I2S_AUD_DSD                        (2 << 2)
1542 #define HDMI_I2S_CUV_SPDIF_ENABLE               (0 << 1)
1543 #define HDMI_I2S_CUV_I2S_ENABLE         (1 << 1)
1544 #define HDMI_I2S_MUX_DISABLE            (0)
1545 #define HDMI_I2S_MUX_ENABLE                     (1)
1546 #define HDMI_I2S_MUX_CON_CLR            (~0xFF)
1547
1548 /* I2S_CH_ST_CON */
1549 #define HDMI_I2S_CH_STATUS_RELOAD               (1)
1550 #define HDMI_I2S_CH_ST_CON_CLR          (~1)
1551
1552 /* I2S_CH_ST_0 / I2S_CH_ST_SH_0 */
1553 #define HDMI_I2S_CH_STATUS_MODE_0               (0 << 6)
1554 #define HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH        (0 << 3)
1555 #define HDMI_I2S_2AUD_CH_WITH_PREEMPH   (1 << 3)
1556 #define HDMI_I2S_DEFAULT_EMPHASIS               (0 << 3)
1557 #define HDMI_I2S_COPYRIGHT                      (0 << 2)
1558 #define HDMI_I2S_NO_COPYRIGHT           (1 << 2)
1559 #define HDMI_I2S_LINEAR_PCM                     (0 << 1)
1560 #define HDMI_I2S_NO_LINEAR_PCM          (1 << 1)
1561 #define HDMI_I2S_CONSUMER_FORMAT                (0)
1562 #define HDMI_I2S_PROF_FORMAT            (1)
1563 #define HDMI_I2S_CH_ST_0_CLR            (~0xFF)
1564
1565 /* I2S_CH_ST_1 / I2S_CH_ST_SH_1 */
1566 #define HDMI_I2S_CD_PLAYER                      (0x00)
1567 #define HDMI_I2S_DAT_PLAYER                     (0x03)
1568 #define HDMI_I2S_DCC_PLAYER                     (0x43)
1569 #define HDMI_I2S_MINI_DISC_PLAYER               (0x49)
1570
1571 /* I2S_CH_ST_2 / I2S_CH_ST_SH_2 */
1572 #define HDMI_I2S_CHANNEL_NUM_MASK               (0xF << 4)
1573 #define HDMI_I2S_SOURCE_NUM_MASK                (0xF)
1574 #define HDMI_I2S_SET_CHANNEL_NUM(x)             ((x) & (0xF) << 4)
1575 #define HDMI_I2S_SET_SOURCE_NUM(x)              ((x) & (0xF))
1576
1577 /* I2S_CH_ST_3 / I2S_CH_ST_SH_3 */
1578 #define HDMI_I2S_CLK_ACCUR_LEVEL_1              (1 << 4)
1579 #define HDMI_I2S_CLK_ACCUR_LEVEL_2              (0 << 4)
1580 #define HDMI_I2S_CLK_ACCUR_LEVEL_3              (2 << 4)
1581 #define HDMI_I2S_SAMPLING_FREQ_44_1             (0x0)
1582 #define HDMI_I2S_SAMPLING_FREQ_48               (0x2)
1583 #define HDMI_I2S_SAMPLING_FREQ_32               (0x3)
1584 #define HDMI_I2S_SAMPLING_FREQ_96               (0xA)
1585 #define HDMI_I2S_SET_SAMPLING_FREQ(x)   ((x) & (0xF))
1586
1587 /* I2S_CH_ST_4 / I2S_CH_ST_SH_4 */
1588 #define HDMI_I2S_ORG_SAMPLING_FREQ_44_1 (0xF << 4)
1589 #define HDMI_I2S_ORG_SAMPLING_FREQ_88_2 (0x7 << 4)
1590 #define HDMI_I2S_ORG_SAMPLING_FREQ_22_05        (0xB << 4)
1591 #define HDMI_I2S_ORG_SAMPLING_FREQ_176_4        (0x3 << 4)
1592 #define HDMI_I2S_WORD_LENGTH_NOT_DEFINE (0x0 << 1)
1593 #define HDMI_I2S_WORD_LENGTH_MAX24_20BITS       (0x1 << 1)
1594 #define HDMI_I2S_WORD_LENGTH_MAX24_22BITS       (0x2 << 1)
1595 #define HDMI_I2S_WORD_LENGTH_MAX24_23BITS       (0x4 << 1)
1596 #define HDMI_I2S_WORD_LENGTH_MAX24_24BITS       (0x5 << 1)
1597 #define HDMI_I2S_WORD_LENGTH_MAX24_21BITS       (0x6 << 1)
1598 #define HDMI_I2S_WORD_LENGTH_MAX20_16BITS       (0x1 << 1)
1599 #define HDMI_I2S_WORD_LENGTH_MAX20_18BITS       (0x2 << 1)
1600 #define HDMI_I2S_WORD_LENGTH_MAX20_19BITS       (0x4 << 1)
1601 #define HDMI_I2S_WORD_LENGTH_MAX20_20BITS       (0x5 << 1)
1602 #define HDMI_I2S_WORD_LENGTH_MAX20_17BITS       (0x6 << 1)
1603 #define HDMI_I2S_WORD_LENGTH_MAX_24BITS (1)
1604 #define HDMI_I2S_WORD_LENGTH_MAX_20BITS (0)
1605
1606 /* I2S_VD_DATA */
1607 #define HDMI_I2S_VD_AUD_SAMPLE_RELIABLE (0)
1608 #define HDMI_I2S_VD_AUD_SAMPLE_UNRELIABLE       (1)
1609
1610 /* I2S_MUX_CH */
1611 #define HDMI_I2S_CH3_R_EN                       (1 << 7)
1612 #define HDMI_I2S_CH3_L_EN                       (1 << 6)
1613 #define HDMI_I2S_CH3_EN                 (3 << 6)
1614 #define HDMI_I2S_CH2_R_EN                       (1 << 5)
1615 #define HDMI_I2S_CH2_L_EN                       (1 << 4)
1616 #define HDMI_I2S_CH2_EN                 (3 << 4)
1617 #define HDMI_I2S_CH1_R_EN                       (1 << 3)
1618 #define HDMI_I2S_CH1_L_EN                       (1 << 2)
1619 #define HDMI_I2S_CH1_EN                 (3 << 2)
1620 #define HDMI_I2S_CH0_R_EN                       (1 << 1)
1621 #define HDMI_I2S_CH0_L_EN                       (1)
1622 #define HDMI_I2S_CH0_EN                 (3)
1623 #define HDMI_I2S_CH_ALL_EN                      (0xFF)
1624 #define HDMI_I2S_MUX_CH_CLR                     (~HDMI_I2S_CH_ALL_EN)
1625
1626 /* I2S_MUX_CUV */
1627 #define HDMI_I2S_CUV_R_EN                       (1 << 1)
1628 #define HDMI_I2S_CUV_L_EN                       (1)
1629 #define HDMI_I2S_CUV_RL_EN                      (0x03)
1630
1631 /* I2S_IRQ_MASK */
1632 #define HDMI_I2S_INT2_DIS                       (0 << 1)
1633 #define HDMI_I2S_INT2_EN                        (1 << 1)
1634
1635 /* I2S_IRQ_STATUS */
1636 #define HDMI_I2S_INT2_STATUS            (1 << 1)
1637
1638 /* I2S_CH0_L_0 */
1639 /* I2S_CH0_L_1 */
1640 /* I2S_CH0_L_2 */
1641 /* I2S_CH0_L_3 */
1642 /* I2S_CH0_R_0 */
1643 /* I2S_CH0_R_1 */
1644 /* I2S_CH0_R_2 */
1645 /* I2S_CH0_R_3 */
1646 /* I2S_CH1_L_0 */
1647 /* I2S_CH1_L_1 */
1648 /* I2S_CH1_L_2 */
1649 /* I2S_CH1_L_3 */
1650 /* I2S_CH1_R_0 */
1651 /* I2S_CH1_R_1 */
1652 /* I2S_CH1_R_2 */
1653 /* I2S_CH1_R_3 */
1654 /* I2S_CH2_L_0 */
1655 /* I2S_CH2_L_1 */
1656 /* I2S_CH2_L_2 */
1657 /* I2S_CH2_L_3 */
1658 /* I2S_CH2_R_0 */
1659 /* I2S_CH2_R_1 */
1660 /* I2S_CH2_R_2 */
1661 /* I2S_Ch2_R_3 */
1662 /* I2S_CH3_L_0 */
1663 /* I2S_CH3_L_1 */
1664 /* I2S_CH3_L_2 */
1665 /* I2S_CH3_R_0 */
1666 /* I2S_CH3_R_1 */
1667 /* I2S_CH3_R_2 */
1668
1669 /* I2S_CUV_L_R */
1670 #define HDMI_I2S_CUV_R_DATA_MASK                (0x7 << 4)
1671 #define HDMI_I2S_CUV_L_DATA_MASK                (0x7)
1672
1673
1674 /* Timing Generator Register */
1675 /* TG_CMD */
1676 #define HDMI_GETSYNC_TYPE_EN            (1 << 4)
1677 #define HDMI_GETSYNC_TYPE_DIS           (~HDMI_GETSYNC_TYPE_EN)
1678 #define HDMI_GETSYNC_EN                 (1 << 3)
1679 #define HDMI_GETSYNC_DIS                        (~HDMI_GETSYNC_EN)
1680 #define HDMI_FIELD_EN                   (1 << 1)
1681 #define HDMI_FIELD_DIS                  (~HDMI_FIELD_EN)
1682 #define HDMI_TG_EN                              (1)
1683 #define HDMI_TG_DIS                             (~HDMI_TG_EN)
1684
1685 /* TG_CFG */
1686 /* TG_CB_SZ */
1687 /* TG_INDELAY_L */
1688 /* TG_INDELAY_H */
1689 /* TG_POL_CTRL */
1690
1691 /* TG_H_FSZ_L */
1692 #define HDMI_SET_TG_H_FSZ_L(x)          ((x) & 0xFF)
1693
1694 /* TG_H_FSZ_H */
1695 #define HDMI_SET_TG_H_FSZ_H(x)          (((x) >> 8) & 0x1F)
1696
1697 /* TG_HACT_ST_L */
1698 #define HDMI_SET_TG_HACT_ST_L(x)                ((x) & 0xFF)
1699
1700 /* TG_HACT_ST_H */
1701 #define HDMI_SET_TG_HACT_ST_H(x)                (((x) >> 8) & 0xF)
1702
1703 /* TG_HACT_SZ_L */
1704 #define HDMI_SET_TG_HACT_SZ_L(x)                ((x) & 0xFF)
1705
1706 /* TG_HACT_SZ_H */
1707 #define HDMI_SET_TG_HACT_SZ_H(x)                (((x) >> 8) & 0xF)
1708
1709 /* TG_V_FSZ_L */
1710 #define HDMI_SET_TG_V_FSZ_L(x)          ((x) & 0xFF)
1711
1712 /* TG_V_FSZ_H */
1713 #define HDMI_SET_TG_V_FSZ_H(x)          (((x) >> 8) & 0x7)
1714
1715 /* TG_VSYNC_L */
1716 #define HDMI_SET_TG_VSYNC_L(x)          ((x) & 0xFF)
1717
1718 /* TG_VSYNC_H */
1719 #define HDMI_SET_TG_VSYNC_H(x)          (((x) >> 8) & 0x7)
1720
1721 /* TG_VSYNC2_L */
1722 #define HDMI_SET_TG_VSYNC2_L(x)         ((x) & 0xFF)
1723
1724 /* TG_VSYNC2_H */
1725 #define HDMI_SET_TG_VSYNC2_H(x)         (((x) >> 8) & 0x7)
1726
1727 /* TG_VACT_ST_L */
1728 #define HDMI_SET_TG_VACT_ST_L(x)                ((x) & 0xFF)
1729
1730 /* TG_VACT_ST_H */
1731 #define HDMI_SET_TG_VACT_ST_H(x)                (((x) >> 8) & 0x7)
1732
1733 /* TG_VACT_SZ_L */
1734 #define HDMI_SET_TG_VACT_SZ_L(x)                ((x) & 0xFF)
1735
1736 /* TG_VACT_SZ_H */
1737 #define HDMI_SET_TG_VACT_SZ_H(x)                (((x) >> 8) & 0x7)
1738
1739 /* TG_FIELD_CHG_L */
1740 #define HDMI_SET_TG_FIELD_CHG_L(x)              ((x) & 0xFF)
1741
1742 /* TG_FIELD_CHG_H */
1743 #define HDMI_SET_TG_FIELD_CHG_H(x)              (((x) >> 8) & 0x7)
1744
1745 /* TG_VACT_ST2_L */
1746 #define HDMI_SET_TG_VACT_ST2_L(x)               ((x) & 0xFF)
1747
1748 /* TG_VACT_ST2_H */
1749 #define HDMI_SET_TG_VACT_ST2_H(x)               (((x) >> 8) & 0x7)
1750
1751 /* TG_VACT_SC_ST_L */
1752 /* TG_VACT_SC_ST_H */
1753 /* TG_VACT_SC_SZ_L */
1754 /* TG_VACT_SC_SZ_H */
1755
1756 /* TG_VSYNC_TOP_HDMI_L */
1757 #define HDMI_SET_TG_VSYNC_TOP_HDMI_L(x) ((x) & 0xFF)
1758
1759 /* TG_VSYNC_TOP_HDMI_H */
1760 #define HDMI_SET_TG_VSYNC_TOP_HDMI_H(x) (((x) >> 8) & 0x7)
1761
1762 /* TG_VSYNC_BOT_HDMI_L */
1763 #define HDMI_SET_TG_VSYNC_BOT_HDMI_L(x) ((x) & 0xFF)
1764
1765 /* TG_VSYNC_BOT_HDMI_H */
1766 #define HDMI_SET_TG_VSYNC_BOT_HDMI_H(x) (((x) >> 8) & 0x7)
1767
1768 /* TG_FIELD_TOP_HDMI_L */
1769 #define HDMI_SET_TG_FIELD_TOP_HDMI_L(x) ((x) & 0xFF)
1770
1771 /* TG_FIELD_TOP_HDMI_H */
1772 #define HDMI_SET_TG_FIELD_TOP_HDMI_H(x) (((x) >> 8) & 0x7)
1773
1774 /* TG_FIELD_BOT_HDMI_L */
1775 #define HDMI_SET_TG_FIELD_BOT_HDMI_L(x) ((x) & 0xFF)
1776
1777 /* TG_FIELD_BOT_HDMI_H */
1778 #define HDMI_SET_TG_FIELD_BOT_HDMI_H(x) (((x) >> 8) & 0x7)
1779
1780 /* TG_HSYNC_HDOUT_ST_L */
1781 /* TG_HSYNC_HDOUT_ST_H */
1782 /* TG_HSYNC_HDOUT_END_L */
1783 /* TG_HSYNC_HDOUT_END_H */
1784 /* TG_VSYNC_HDOUT_ST_L */
1785 /* TG_VSYNC_HDOUT_ST_H */
1786 /* TG_VSYNC_HDOUT_END_L */
1787 /* TG_VSYNC_HDOUT_END_H */
1788 /* TG_VSYNC_HDOUT_DLY_L */
1789 /* TG_VSYNC_HDOUT_DLY_H */
1790 /* TG_BT_ERR_RANGE */
1791 /* TG_BT_ERR_RESULT */
1792 /* TG_COR_THR */
1793 /* TG_COR_NUM */
1794 /* TG_BT_CON */
1795 /* TG_BT_H_FSZ_L */
1796 /* TG_BT_H_FSZ_H */
1797 /* TG_BT_HSYNC_ST */
1798 /* TG_BT_HSYNC_SZ */
1799 /* TG_BT_FSZ_L */
1800 /* TG_BT_FSZ_H */
1801 /* TG_BT_VACT_T_ST_L */
1802 /* TG_BT_VACT_T_ST_H */
1803 /* TG_BT_VACT_B_ST_L */
1804 /* TG_BT_VACT_B_ST_H */
1805 /* TG_BT_VACT_SZ_L */
1806 /* TG_BT_VACT_SZ_H */
1807 /* TG_BT_VSYNC_SZ */
1808
1809
1810 /* HDCP E-FUSE Control Register */
1811 /* HDCP_E_FUSE_CTRL */
1812 #define HDMI_EFUSE_CTRL_HDCP_KEY_READ   (1)
1813
1814 /* HDCP_E_FUSE_STATUS */
1815 #define HDMI_EFUSE_ECC_FAIL                     (1 << 2)
1816 #define HDMI_EFUSE_ECC_BUSY                     (1 << 1)
1817 #define HDMI_EFUSE_ECC_DONE                     (1)
1818
1819 /* EFUSE_ADDR_WIDTH */
1820 /* EFUSE_SIGDEV_ASSERT */
1821 /* EFUSE_SIGDEV_DE-ASSERT */
1822 /* EFUSE_PRCHG_ASSERT */
1823 /* EFUSE_PRCHG_DE-ASSERT */
1824 /* EFUSE_FSET_ASSERT */
1825 /* EFUSE_FSET_DE-ASSERT */
1826 /* EFUSE_SENSING */
1827 /* EFUSE_SCK_ASSERT */
1828 /* EFUSE_SCK_DEASSERT */
1829 /* EFUSE_SDOUT_OFFSET */
1830 /* EFUSE_READ_OFFSET */
1831
1832 /* HDCP_SHA_RESULT, Not support in s5pv210 */
1833 /* Not support in s5pv210 */
1834 #define HDMI_HDCP_SHA_VALID_NO_RD               (0 << 1)
1835 /* Not support in s5pv210 */
1836 #define HDMI_HDCP_SHA_VALID_RD          (1 << 1)
1837 /* Not support in s5pv210 */
1838 #define HDMI_HDCP_SHA_VALID                     (1)
1839 /* Not support in s5pv210 */
1840 #define HDMI_HDCP_SHA_NO_VALID          (0)
1841
1842 /* DC_CONTRAL */
1843 /*Not support in S5PV210 */
1844 #define HDMI_DC_CTL_12                  (1 << 1)
1845 /*Not support in S5PV210 */
1846 #define HDMI_DC_CTL_8                   (0)
1847 /*Not support in S5PV210 */
1848 #define HDMI_DC_CTL_10                  (1)
1849 #endif /* __ASM_ARCH_REGS_HDMI_H */