drivers/media/tuners/r820t.c

   1 /*
   2  * Rafael Micro R820T driver
   3  *
   4  * Copyright (C) 2013 Mauro Carvalho Chehab <mchehab@redhat.com>
   5  *
   6  * This driver was written from scratch, based on an existing driver
   7  * that it is part of rtl-sdr git tree, released under GPLv2:
   8  *      https://groups.google.com/forum/#!topic/ultra-cheap-sdr/Y3rBEOFtHug
   9  *      https://github.com/n1gp/gr-baz
  10  *
  11  * From what I understood from the threads, the original driver was converted
  12  * to userspace from a Realtek tree. I couldn't find the original tree.
  13  * However, the original driver look awkward on my eyes. So, I decided to
  14  * write a new version from it from the scratch, while trying to reproduce
  15  * everything found there.
  16  *
  17  * TODO:
  18  *      After locking, the original driver seems to have some routines to
  19  *              improve reception. This was not implemented here yet.
  20  *
  21  *      RF Gain set/get is not implemented.
  22  *
  23  *    This program is free software; you can redistribute it and/or modify
  24  *    it under the terms of the GNU General Public License as published by
  25  *    the Free Software Foundation; either version 2 of the License, or
  26  *    (at your option) any later version.
  27  *
  28  *    This program is distributed in the hope that it will be useful,
  29  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  30  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  31  *    GNU General Public License for more details.
  32  *
  33  */
  34
  35 #include <linux/videodev2.h>
  36 #include <linux/mutex.h>
  37 #include <linux/slab.h>
  38 #include <linux/bitrev.h>
  39
  40 #include "tuner-i2c.h"
  41 #include "r820t.h"
  42
  43 /*
  44  * FIXME: I think that there are only 32 registers, but better safe than
  45  *        sorry. After finishing the driver, we may review it.
  46  */
  47 #define REG_SHADOW_START        5
  48 #define NUM_REGS                27
  49 #define NUM_IMR                 5
  50 #define IMR_TRIAL               9
  51
  52 #define VER_NUM  49
  53
  54 static int debug;
  55 module_param(debug, int, 0644);
  56 MODULE_PARM_DESC(debug, "enable verbose debug messages");
  57
  58 static int no_imr_cal;
  59 module_param(no_imr_cal, int, 0444);
  60 MODULE_PARM_DESC(no_imr_cal, "Disable IMR calibration at module init");
  61
  62
  63 /*
  64  * enums and structures
  65  */
  66
  67 enum xtal_cap_value {
  68         XTAL_LOW_CAP_30P = 0,
  69         XTAL_LOW_CAP_20P,
  70         XTAL_LOW_CAP_10P,
  71         XTAL_LOW_CAP_0P,
  72         XTAL_HIGH_CAP_0P
  73 };
  74
  75 struct r820t_sect_type {
  76         u8      phase_y;
  77         u8      gain_x;
  78         u16     value;
  79 };
  80
  81 struct r820t_priv {
  82         struct list_head                hybrid_tuner_instance_list;
  83         const struct r820t_config       *cfg;
  84         struct tuner_i2c_props          i2c_props;
  85         struct mutex                    lock;
  86
  87         u8                              regs[NUM_REGS];
  88         u8                              buf[NUM_REGS + 1];
  89         enum xtal_cap_value             xtal_cap_sel;
  90         u16                             pll;    /* kHz */
  91         u32                             int_freq;
  92         u8                              fil_cal_code;
  93         bool                            imr_done;
  94         bool                            has_lock;
  95         bool                            init_done;
  96         struct r820t_sect_type          imr_data[NUM_IMR];
  97
  98         /* Store current mode */
  99         u32                             delsys;
 100         enum v4l2_tuner_type            type;
 101         v4l2_std_id                     std;
 102         u32                             bw;     /* in MHz */
 103 };
 104
 105 struct r820t_freq_range {
 106         u32     freq;
 107         u8      open_d;
 108         u8      rf_mux_ploy;
 109         u8      tf_c;
 110         u8      xtal_cap20p;
 111         u8      xtal_cap10p;
 112         u8      xtal_cap0p;
 113         u8      imr_mem;                /* Not used, currently */
 114 };
 115
 116 #define VCO_POWER_REF   0x02
 117 #define DIP_FREQ        32000000
 118
 119 /*
 120  * Static constants
 121  */
 122
 123 static LIST_HEAD(hybrid_tuner_instance_list);
 124 static DEFINE_MUTEX(r820t_list_mutex);
 125
 126 /* Those initial values start from REG_SHADOW_START */
 127 static const u8 r820t_init_array[NUM_REGS] = {
 128         0x83, 0x32, 0x75,                       /* 05 to 07 */
 129         0xc0, 0x40, 0xd6, 0x6c,                 /* 08 to 0b */
 130         0xf5, 0x63, 0x75, 0x68,                 /* 0c to 0f */
 131         0x6c, 0x83, 0x80, 0x00,                 /* 10 to 13 */
 132         0x0f, 0x00, 0xc0, 0x30,                 /* 14 to 17 */
 133         0x48, 0xcc, 0x60, 0x00,                 /* 18 to 1b */
 134         0x54, 0xae, 0x4a, 0xc0                  /* 1c to 1f */
 135 };
 136
 137 /* Tuner frequency ranges */
 138 static const struct r820t_freq_range freq_ranges[] = {
 139         {
 140                 .freq = 0,
 141                 .open_d = 0x08,         /* low */
 142                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 143                 .tf_c = 0xdf,           /* R27[7:0]  band2,band0 */
 144                 .xtal_cap20p = 0x02,    /* R16[1:0]  20pF (10)   */
 145                 .xtal_cap10p = 0x01,
 146                 .xtal_cap0p = 0x00,
 147                 .imr_mem = 0,
 148         }, {
 149                 .freq = 50,             /* Start freq, in MHz */
 150                 .open_d = 0x08,         /* low */
 151                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 152                 .tf_c = 0xbe,           /* R27[7:0]  band4,band1  */
 153                 .xtal_cap20p = 0x02,    /* R16[1:0]  20pF (10)   */
 154                 .xtal_cap10p = 0x01,
 155                 .xtal_cap0p = 0x00,
 156                 .imr_mem = 0,
 157         }, {
 158                 .freq = 55,             /* Start freq, in MHz */
 159                 .open_d = 0x08,         /* low */
 160                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 161                 .tf_c = 0x8b,           /* R27[7:0]  band7,band4 */
 162                 .xtal_cap20p = 0x02,    /* R16[1:0]  20pF (10)   */
 163                 .xtal_cap10p = 0x01,
 164                 .xtal_cap0p = 0x00,
 165                 .imr_mem = 0,
 166         }, {
 167                 .freq = 60,             /* Start freq, in MHz */
 168                 .open_d = 0x08,         /* low */
 169                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 170                 .tf_c = 0x7b,           /* R27[7:0]  band8,band4 */
 171                 .xtal_cap20p = 0x02,    /* R16[1:0]  20pF (10)   */
 172                 .xtal_cap10p = 0x01,
 173                 .xtal_cap0p = 0x00,
 174                 .imr_mem = 0,
 175         }, {
 176                 .freq = 65,             /* Start freq, in MHz */
 177                 .open_d = 0x08,         /* low */
 178                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 179                 .tf_c = 0x69,           /* R27[7:0]  band9,band6 */
 180                 .xtal_cap20p = 0x02,    /* R16[1:0]  20pF (10)   */
 181                 .xtal_cap10p = 0x01,
 182                 .xtal_cap0p = 0x00,
 183                 .imr_mem = 0,
 184         }, {
 185                 .freq = 70,             /* Start freq, in MHz */
 186                 .open_d = 0x08,         /* low */
 187                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 188                 .tf_c = 0x58,           /* R27[7:0]  band10,band7 */
 189                 .xtal_cap20p = 0x02,    /* R16[1:0]  20pF (10)   */
 190                 .xtal_cap10p = 0x01,
 191                 .xtal_cap0p = 0x00,
 192                 .imr_mem = 0,
 193         }, {
 194                 .freq = 75,             /* Start freq, in MHz */
 195                 .open_d = 0x00,         /* high */
 196                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 197                 .tf_c = 0x44,           /* R27[7:0]  band11,band11 */
 198                 .xtal_cap20p = 0x02,    /* R16[1:0]  20pF (10)   */
 199                 .xtal_cap10p = 0x01,
 200                 .xtal_cap0p = 0x00,
 201                 .imr_mem = 0,
 202         }, {
 203                 .freq = 80,             /* Start freq, in MHz */
 204                 .open_d = 0x00,         /* high */
 205                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 206                 .tf_c = 0x44,           /* R27[7:0]  band11,band11 */
 207                 .xtal_cap20p = 0x02,    /* R16[1:0]  20pF (10)   */
 208                 .xtal_cap10p = 0x01,
 209                 .xtal_cap0p = 0x00,
 210                 .imr_mem = 0,
 211         }, {
 212                 .freq = 90,             /* Start freq, in MHz */
 213                 .open_d = 0x00,         /* high */
 214                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 215                 .tf_c = 0x34,           /* R27[7:0]  band12,band11 */
 216                 .xtal_cap20p = 0x01,    /* R16[1:0]  10pF (01)   */
 217                 .xtal_cap10p = 0x01,
 218                 .xtal_cap0p = 0x00,
 219                 .imr_mem = 0,
 220         }, {
 221                 .freq = 100,            /* Start freq, in MHz */
 222                 .open_d = 0x00,         /* high */
 223                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 224                 .tf_c = 0x34,           /* R27[7:0]  band12,band11 */
 225                 .xtal_cap20p = 0x01,    /* R16[1:0]  10pF (01)    */
 226                 .xtal_cap10p = 0x01,
 227                 .xtal_cap0p = 0x00,
 228                 .imr_mem = 0,
 229         }, {
 230                 .freq = 110,            /* Start freq, in MHz */
 231                 .open_d = 0x00,         /* high */
 232                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 233                 .tf_c = 0x24,           /* R27[7:0]  band13,band11 */
 234                 .xtal_cap20p = 0x01,    /* R16[1:0]  10pF (01)   */
 235                 .xtal_cap10p = 0x01,
 236                 .xtal_cap0p = 0x00,
 237                 .imr_mem = 1,
 238         }, {
 239                 .freq = 120,            /* Start freq, in MHz */
 240                 .open_d = 0x00,         /* high */
 241                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 242                 .tf_c = 0x24,           /* R27[7:0]  band13,band11 */
 243                 .xtal_cap20p = 0x01,    /* R16[1:0]  10pF (01)   */
 244                 .xtal_cap10p = 0x01,
 245                 .xtal_cap0p = 0x00,
 246                 .imr_mem = 1,
 247         }, {
 248                 .freq = 140,            /* Start freq, in MHz */
 249                 .open_d = 0x00,         /* high */
 250                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 251                 .tf_c = 0x14,           /* R27[7:0]  band14,band11 */
 252                 .xtal_cap20p = 0x01,    /* R16[1:0]  10pF (01)   */
 253                 .xtal_cap10p = 0x01,
 254                 .xtal_cap0p = 0x00,
 255                 .imr_mem = 1,
 256         }, {
 257                 .freq = 180,            /* Start freq, in MHz */
 258                 .open_d = 0x00,         /* high */
 259                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 260                 .tf_c = 0x13,           /* R27[7:0]  band14,band12 */
 261                 .xtal_cap20p = 0x00,    /* R16[1:0]  0pF (00)   */
 262                 .xtal_cap10p = 0x00,
 263                 .xtal_cap0p = 0x00,
 264                 .imr_mem = 1,
 265         }, {
 266                 .freq = 220,            /* Start freq, in MHz */
 267                 .open_d = 0x00,         /* high */
 268                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 269                 .tf_c = 0x13,           /* R27[7:0]  band14,band12 */
 270                 .xtal_cap20p = 0x00,    /* R16[1:0]  0pF (00)   */
 271                 .xtal_cap10p = 0x00,
 272                 .xtal_cap0p = 0x00,
 273                 .imr_mem = 2,
 274         }, {
 275                 .freq = 250,            /* Start freq, in MHz */
 276                 .open_d = 0x00,         /* high */
 277                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 278                 .tf_c = 0x11,           /* R27[7:0]  highest,highest */
 279                 .xtal_cap20p = 0x00,    /* R16[1:0]  0pF (00)   */
 280                 .xtal_cap10p = 0x00,
 281                 .xtal_cap0p = 0x00,
 282                 .imr_mem = 2,
 283         }, {
 284                 .freq = 280,            /* Start freq, in MHz */
 285                 .open_d = 0x00,         /* high */
 286                 .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
 287                 .tf_c = 0x00,           /* R27[7:0]  highest,highest */
 288                 .xtal_cap20p = 0x00,    /* R16[1:0]  0pF (00)   */
 289                 .xtal_cap10p = 0x00,
 290                 .xtal_cap0p = 0x00,
 291                 .imr_mem = 2,
 292         }, {
 293                 .freq = 310,            /* Start freq, in MHz */
 294                 .open_d = 0x00,         /* high */
 295                 .rf_mux_ploy = 0x41,    /* R26[7:6]=1 (bypass)  R26[1:0]=1 (middle) */
 296                 .tf_c = 0x00,           /* R27[7:0]  highest,highest */
 297                 .xtal_cap20p = 0x00,    /* R16[1:0]  0pF (00)   */
 298                 .xtal_cap10p = 0x00,
 299                 .xtal_cap0p = 0x00,
 300                 .imr_mem = 2,
 301         }, {
 302                 .freq = 450,            /* Start freq, in MHz */
 303                 .open_d = 0x00,         /* high */
 304                 .rf_mux_ploy = 0x41,    /* R26[7:6]=1 (bypass)  R26[1:0]=1 (middle) */
 305                 .tf_c = 0x00,           /* R27[7:0]  highest,highest */
 306                 .xtal_cap20p = 0x00,    /* R16[1:0]  0pF (00)   */
 307                 .xtal_cap10p = 0x00,
 308                 .xtal_cap0p = 0x00,
 309                 .imr_mem = 3,
 310         }, {
 311                 .freq = 588,            /* Start freq, in MHz */
 312                 .open_d = 0x00,         /* high */
 313                 .rf_mux_ploy = 0x40,    /* R26[7:6]=1 (bypass)  R26[1:0]=0 (highest) */
 314                 .tf_c = 0x00,           /* R27[7:0]  highest,highest */
 315                 .xtal_cap20p = 0x00,    /* R16[1:0]  0pF (00)   */
 316                 .xtal_cap10p = 0x00,
 317                 .xtal_cap0p = 0x00,
 318                 .imr_mem = 3,
 319         }, {
 320                 .freq = 650,            /* Start freq, in MHz */
 321                 .open_d = 0x00,         /* high */
 322                 .rf_mux_ploy = 0x40,    /* R26[7:6]=1 (bypass)  R26[1:0]=0 (highest) */
 323                 .tf_c = 0x00,           /* R27[7:0]  highest,highest */
 324                 .xtal_cap20p = 0x00,    /* R16[1:0]  0pF (00)   */
 325                 .xtal_cap10p = 0x00,
 326                 .xtal_cap0p = 0x00,
 327                 .imr_mem = 4,
 328         }
 329 };
 330
 331 static int r820t_xtal_capacitor[][2] = {
 332         { 0x0b, XTAL_LOW_CAP_30P },
 333         { 0x02, XTAL_LOW_CAP_20P },
 334         { 0x01, XTAL_LOW_CAP_10P },
 335         { 0x00, XTAL_LOW_CAP_0P  },
 336         { 0x10, XTAL_HIGH_CAP_0P },
 337 };
 338
 339 /*
 340  * measured with a Racal 6103E GSM test set at 928 MHz with -60 dBm
 341  * input power, for raw results see:
 342  *      http://steve-m.de/projects/rtl-sdr/gain_measurement/r820t/
 343  */
 344
 345 static const int r820t_lna_gain_steps[]  = {
 346         0, 9, 13, 40, 38, 13, 31, 22, 26, 31, 26, 14, 19, 5, 35, 13
 347 };
 348
 349 static const int r820t_mixer_gain_steps[]  = {
 350         0, 5, 10, 10, 19, 9, 10, 25, 17, 10, 8, 16, 13, 6, 3, -8
 351 };
 352
 353 /*
 354  * I2C read/write code and shadow registers logic
 355  */
 356 static void shadow_store(struct r820t_priv *priv, u8 reg, const u8 *val,
 357                          int len)
 358 {
 359         int r = reg - REG_SHADOW_START;
 360
 361         if (r < 0) {
 362                 len += r;
 363                 r = 0;
 364         }
 365         if (len <= 0)
 366                 return;
 367         if (len > NUM_REGS)
 368                 len = NUM_REGS;
 369
 370         tuner_dbg("%s: prev  reg=%02x len=%d: %*ph\n",
 371                   __func__, r + REG_SHADOW_START, len, len, val);
 372
 373         memcpy(&priv->regs[r], val, len);
 374 }
 375
 376 static int r820t_write(struct r820t_priv *priv, u8 reg, const u8 *val,
 377                        int len)
 378 {
 379         int rc, size, pos = 0;
 380
 381         /* Store the shadow registers */
 382         shadow_store(priv, reg, val, len);
 383
 384         do {
 385                 if (len > priv->cfg->max_i2c_msg_len - 1)
 386                         size = priv->cfg->max_i2c_msg_len - 1;
 387                 else
 388                         size = len;
 389
 390                 /* Fill I2C buffer */
 391                 priv->buf[0] = reg;
 392                 memcpy(&priv->buf[1], &val[pos], size);
 393
 394                 rc = tuner_i2c_xfer_send(&priv->i2c_props, priv->buf, size + 1);
 395                 if (rc != size + 1) {
 396                         tuner_info("%s: i2c wr failed=%d reg=%02x len=%d: %*ph\n",
 397                                    __func__, rc, reg, size, size, &priv->buf[1]);
 398                         if (rc < 0)
 399                                 return rc;
 400                         return -EREMOTEIO;
 401                 }
 402                 tuner_dbg("%s: i2c wr reg=%02x len=%d: %*ph\n",
 403                           __func__, reg, size, size, &priv->buf[1]);
 404
 405                 reg += size;
 406                 len -= size;
 407                 pos += size;
 408         } while (len > 0);
 409
 410         return 0;
 411 }
 412
 413 static int r820t_write_reg(struct r820t_priv *priv, u8 reg, u8 val)
 414 {
 415         return r820t_write(priv, reg, &val, 1);
 416 }
 417
 418 static int r820t_read_cache_reg(struct r820t_priv *priv, int reg)
 419 {
 420         reg -= REG_SHADOW_START;
 421
 422         if (reg >= 0 && reg < NUM_REGS)
 423                 return priv->regs[reg];
 424         else
 425                 return -EINVAL;
 426 }
 427
 428 static int r820t_write_reg_mask(struct r820t_priv *priv, u8 reg, u8 val,
 429                                 u8 bit_mask)
 430 {
 431         int rc = r820t_read_cache_reg(priv, reg);
 432
 433         if (rc < 0)
 434                 return rc;
 435
 436         val = (rc & ~bit_mask) | (val & bit_mask);
 437
 438         return r820t_write(priv, reg, &val, 1);
 439 }
 440
 441 static int r820t_read(struct r820t_priv *priv, u8 reg, u8 *val, int len)
 442 {
 443         int rc, i;
 444         u8 *p = &priv->buf[1];
 445
 446         priv->buf[0] = reg;
 447
 448         rc = tuner_i2c_xfer_send_recv(&priv->i2c_props, priv->buf, 1, p, len);
 449         if (rc != len) {
 450                 tuner_info("%s: i2c rd failed=%d reg=%02x len=%d: %*ph\n",
 451                            __func__, rc, reg, len, len, p);
 452                 if (rc < 0)
 453                         return rc;
 454                 return -EREMOTEIO;
 455         }
 456
 457         /* Copy data to the output buffer */
 458         for (i = 0; i < len; i++)
 459                 val[i] = bitrev8(p[i]);
 460
 461         tuner_dbg("%s: i2c rd reg=%02x len=%d: %*ph\n",
 462                   __func__, reg, len, len, val);
 463
 464         return 0;
 465 }
 466
 467 /*
 468  * r820t tuning logic
 469  */
 470
 471 static int r820t_set_mux(struct r820t_priv *priv, u32 freq)
 472 {
 473         const struct r820t_freq_range *range;
 474         int i, rc;
 475         u8 val, reg08, reg09;
 476
 477         /* Get the proper frequency range */
 478         freq = freq / 1000000;
 479         for (i = 0; i < ARRAY_SIZE(freq_ranges) - 1; i++) {
 480                 if (freq < freq_ranges[i + 1].freq)
 481                         break;
 482         }
 483         range = &freq_ranges[i];
 484
 485         tuner_dbg("set r820t range#%d for frequency %d MHz\n", i, freq);
 486
 487         /* Open Drain */
 488         rc = r820t_write_reg_mask(priv, 0x17, range->open_d, 0x08);
 489         if (rc < 0)
 490                 return rc;
 491
 492         /* RF_MUX,Polymux */
 493         rc = r820t_write_reg_mask(priv, 0x1a, range->rf_mux_ploy, 0xc3);
 494         if (rc < 0)
 495                 return rc;
 496
 497         /* TF BAND */
 498         rc = r820t_write_reg(priv, 0x1b, range->tf_c);
 499         if (rc < 0)
 500                 return rc;
 501
 502         /* XTAL CAP & Drive */
 503         switch (priv->xtal_cap_sel) {
 504         case XTAL_LOW_CAP_30P:
 505         case XTAL_LOW_CAP_20P:
 506                 val = range->xtal_cap20p | 0x08;
 507                 break;
 508         case XTAL_LOW_CAP_10P:
 509                 val = range->xtal_cap10p | 0x08;
 510                 break;
 511         case XTAL_HIGH_CAP_0P:
 512                 val = range->xtal_cap0p | 0x00;
 513                 break;
 514         default:
 515         case XTAL_LOW_CAP_0P:
 516                 val = range->xtal_cap0p | 0x08;
 517                 break;
 518         }
 519         rc = r820t_write_reg_mask(priv, 0x10, val, 0x0b);
 520         if (rc < 0)
 521                 return rc;
 522
 523         if (priv->imr_done) {
 524                 reg08 = priv->imr_data[range->imr_mem].gain_x;
 525                 reg09 = priv->imr_data[range->imr_mem].phase_y;
 526         } else {
 527                 reg08 = 0;
 528                 reg09 = 0;
 529         }
 530         rc = r820t_write_reg_mask(priv, 0x08, reg08, 0x3f);
 531         if (rc < 0)
 532                 return rc;
 533
 534         rc = r820t_write_reg_mask(priv, 0x09, reg09, 0x3f);
 535
 536         return rc;
 537 }
 538
 539 static int r820t_set_pll(struct r820t_priv *priv, enum v4l2_tuner_type type,
 540                          u32 freq)
 541 {
 542         u32 vco_freq;
 543         int rc, i;
 544         unsigned sleep_time = 10000;
 545         u32 vco_fra;            /* VCO contribution by SDM (kHz) */
 546         u32 vco_min  = 1770000;
 547         u32 vco_max  = vco_min * 2;
 548         u32 pll_ref;
 549         u16 n_sdm = 2;
 550         u16 sdm = 0;
 551         u8 mix_div = 2;
 552         u8 div_buf = 0;
 553         u8 div_num = 0;
 554         u8 refdiv2 = 0;
 555         u8 ni, si, nint, vco_fine_tune, val;
 556         u8 data[5];
 557
 558         /* Frequency in kHz */
 559         freq = freq / 1000;
 560         pll_ref = priv->cfg->xtal / 1000;
 561
 562         if ((priv->cfg->rafael_chip == CHIP_R620D) ||
 563            (priv->cfg->rafael_chip == CHIP_R828D) ||
 564            (priv->cfg->rafael_chip == CHIP_R828)) {
 565                 /* ref set refdiv2, reffreq = Xtal/2 on ATV application */
 566                 if (type != V4L2_TUNER_DIGITAL_TV) {
 567                         pll_ref /= 2;
 568                         refdiv2 = 0x10;
 569                         sleep_time = 20000;
 570                 }
 571         } else {
 572                 if (priv->cfg->xtal > 24000000) {
 573                         pll_ref /= 2;
 574                         refdiv2 = 0x10;
 575                 }
 576         }
 577
 578         rc = r820t_write_reg_mask(priv, 0x10, refdiv2, 0x10);
 579         if (rc < 0)
 580                 return rc;
 581
 582         /* set pll autotune = 128kHz */
 583         rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
 584         if (rc < 0)
 585                 return rc;
 586
 587         /* set VCO current = 100 */
 588         rc = r820t_write_reg_mask(priv, 0x12, 0x80, 0xe0);
 589         if (rc < 0)
 590                 return rc;
 591
 592         /* Calculate divider */
 593         while (mix_div <= 64) {
 594                 if (((freq * mix_div) >= vco_min) &&
 595                    ((freq * mix_div) < vco_max)) {
 596                         div_buf = mix_div;
 597                         while (div_buf > 2) {
 598                                 div_buf = div_buf >> 1;
 599                                 div_num++;
 600                         }
 601                         break;
 602                 }
 603                 mix_div = mix_div << 1;
 604         }
 605
 606         rc = r820t_read(priv, 0x00, data, sizeof(data));
 607         if (rc < 0)
 608                 return rc;
 609
 610         vco_fine_tune = (data[4] & 0x30) >> 4;
 611
 612         if (vco_fine_tune > VCO_POWER_REF)
 613                 div_num = div_num - 1;
 614         else if (vco_fine_tune < VCO_POWER_REF)
 615                 div_num = div_num + 1;
 616
 617         rc = r820t_write_reg_mask(priv, 0x10, div_num << 5, 0xe0);
 618         if (rc < 0)
 619                 return rc;
 620
 621         vco_freq = freq * mix_div;
 622         nint = vco_freq / (2 * pll_ref);
 623         vco_fra = vco_freq - 2 * pll_ref * nint;
 624
 625         /* boundary spur prevention */
 626         if (vco_fra < pll_ref / 64) {
 627                 vco_fra = 0;
 628         } else if (vco_fra > pll_ref * 127 / 64) {
 629                 vco_fra = 0;
 630                 nint++;
 631         } else if ((vco_fra > pll_ref * 127 / 128) && (vco_fra < pll_ref)) {
 632                 vco_fra = pll_ref * 127 / 128;
 633         } else if ((vco_fra > pll_ref) && (vco_fra < pll_ref * 129 / 128)) {
 634                 vco_fra = pll_ref * 129 / 128;
 635         }
 636
 637         if (nint > 63) {
 638                 tuner_info("No valid PLL values for %u kHz!\n", freq);
 639                 return -EINVAL;
 640         }
 641
 642         ni = (nint - 13) / 4;
 643         si = nint - 4 * ni - 13;
 644
 645         rc = r820t_write_reg(priv, 0x14, ni + (si << 6));
 646         if (rc < 0)
 647                 return rc;
 648
 649         /* pw_sdm */
 650         if (!vco_fra)
 651                 val = 0x08;
 652         else
 653                 val = 0x00;
 654
 655         rc = r820t_write_reg_mask(priv, 0x12, val, 0x08);
 656         if (rc < 0)
 657                 return rc;
 658
 659         /* sdm calculator */
 660         while (vco_fra > 1) {
 661                 if (vco_fra > (2 * pll_ref / n_sdm)) {
 662                         sdm = sdm + 32768 / (n_sdm / 2);
 663                         vco_fra = vco_fra - 2 * pll_ref / n_sdm;
 664                         if (n_sdm >= 0x8000)
 665                                 break;
 666                 }
 667                 n_sdm = n_sdm << 1;
 668         }
 669
 670         tuner_dbg("freq %d kHz, pll ref %d%s, sdm=0x%04x\n",
 671                   freq, pll_ref, refdiv2 ? " / 2" : "", sdm);
 672
 673         rc = r820t_write_reg(priv, 0x16, sdm >> 8);
 674         if (rc < 0)
 675                 return rc;
 676         rc = r820t_write_reg(priv, 0x15, sdm & 0xff);
 677         if (rc < 0)
 678                 return rc;
 679
 680         for (i = 0; i < 2; i++) {
 681                 usleep_range(sleep_time, sleep_time + 1000);
 682
 683                 /* Check if PLL has locked */
 684                 rc = r820t_read(priv, 0x00, data, 3);
 685                 if (rc < 0)
 686                         return rc;
 687                 if (data[2] & 0x40)
 688                         break;
 689
 690                 if (!i) {
 691                         /* Didn't lock. Increase VCO current */
 692                         rc = r820t_write_reg_mask(priv, 0x12, 0x60, 0xe0);
 693                         if (rc < 0)
 694                                 return rc;
 695                 }
 696         }
 697
 698         if (!(data[2] & 0x40)) {
 699                 priv->has_lock = false;
 700                 return 0;
 701         }
 702
 703         priv->has_lock = true;
 704         tuner_dbg("tuner has lock at frequency %d kHz\n", freq);
 705
 706         /* set pll autotune = 8kHz */
 707         rc = r820t_write_reg_mask(priv, 0x1a, 0x08, 0x08);
 708
 709         return rc;
 710 }
 711
 712 static int r820t_sysfreq_sel(struct r820t_priv *priv, u32 freq,
 713                              enum v4l2_tuner_type type,
 714                              v4l2_std_id std,
 715                              u32 delsys)
 716 {
 717         int rc;
 718         u8 mixer_top, lna_top, cp_cur, div_buf_cur, lna_vth_l, mixer_vth_l;
 719         u8 air_cable1_in, cable2_in, pre_dect, lna_discharge, filter_cur;
 720
 721         tuner_dbg("adjusting tuner parameters for the standard\n");
 722
 723         switch (delsys) {
 724         case SYS_DVBT:
 725                 if ((freq == 506000000) || (freq == 666000000) ||
 726                    (freq == 818000000)) {
 727                         mixer_top = 0x14;       /* mixer top:14 , top-1, low-discharge */
 728                         lna_top = 0xe5;         /* detect bw 3, lna top:4, predet top:2 */
 729                         cp_cur = 0x28;          /* 101, 0.2 */
 730                         div_buf_cur = 0x20;     /* 10, 200u */
 731                 } else {
 732                         mixer_top = 0x24;       /* mixer top:13 , top-1, low-discharge */
 733                         lna_top = 0xe5;         /* detect bw 3, lna top:4, predet top:2 */
 734                         cp_cur = 0x38;          /* 111, auto */
 735                         div_buf_cur = 0x30;     /* 11, 150u */
 736                 }
 737                 lna_vth_l = 0x53;               /* lna vth 0.84 ,  vtl 0.64 */
 738                 mixer_vth_l = 0x75;             /* mixer vth 1.04, vtl 0.84 */
 739                 air_cable1_in = 0x00;
 740                 cable2_in = 0x00;
 741                 pre_dect = 0x40;
 742                 lna_discharge = 14;
 743                 filter_cur = 0x40;              /* 10, low */
 744                 break;
 745         case SYS_DVBT2:
 746                 mixer_top = 0x24;       /* mixer top:13 , top-1, low-discharge */
 747                 lna_top = 0xe5;         /* detect bw 3, lna top:4, predet top:2 */
 748                 lna_vth_l = 0x53;       /* lna vth 0.84 ,  vtl 0.64 */
 749                 mixer_vth_l = 0x75;     /* mixer vth 1.04, vtl 0.84 */
 750                 air_cable1_in = 0x00;
 751                 cable2_in = 0x00;
 752                 pre_dect = 0x40;
 753                 lna_discharge = 14;
 754                 cp_cur = 0x38;          /* 111, auto */
 755                 div_buf_cur = 0x30;     /* 11, 150u */
 756                 filter_cur = 0x40;      /* 10, low */
 757                 break;
 758         case SYS_ISDBT:
 759                 mixer_top = 0x24;       /* mixer top:13 , top-1, low-discharge */
 760                 lna_top = 0xe5;         /* detect bw 3, lna top:4, predet top:2 */
 761                 lna_vth_l = 0x75;       /* lna vth 1.04 ,  vtl 0.84 */
 762                 mixer_vth_l = 0x75;     /* mixer vth 1.04, vtl 0.84 */
 763                 air_cable1_in = 0x00;
 764                 cable2_in = 0x00;
 765                 pre_dect = 0x40;
 766                 lna_discharge = 14;
 767                 cp_cur = 0x38;          /* 111, auto */
 768                 div_buf_cur = 0x30;     /* 11, 150u */
 769                 filter_cur = 0x40;      /* 10, low */
 770                 break;
 771         default: /* DVB-T 8M */
 772                 mixer_top = 0x24;       /* mixer top:13 , top-1, low-discharge */
 773                 lna_top = 0xe5;         /* detect bw 3, lna top:4, predet top:2 */
 774                 lna_vth_l = 0x53;       /* lna vth 0.84 ,  vtl 0.64 */
 775                 mixer_vth_l = 0x75;     /* mixer vth 1.04, vtl 0.84 */
 776                 air_cable1_in = 0x00;
 777                 cable2_in = 0x00;
 778                 pre_dect = 0x40;
 779                 lna_discharge = 14;
 780                 cp_cur = 0x38;          /* 111, auto */
 781                 div_buf_cur = 0x30;     /* 11, 150u */
 782                 filter_cur = 0x40;      /* 10, low */
 783                 break;
 784         }
 785
 786         if (priv->cfg->use_diplexer &&
 787            ((priv->cfg->rafael_chip == CHIP_R820T) ||
 788            (priv->cfg->rafael_chip == CHIP_R828S) ||
 789            (priv->cfg->rafael_chip == CHIP_R820C))) {
 790                 if (freq > DIP_FREQ)
 791                         air_cable1_in = 0x00;
 792                 else
 793                         air_cable1_in = 0x60;
 794                 cable2_in = 0x00;
 795         }
 796
 797         rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0xc7);
 798         if (rc < 0)
 799                 return rc;
 800         rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0xf8);
 801         if (rc < 0)
 802                 return rc;
 803         rc = r820t_write_reg(priv, 0x0d, lna_vth_l);
 804         if (rc < 0)
 805                 return rc;
 806         rc = r820t_write_reg(priv, 0x0e, mixer_vth_l);
 807         if (rc < 0)
 808                 return rc;
 809
 810         /* Air-IN only for Astrometa */
 811         rc = r820t_write_reg_mask(priv, 0x05, air_cable1_in, 0x60);
 812         if (rc < 0)
 813                 return rc;
 814         rc = r820t_write_reg_mask(priv, 0x06, cable2_in, 0x08);
 815         if (rc < 0)
 816                 return rc;
 817
 818         rc = r820t_write_reg_mask(priv, 0x11, cp_cur, 0x38);
 819         if (rc < 0)
 820                 return rc;
 821         rc = r820t_write_reg_mask(priv, 0x17, div_buf_cur, 0x30);
 822         if (rc < 0)
 823                 return rc;
 824         rc = r820t_write_reg_mask(priv, 0x0a, filter_cur, 0x60);
 825         if (rc < 0)
 826                 return rc;
 827         /*
 828          * Original driver initializes regs 0x05 and 0x06 with the
 829          * same value again on this point. Probably, it is just an
 830          * error there
 831          */
 832
 833         /*
 834          * Set LNA
 835          */
 836
 837         tuner_dbg("adjusting LNA parameters\n");
 838         if (type != V4L2_TUNER_ANALOG_TV) {
 839                 /* LNA TOP: lowest */
 840                 rc = r820t_write_reg_mask(priv, 0x1d, 0, 0x38);
 841                 if (rc < 0)
 842                         return rc;
 843
 844                 /* 0: normal mode */
 845                 rc = r820t_write_reg_mask(priv, 0x1c, 0, 0x04);
 846                 if (rc < 0)
 847                         return rc;
 848
 849                 /* 0: PRE_DECT off */
 850                 rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40);
 851                 if (rc < 0)
 852                         return rc;
 853
 854                 /* agc clk 250hz */
 855                 rc = r820t_write_reg_mask(priv, 0x1a, 0x30, 0x30);
 856                 if (rc < 0)
 857                         return rc;
 858
 859                 msleep(250);
 860
 861                 /* write LNA TOP = 3 */
 862                 rc = r820t_write_reg_mask(priv, 0x1d, 0x18, 0x38);
 863                 if (rc < 0)
 864                         return rc;
 865
 866                 /*
 867                  * write discharge mode
 868                  * FIXME: IMHO, the mask here is wrong, but it matches
 869                  * what's there at the original driver
 870                  */
 871                 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04);
 872                 if (rc < 0)
 873                         return rc;
 874
 875                 /* LNA discharge current */
 876                 rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f);
 877                 if (rc < 0)
 878                         return rc;
 879
 880                 /* agc clk 60hz */
 881                 rc = r820t_write_reg_mask(priv, 0x1a, 0x20, 0x30);
 882                 if (rc < 0)
 883                         return rc;
 884         } else {
 885                 /* PRE_DECT off */
 886                 rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40);
 887                 if (rc < 0)
 888                         return rc;
 889
 890                 /* write LNA TOP */
 891                 rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0x38);
 892                 if (rc < 0)
 893                         return rc;
 894
 895                 /*
 896                  * write discharge mode
 897                  * FIXME: IMHO, the mask here is wrong, but it matches
 898                  * what's there at the original driver
 899                  */
 900                 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04);
 901                 if (rc < 0)
 902                         return rc;
 903
 904                 /* LNA discharge current */
 905                 rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f);
 906                 if (rc < 0)
 907                         return rc;
 908
 909                 /* agc clk 1Khz, external det1 cap 1u */
 910                 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x30);
 911                 if (rc < 0)
 912                         return rc;
 913
 914                 rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x04);
 915                 if (rc < 0)
 916                         return rc;
 917          }
 918          return 0;
 919 }
 920
 921 static int r820t_set_tv_standard(struct r820t_priv *priv,
 922                                  unsigned bw,
 923                                  enum v4l2_tuner_type type,
 924                                  v4l2_std_id std, u32 delsys)
 925
 926 {
 927         int rc, i;
 928         u32 if_khz, filt_cal_lo;
 929         u8 data[5], val;
 930         u8 filt_gain, img_r, filt_q, hp_cor, ext_enable, loop_through;
 931         u8 lt_att, flt_ext_widest, polyfil_cur;
 932         bool need_calibration;
 933
 934         tuner_dbg("selecting the delivery system\n");
 935
 936         if (delsys == SYS_ISDBT) {
 937                 if_khz = 4063;
 938                 filt_cal_lo = 59000;
 939                 filt_gain = 0x10;       /* +3db, 6mhz on */
 940                 img_r = 0x00;           /* image negative */
 941                 filt_q = 0x10;          /* r10[4]:low q(1'b1) */
 942                 hp_cor = 0x6a;          /* 1.7m disable, +2cap, 1.25mhz */
 943                 ext_enable = 0x40;      /* r30[6], ext enable; r30[5]:0 ext at lna max */
 944                 loop_through = 0x00;    /* r5[7], lt on */
 945                 lt_att = 0x00;          /* r31[7], lt att enable */
 946                 flt_ext_widest = 0x00;  /* r15[7]: flt_ext_wide off */
 947                 polyfil_cur = 0x60;     /* r25[6:5]:min */
 948         } else {
 949                 if (bw <= 6) {
 950                         if_khz = 3570;
 951                         filt_cal_lo = 56000;    /* 52000->56000 */
 952                         filt_gain = 0x10;       /* +3db, 6mhz on */
 953                         img_r = 0x00;           /* image negative */
 954                         filt_q = 0x10;          /* r10[4]:low q(1'b1) */
 955                         hp_cor = 0x6b;          /* 1.7m disable, +2cap, 1.0mhz */
 956                         ext_enable = 0x60;      /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
 957                         loop_through = 0x00;    /* r5[7], lt on */
 958                         lt_att = 0x00;          /* r31[7], lt att enable */
 959                         flt_ext_widest = 0x00;  /* r15[7]: flt_ext_wide off */
 960                         polyfil_cur = 0x60;     /* r25[6:5]:min */
 961                 } else if (bw == 7) {
 962 #if 0
 963                         /*
 964                          * There are two 7 MHz tables defined on the original
 965                          * driver, but just the second one seems to be visible
 966                          * by rtl2832. Keep this one here commented, as it
 967                          * might be needed in the future
 968                          */
 969
 970                         if_khz = 4070;
 971                         filt_cal_lo = 60000;
 972                         filt_gain = 0x10;       /* +3db, 6mhz on */
 973                         img_r = 0x00;           /* image negative */
 974                         filt_q = 0x10;          /* r10[4]:low q(1'b1) */
 975                         hp_cor = 0x2b;          /* 1.7m disable, +1cap, 1.0mhz */
 976                         ext_enable = 0x60;      /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
 977                         loop_through = 0x00;    /* r5[7], lt on */
 978                         lt_att = 0x00;          /* r31[7], lt att enable */
 979                         flt_ext_widest = 0x00;  /* r15[7]: flt_ext_wide off */
 980                         polyfil_cur = 0x60;     /* r25[6:5]:min */
 981 #endif
 982                         /* 7 MHz, second table */
 983                         if_khz = 4570;
 984                         filt_cal_lo = 63000;
 985                         filt_gain = 0x10;       /* +3db, 6mhz on */
 986                         img_r = 0x00;           /* image negative */
 987                         filt_q = 0x10;          /* r10[4]:low q(1'b1) */
 988                         hp_cor = 0x2a;          /* 1.7m disable, +1cap, 1.25mhz */
 989                         ext_enable = 0x60;      /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
 990                         loop_through = 0x00;    /* r5[7], lt on */
 991                         lt_att = 0x00;          /* r31[7], lt att enable */
 992                         flt_ext_widest = 0x00;  /* r15[7]: flt_ext_wide off */
 993                         polyfil_cur = 0x60;     /* r25[6:5]:min */
 994                 } else {
 995                         if_khz = 4570;
 996                         filt_cal_lo = 68500;
 997                         filt_gain = 0x10;       /* +3db, 6mhz on */
 998                         img_r = 0x00;           /* image negative */
 999                         filt_q = 0x10;          /* r10[4]:low q(1'b1) */
1000                         hp_cor = 0x0b;          /* 1.7m disable, +0cap, 1.0mhz */
1001                         ext_enable = 0x60;      /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
1002                         loop_through = 0x00;    /* r5[7], lt on */
1003                         lt_att = 0x00;          /* r31[7], lt att enable */
1004                         flt_ext_widest = 0x00;  /* r15[7]: flt_ext_wide off */
1005                         polyfil_cur = 0x60;     /* r25[6:5]:min */
1006                 }
1007         }
1008
1009         /* Initialize the shadow registers */
1010         memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1011
1012         /* Init Flag & Xtal_check Result */
1013         if (priv->imr_done)
1014                 val = 1 | priv->xtal_cap_sel << 1;
1015         else
1016                 val = 0;
1017         rc = r820t_write_reg_mask(priv, 0x0c, val, 0x0f);
1018         if (rc < 0)
1019                 return rc;
1020
1021         /* version */
1022         rc = r820t_write_reg_mask(priv, 0x13, VER_NUM, 0x3f);
1023         if (rc < 0)
1024                 return rc;
1025
1026         /* for LT Gain test */
1027         if (type != V4L2_TUNER_ANALOG_TV) {
1028                 rc = r820t_write_reg_mask(priv, 0x1d, 0x00, 0x38);
1029                 if (rc < 0)
1030                         return rc;
1031                 usleep_range(1000, 2000);
1032         }
1033         priv->int_freq = if_khz * 1000;
1034
1035         /* Check if standard changed. If so, filter calibration is needed */
1036         if (type != priv->type)
1037                 need_calibration = true;
1038         else if ((type == V4L2_TUNER_ANALOG_TV) && (std != priv->std))
1039                 need_calibration = true;
1040         else if ((type == V4L2_TUNER_DIGITAL_TV) &&
1041                  ((delsys != priv->delsys) || bw != priv->bw))
1042                 need_calibration = true;
1043         else
1044                 need_calibration = false;
1045
1046         if (need_calibration) {
1047                 tuner_dbg("calibrating the tuner\n");
1048                 for (i = 0; i < 2; i++) {
1049                         /* Set filt_cap */
1050                         rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0x60);
1051                         if (rc < 0)
1052                                 return rc;
1053
1054                         /* set cali clk =on */
1055                         rc = r820t_write_reg_mask(priv, 0x0f, 0x04, 0x04);
1056                         if (rc < 0)
1057                                 return rc;
1058
1059                         /* X'tal cap 0pF for PLL */
1060                         rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x03);
1061                         if (rc < 0)
1062                                 return rc;
1063
1064                         rc = r820t_set_pll(priv, type, filt_cal_lo * 1000);
1065                         if (rc < 0 || !priv->has_lock)
1066                                 return rc;
1067
1068                         /* Start Trigger */
1069                         rc = r820t_write_reg_mask(priv, 0x0b, 0x10, 0x10);
1070                         if (rc < 0)
1071                                 return rc;
1072
1073                         usleep_range(1000, 2000);
1074
1075                         /* Stop Trigger */
1076                         rc = r820t_write_reg_mask(priv, 0x0b, 0x00, 0x10);
1077                         if (rc < 0)
1078                                 return rc;
1079
1080                         /* set cali clk =off */
1081                         rc = r820t_write_reg_mask(priv, 0x0f, 0x00, 0x04);
1082                         if (rc < 0)
1083                                 return rc;
1084
1085                         /* Check if calibration worked */
1086                         rc = r820t_read(priv, 0x00, data, sizeof(data));
1087                         if (rc < 0)
1088                                 return rc;
1089
1090                         priv->fil_cal_code = data[4] & 0x0f;
1091                         if (priv->fil_cal_code && priv->fil_cal_code != 0x0f)
1092                                 break;
1093                 }
1094                 /* narrowest */
1095                 if (priv->fil_cal_code == 0x0f)
1096                         priv->fil_cal_code = 0;
1097         }
1098
1099         rc = r820t_write_reg_mask(priv, 0x0a,
1100                                   filt_q | priv->fil_cal_code, 0x1f);
1101         if (rc < 0)
1102                 return rc;
1103
1104         /* Set BW, Filter_gain, & HP corner */
1105         rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0xef);
1106         if (rc < 0)
1107                 return rc;
1108
1109
1110         /* Set Img_R */
1111         rc = r820t_write_reg_mask(priv, 0x07, img_r, 0x80);
1112         if (rc < 0)
1113                 return rc;
1114
1115         /* Set filt_3dB, V6MHz */
1116         rc = r820t_write_reg_mask(priv, 0x06, filt_gain, 0x30);
1117         if (rc < 0)
1118                 return rc;
1119
1120         /* channel filter extension */
1121         rc = r820t_write_reg_mask(priv, 0x1e, ext_enable, 0x60);
1122         if (rc < 0)
1123                 return rc;
1124
1125         /* Loop through */
1126         rc = r820t_write_reg_mask(priv, 0x05, loop_through, 0x80);
1127         if (rc < 0)
1128                 return rc;
1129
1130         /* Loop through attenuation */
1131         rc = r820t_write_reg_mask(priv, 0x1f, lt_att, 0x80);
1132         if (rc < 0)
1133                 return rc;
1134
1135         /* filter extension widest */
1136         rc = r820t_write_reg_mask(priv, 0x0f, flt_ext_widest, 0x80);
1137         if (rc < 0)
1138                 return rc;
1139
1140         /* RF poly filter current */
1141         rc = r820t_write_reg_mask(priv, 0x19, polyfil_cur, 0x60);
1142         if (rc < 0)
1143                 return rc;
1144
1145         /* Store current standard. If it changes, re-calibrate the tuner */
1146         priv->delsys = delsys;
1147         priv->type = type;
1148         priv->std = std;
1149         priv->bw = bw;
1150
1151         return 0;
1152 }
1153
1154 static int r820t_read_gain(struct r820t_priv *priv)
1155 {
1156         u8 data[4];
1157         int rc;
1158
1159         rc = r820t_read(priv, 0x00, data, sizeof(data));
1160         if (rc < 0)
1161                 return rc;
1162
1163         return ((data[3] & 0x0f) << 1) + ((data[3] & 0xf0) >> 4);
1164 }
1165
1166 #if 0
1167 /* FIXME: This routine requires more testing */
1168 static int r820t_set_gain_mode(struct r820t_priv *priv,
1169                                bool set_manual_gain,
1170                                int gain)
1171 {
1172         int rc;
1173
1174         if (set_manual_gain) {
1175                 int i, total_gain = 0;
1176                 uint8_t mix_index = 0, lna_index = 0;
1177                 u8 data[4];
1178
1179                 /* LNA auto off */
1180                 rc = r820t_write_reg_mask(priv, 0x05, 0x10, 0x10);
1181                 if (rc < 0)
1182                         return rc;
1183
1184                  /* Mixer auto off */
1185                 rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10);
1186                 if (rc < 0)
1187                         return rc;
1188
1189                 rc = r820t_read(priv, 0x00, data, sizeof(data));
1190                 if (rc < 0)
1191                         return rc;
1192
1193                 /* set fixed VGA gain for now (16.3 dB) */
1194                 rc = r820t_write_reg_mask(priv, 0x0c, 0x08, 0x9f);
1195                 if (rc < 0)
1196                         return rc;
1197
1198                 for (i = 0; i < 15; i++) {
1199                         if (total_gain >= gain)
1200                                 break;
1201
1202                         total_gain += r820t_lna_gain_steps[++lna_index];
1203
1204                         if (total_gain >= gain)
1205                                 break;
1206
1207                         total_gain += r820t_mixer_gain_steps[++mix_index];
1208                 }
1209
1210                 /* set LNA gain */
1211                 rc = r820t_write_reg_mask(priv, 0x05, lna_index, 0x0f);
1212                 if (rc < 0)
1213                         return rc;
1214
1215                 /* set Mixer gain */
1216                 rc = r820t_write_reg_mask(priv, 0x07, mix_index, 0x0f);
1217                 if (rc < 0)
1218                         return rc;
1219         } else {
1220                 /* LNA */
1221                 rc = r820t_write_reg_mask(priv, 0x05, 0, 0x10);
1222                 if (rc < 0)
1223                         return rc;
1224
1225                 /* Mixer */
1226                 rc = r820t_write_reg_mask(priv, 0x07, 0x10, 0x10);
1227                 if (rc < 0)
1228                         return rc;
1229
1230                 /* set fixed VGA gain for now (26.5 dB) */
1231                 rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f);
1232                 if (rc < 0)
1233                         return rc;
1234         }
1235
1236         return 0;
1237 }
1238 #endif
1239
1240 static int generic_set_freq(struct dvb_frontend *fe,
1241                             u32 freq /* in HZ */,
1242                             unsigned bw,
1243                             enum v4l2_tuner_type type,
1244                             v4l2_std_id std, u32 delsys)
1245 {
1246         struct r820t_priv               *priv = fe->tuner_priv;
1247         int                             rc = -EINVAL;
1248         u32                             lo_freq;
1249
1250         tuner_dbg("should set frequency to %d kHz, bw %d MHz\n",
1251                   freq / 1000, bw);
1252
1253         rc = r820t_set_tv_standard(priv, bw, type, std, delsys);
1254         if (rc < 0)
1255                 goto err;
1256
1257         if ((type == V4L2_TUNER_ANALOG_TV) && (std == V4L2_STD_SECAM_LC))
1258                 lo_freq = freq - priv->int_freq;
1259          else
1260                 lo_freq = freq + priv->int_freq;
1261
1262         rc = r820t_set_mux(priv, lo_freq);
1263         if (rc < 0)
1264                 goto err;
1265
1266         rc = r820t_set_pll(priv, type, lo_freq);
1267         if (rc < 0 || !priv->has_lock)
1268                 goto err;
1269
1270         rc = r820t_sysfreq_sel(priv, freq, type, std, delsys);
1271         if (rc < 0)
1272                 goto err;
1273
1274         tuner_dbg("%s: PLL locked on frequency %d Hz, gain=%d\n",
1275                   __func__, freq, r820t_read_gain(priv));
1276
1277 err:
1278
1279         if (rc < 0)
1280                 tuner_dbg("%s: failed=%d\n", __func__, rc);
1281         return rc;
1282 }
1283
1284 /*
1285  * r820t standby logic
1286  */
1287
1288 static int r820t_standby(struct r820t_priv *priv)
1289 {
1290         int rc;
1291
1292         /* If device was not initialized yet, don't need to standby */
1293         if (!priv->init_done)
1294                 return 0;
1295
1296         rc = r820t_write_reg(priv, 0x06, 0xb1);
1297         if (rc < 0)
1298                 return rc;
1299         rc = r820t_write_reg(priv, 0x05, 0x03);
1300         if (rc < 0)
1301                 return rc;
1302         rc = r820t_write_reg(priv, 0x07, 0x3a);
1303         if (rc < 0)
1304                 return rc;
1305         rc = r820t_write_reg(priv, 0x08, 0x40);
1306         if (rc < 0)
1307                 return rc;
1308         rc = r820t_write_reg(priv, 0x09, 0xc0);
1309         if (rc < 0)
1310                 return rc;
1311         rc = r820t_write_reg(priv, 0x0a, 0x36);
1312         if (rc < 0)
1313                 return rc;
1314         rc = r820t_write_reg(priv, 0x0c, 0x35);
1315         if (rc < 0)
1316                 return rc;
1317         rc = r820t_write_reg(priv, 0x0f, 0x68);
1318         if (rc < 0)
1319                 return rc;
1320         rc = r820t_write_reg(priv, 0x11, 0x03);
1321         if (rc < 0)
1322                 return rc;
1323         rc = r820t_write_reg(priv, 0x17, 0xf4);
1324         if (rc < 0)
1325                 return rc;
1326         rc = r820t_write_reg(priv, 0x19, 0x0c);
1327
1328         /* Force initial calibration */
1329         priv->type = -1;
1330
1331         return rc;
1332 }
1333
1334 /*
1335  * r820t device init logic
1336  */
1337
1338 static int r820t_xtal_check(struct r820t_priv *priv)
1339 {
1340         int rc, i;
1341         u8 data[3], val;
1342
1343         /* Initialize the shadow registers */
1344         memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1345
1346         /* cap 30pF & Drive Low */
1347         rc = r820t_write_reg_mask(priv, 0x10, 0x0b, 0x0b);
1348         if (rc < 0)
1349                 return rc;
1350
1351         /* set pll autotune = 128kHz */
1352         rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
1353         if (rc < 0)
1354                 return rc;
1355
1356         /* set manual initial reg = 111111;  */
1357         rc = r820t_write_reg_mask(priv, 0x13, 0x7f, 0x7f);
1358         if (rc < 0)
1359                 return rc;
1360
1361         /* set auto */
1362         rc = r820t_write_reg_mask(priv, 0x13, 0x00, 0x40);
1363         if (rc < 0)
1364                 return rc;
1365
1366         /* Try several xtal capacitor alternatives */
1367         for (i = 0; i < ARRAY_SIZE(r820t_xtal_capacitor); i++) {
1368                 rc = r820t_write_reg_mask(priv, 0x10,
1369                                           r820t_xtal_capacitor[i][0], 0x1b);
1370                 if (rc < 0)
1371                         return rc;
1372
1373                 usleep_range(5000, 6000);
1374
1375                 rc = r820t_read(priv, 0x00, data, sizeof(data));
1376                 if (rc < 0)
1377                         return rc;
1378                 if ((!data[2]) & 0x40)
1379                         continue;
1380
1381                 val = data[2] & 0x3f;
1382
1383                 if (priv->cfg->xtal == 16000000 && (val > 29 || val < 23))
1384                         break;
1385
1386                 if (val != 0x3f)
1387                         break;
1388         }
1389
1390         if (i == ARRAY_SIZE(r820t_xtal_capacitor))
1391                 return -EINVAL;
1392
1393         return r820t_xtal_capacitor[i][1];
1394 }
1395
1396 static int r820t_imr_prepare(struct r820t_priv *priv)
1397 {
1398         int rc;
1399
1400         /* Initialize the shadow registers */
1401         memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1402
1403         /* lna off (air-in off) */
1404         rc = r820t_write_reg_mask(priv, 0x05, 0x20, 0x20);
1405         if (rc < 0)
1406                 return rc;
1407
1408         /* mixer gain mode = manual */
1409         rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10);
1410         if (rc < 0)
1411                 return rc;
1412
1413         /* filter corner = lowest */
1414         rc = r820t_write_reg_mask(priv, 0x0a, 0x0f, 0x0f);
1415         if (rc < 0)
1416                 return rc;
1417
1418         /* filter bw=+2cap, hp=5M */
1419         rc = r820t_write_reg_mask(priv, 0x0b, 0x60, 0x6f);
1420         if (rc < 0)
1421                 return rc;
1422
1423         /* adc=on, vga code mode, gain = 26.5dB   */
1424         rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f);
1425         if (rc < 0)
1426                 return rc;
1427
1428         /* ring clk = on */
1429         rc = r820t_write_reg_mask(priv, 0x0f, 0, 0x08);
1430         if (rc < 0)
1431                 return rc;
1432
1433         /* ring power = on */
1434         rc = r820t_write_reg_mask(priv, 0x18, 0x10, 0x10);
1435         if (rc < 0)
1436                 return rc;
1437
1438         /* from ring = ring pll in */
1439         rc = r820t_write_reg_mask(priv, 0x1c, 0x02, 0x02);
1440         if (rc < 0)
1441                 return rc;
1442
1443         /* sw_pdect = det3 */
1444         rc = r820t_write_reg_mask(priv, 0x1e, 0x80, 0x80);
1445         if (rc < 0)
1446                 return rc;
1447
1448         /* Set filt_3dB */
1449         rc = r820t_write_reg_mask(priv, 0x06, 0x20, 0x20);
1450
1451         return rc;
1452 }
1453
1454 static int r820t_multi_read(struct r820t_priv *priv)
1455 {
1456         int rc, i;
1457         u8 data[2], min = 0, max = 255, sum = 0;
1458
1459         usleep_range(5000, 6000);
1460
1461         for (i = 0; i < 6; i++) {
1462                 rc = r820t_read(priv, 0x00, data, sizeof(data));
1463                 if (rc < 0)
1464                         return rc;
1465
1466                 sum += data[1];
1467
1468                 if (data[1] < min)
1469                         min = data[1];
1470
1471                 if (data[1] > max)
1472                         max = data[1];
1473         }
1474         rc = sum - max - min;
1475
1476         return rc;
1477 }
1478
1479 static int r820t_imr_cross(struct r820t_priv *priv,
1480                            struct r820t_sect_type iq_point[3],
1481                            u8 *x_direct)
1482 {
1483         struct r820t_sect_type cross[5]; /* (0,0)(0,Q-1)(0,I-1)(Q-1,0)(I-1,0) */
1484         struct r820t_sect_type tmp;
1485         int i, rc;
1486         u8 reg08, reg09;
1487
1488         reg08 = r820t_read_cache_reg(priv, 8) & 0xc0;
1489         reg09 = r820t_read_cache_reg(priv, 9) & 0xc0;
1490
1491         tmp.gain_x = 0;
1492         tmp.phase_y = 0;
1493         tmp.value = 255;
1494
1495         for (i = 0; i < 5; i++) {
1496                 switch (i) {
1497                 case 0:
1498                         cross[i].gain_x  = reg08;
1499                         cross[i].phase_y = reg09;
1500                         break;
1501                 case 1:
1502                         cross[i].gain_x  = reg08;               /* 0 */
1503                         cross[i].phase_y = reg09 + 1;           /* Q-1 */
1504                         break;
1505                 case 2:
1506                         cross[i].gain_x  = reg08;               /* 0 */
1507                         cross[i].phase_y = (reg09 | 0x20) + 1;  /* I-1 */
1508                         break;
1509                 case 3:
1510                         cross[i].gain_x  = reg08 + 1;           /* Q-1 */
1511                         cross[i].phase_y = reg09;
1512                         break;
1513                 default:
1514                         cross[i].gain_x  = (reg08 | 0x20) + 1;  /* I-1 */
1515                         cross[i].phase_y = reg09;
1516                 }
1517
1518                 rc = r820t_write_reg(priv, 0x08, cross[i].gain_x);
1519                 if (rc < 0)
1520                         return rc;
1521
1522                 rc = r820t_write_reg(priv, 0x09, cross[i].phase_y);
1523                 if (rc < 0)
1524                         return rc;
1525
1526                 rc = r820t_multi_read(priv);
1527                 if (rc < 0)
1528                         return rc;
1529
1530                 cross[i].value = rc;
1531
1532                 if (cross[i].value < tmp.value)
1533                         memcpy(&tmp, &cross[i], sizeof(tmp));
1534         }
1535
1536         if ((tmp.phase_y & 0x1f) == 1) {        /* y-direction */
1537                 *x_direct = 0;
1538
1539                 iq_point[0] = cross[0];
1540                 iq_point[1] = cross[1];
1541                 iq_point[2] = cross[2];
1542         } else {                                /* (0,0) or x-direction */
1543                 *x_direct = 1;
1544
1545                 iq_point[0] = cross[0];
1546                 iq_point[1] = cross[3];
1547                 iq_point[2] = cross[4];
1548         }
1549         return 0;
1550 }
1551
1552 static void r820t_compre_cor(struct r820t_sect_type iq[3])
1553 {
1554         int i;
1555
1556         for (i = 3; i > 0; i--) {
1557                 if (iq[0].value > iq[i - 1].value)
1558                         swap(iq[0], iq[i - 1]);
1559         }
1560 }
1561
1562 static int r820t_compre_step(struct r820t_priv *priv,
1563                              struct r820t_sect_type iq[3], u8 reg)
1564 {
1565         int rc;
1566         struct r820t_sect_type tmp;
1567
1568         /*
1569          * Purpose: if (Gain<9 or Phase<9), Gain+1 or Phase+1 and compare
1570          * with min value:
1571          *  new < min => update to min and continue
1572          *  new > min => Exit
1573          */
1574
1575         /* min value already saved in iq[0] */
1576         tmp.phase_y = iq[0].phase_y;
1577         tmp.gain_x  = iq[0].gain_x;
1578
1579         while (((tmp.gain_x & 0x1f) < IMR_TRIAL) &&
1580               ((tmp.phase_y & 0x1f) < IMR_TRIAL)) {
1581                 if (reg == 0x08)
1582                         tmp.gain_x++;
1583                 else
1584                         tmp.phase_y++;
1585
1586                 rc = r820t_write_reg(priv, 0x08, tmp.gain_x);
1587                 if (rc < 0)
1588                         return rc;
1589
1590                 rc = r820t_write_reg(priv, 0x09, tmp.phase_y);
1591                 if (rc < 0)
1592                         return rc;
1593
1594                 rc = r820t_multi_read(priv);
1595                 if (rc < 0)
1596                         return rc;
1597                 tmp.value = rc;
1598
1599                 if (tmp.value <= iq[0].value) {
1600                         iq[0].gain_x  = tmp.gain_x;
1601                         iq[0].phase_y = tmp.phase_y;
1602                         iq[0].value   = tmp.value;
1603                 } else {
1604                         return 0;
1605                 }
1606
1607         }
1608
1609         return 0;
1610 }
1611
1612 static int r820t_iq_tree(struct r820t_priv *priv,
1613                          struct r820t_sect_type iq[3],
1614                          u8 fix_val, u8 var_val, u8 fix_reg)
1615 {
1616         int rc, i;
1617         u8 tmp, var_reg;
1618
1619         /*
1620          * record IMC results by input gain/phase location then adjust
1621          * gain or phase positive 1 step and negtive 1 step,
1622          * both record results
1623          */
1624
1625         if (fix_reg == 0x08)
1626                 var_reg = 0x09;
1627         else
1628                 var_reg = 0x08;
1629
1630         for (i = 0; i < 3; i++) {
1631                 rc = r820t_write_reg(priv, fix_reg, fix_val);
1632                 if (rc < 0)
1633                         return rc;
1634
1635                 rc = r820t_write_reg(priv, var_reg, var_val);
1636                 if (rc < 0)
1637                         return rc;
1638
1639                 rc = r820t_multi_read(priv);
1640                 if (rc < 0)
1641                         return rc;
1642                 iq[i].value = rc;
1643
1644                 if (fix_reg == 0x08) {
1645                         iq[i].gain_x  = fix_val;
1646                         iq[i].phase_y = var_val;
1647                 } else {
1648                         iq[i].phase_y = fix_val;
1649                         iq[i].gain_x  = var_val;
1650                 }
1651
1652                 if (i == 0) {  /* try right-side point */
1653                         var_val++;
1654                 } else if (i == 1) { /* try left-side point */
1655                          /* if absolute location is 1, change I/Q direction */
1656                         if ((var_val & 0x1f) < 0x02) {
1657                                 tmp = 2 - (var_val & 0x1f);
1658
1659                                 /* b[5]:I/Q selection. 0:Q-path, 1:I-path */
1660                                 if (var_val & 0x20) {
1661                                         var_val &= 0xc0;
1662                                         var_val |= tmp;
1663                                 } else {
1664                                         var_val |= 0x20 | tmp;
1665                                 }
1666                         } else {
1667                                 var_val -= 2;
1668                         }
1669                 }
1670         }
1671
1672         return 0;
1673 }
1674
1675 static int r820t_section(struct r820t_priv *priv,
1676                          struct r820t_sect_type *iq_point)
1677 {
1678         int rc;
1679         struct r820t_sect_type compare_iq[3], compare_bet[3];
1680
1681         /* Try X-1 column and save min result to compare_bet[0] */
1682         if (!(iq_point->gain_x & 0x1f))
1683                 compare_iq[0].gain_x = ((iq_point->gain_x) & 0xdf) + 1;  /* Q-path, Gain=1 */
1684         else
1685                 compare_iq[0].gain_x  = iq_point->gain_x - 1;  /* left point */
1686         compare_iq[0].phase_y = iq_point->phase_y;
1687
1688         /* y-direction */
1689         rc = r820t_iq_tree(priv, compare_iq,  compare_iq[0].gain_x,
1690                         compare_iq[0].phase_y, 0x08);
1691         if (rc < 0)
1692                 return rc;
1693
1694         r820t_compre_cor(compare_iq);
1695
1696         compare_bet[0] = compare_iq[0];
1697
1698         /* Try X column and save min result to compare_bet[1] */
1699         compare_iq[0].gain_x  = iq_point->gain_x;
1700         compare_iq[0].phase_y = iq_point->phase_y;
1701
1702         rc = r820t_iq_tree(priv, compare_iq,  compare_iq[0].gain_x,
1703                            compare_iq[0].phase_y, 0x08);
1704         if (rc < 0)
1705                 return rc;
1706
1707         r820t_compre_cor(compare_iq);
1708
1709         compare_bet[1] = compare_iq[0];
1710
1711         /* Try X+1 column and save min result to compare_bet[2] */
1712         if ((iq_point->gain_x & 0x1f) == 0x00)
1713                 compare_iq[0].gain_x = ((iq_point->gain_x) | 0x20) + 1;  /* I-path, Gain=1 */
1714         else
1715                 compare_iq[0].gain_x = iq_point->gain_x + 1;
1716         compare_iq[0].phase_y = iq_point->phase_y;
1717
1718         rc = r820t_iq_tree(priv, compare_iq,  compare_iq[0].gain_x,
1719                            compare_iq[0].phase_y, 0x08);
1720         if (rc < 0)
1721                 return rc;
1722
1723         r820t_compre_cor(compare_iq);
1724
1725         compare_bet[2] = compare_iq[0];
1726
1727         r820t_compre_cor(compare_bet);
1728
1729         *iq_point = compare_bet[0];
1730
1731         return 0;
1732 }
1733
1734 static int r820t_vga_adjust(struct r820t_priv *priv)
1735 {
1736         int rc;
1737         u8 vga_count;
1738
1739         /* increase vga power to let image significant */
1740         for (vga_count = 12; vga_count < 16; vga_count++) {
1741                 rc = r820t_write_reg_mask(priv, 0x0c, vga_count, 0x0f);
1742                 if (rc < 0)
1743                         return rc;
1744
1745                 usleep_range(10000, 11000);
1746
1747                 rc = r820t_multi_read(priv);
1748                 if (rc < 0)
1749                         return rc;
1750
1751                 if (rc > 40 * 4)
1752                         break;
1753         }
1754
1755         return 0;
1756 }
1757
1758 static int r820t_iq(struct r820t_priv *priv, struct r820t_sect_type *iq_pont)
1759 {
1760         struct r820t_sect_type compare_iq[3];
1761         int rc;
1762         u8 x_direction = 0;  /* 1:x, 0:y */
1763         u8 dir_reg, other_reg;
1764
1765         r820t_vga_adjust(priv);
1766
1767         rc = r820t_imr_cross(priv, compare_iq, &x_direction);
1768         if (rc < 0)
1769                 return rc;
1770
1771         if (x_direction == 1) {
1772                 dir_reg   = 0x08;
1773                 other_reg = 0x09;
1774         } else {
1775                 dir_reg   = 0x09;
1776                 other_reg = 0x08;
1777         }
1778
1779         /* compare and find min of 3 points. determine i/q direction */
1780         r820t_compre_cor(compare_iq);
1781
1782         /* increase step to find min value of this direction */
1783         rc = r820t_compre_step(priv, compare_iq, dir_reg);
1784         if (rc < 0)
1785                 return rc;
1786
1787         /* the other direction */
1788         rc = r820t_iq_tree(priv, compare_iq,  compare_iq[0].gain_x,
1789                                 compare_iq[0].phase_y, dir_reg);
1790         if (rc < 0)
1791                 return rc;
1792
1793         /* compare and find min of 3 points. determine i/q direction */
1794         r820t_compre_cor(compare_iq);
1795
1796         /* increase step to find min value on this direction */
1797         rc = r820t_compre_step(priv, compare_iq, other_reg);
1798         if (rc < 0)
1799                 return rc;
1800
1801         /* check 3 points again */
1802         rc = r820t_iq_tree(priv, compare_iq,  compare_iq[0].gain_x,
1803                                 compare_iq[0].phase_y, other_reg);
1804         if (rc < 0)
1805                 return rc;
1806
1807         r820t_compre_cor(compare_iq);
1808
1809         /* section-9 check */
1810         rc = r820t_section(priv, compare_iq);
1811
1812         *iq_pont = compare_iq[0];
1813
1814         /* reset gain/phase control setting */
1815         rc = r820t_write_reg_mask(priv, 0x08, 0, 0x3f);
1816         if (rc < 0)
1817                 return rc;
1818
1819         rc = r820t_write_reg_mask(priv, 0x09, 0, 0x3f);
1820
1821         return rc;
1822 }
1823
1824 static int r820t_f_imr(struct r820t_priv *priv, struct r820t_sect_type *iq_pont)
1825 {
1826         int rc;
1827
1828         r820t_vga_adjust(priv);
1829
1830         /*
1831          * search surrounding points from previous point
1832          * try (x-1), (x), (x+1) columns, and find min IMR result point
1833          */
1834         rc = r820t_section(priv, iq_pont);
1835         if (rc < 0)
1836                 return rc;
1837
1838         return 0;
1839 }
1840
1841 static int r820t_imr(struct r820t_priv *priv, unsigned imr_mem, bool im_flag)
1842 {
1843         struct r820t_sect_type imr_point;
1844         int rc;
1845         u32 ring_vco, ring_freq, ring_ref;
1846         u8 n_ring, n;
1847         int reg18, reg19, reg1f;
1848
1849         if (priv->cfg->xtal > 24000000)
1850                 ring_ref = priv->cfg->xtal / 2;
1851         else
1852                 ring_ref = priv->cfg->xtal;
1853
1854         for (n = 0; n < 16; n++) {
1855                 if ((16 + n) * 8 * ring_ref >= 3100000) {
1856                         n_ring = n;
1857                         break;
1858                 }
1859
1860                 /* n_ring not found */
1861                 if (n == 15)
1862                         n_ring = n;
1863         }
1864
1865         reg18 = r820t_read_cache_reg(priv, 0x18);
1866         reg19 = r820t_read_cache_reg(priv, 0x19);
1867         reg1f = r820t_read_cache_reg(priv, 0x1f);
1868
1869         reg18 &= 0xf0;      /* set ring[3:0] */
1870         reg18 |= n_ring;
1871
1872         ring_vco = (16 + n_ring) * 8 * ring_ref;
1873
1874         reg18 &= 0xdf;   /* clear ring_se23 */
1875         reg19 &= 0xfc;   /* clear ring_seldiv */
1876         reg1f &= 0xfc;   /* clear ring_att */
1877
1878         switch (imr_mem) {
1879         case 0:
1880                 ring_freq = ring_vco / 48;
1881                 reg18 |= 0x20;  /* ring_se23 = 1 */
1882                 reg19 |= 0x03;  /* ring_seldiv = 3 */
1883                 reg1f |= 0x02;  /* ring_att 10 */
1884                 break;
1885         case 1:
1886                 ring_freq = ring_vco / 16;
1887                 reg18 |= 0x00;  /* ring_se23 = 0 */
1888                 reg19 |= 0x02;  /* ring_seldiv = 2 */
1889                 reg1f |= 0x00;  /* pw_ring 00 */
1890                 break;
1891         case 2:
1892                 ring_freq = ring_vco / 8;
1893                 reg18 |= 0x00;  /* ring_se23 = 0 */
1894                 reg19 |= 0x01;  /* ring_seldiv = 1 */
1895                 reg1f |= 0x03;  /* pw_ring 11 */
1896                 break;
1897         case 3:
1898                 ring_freq = ring_vco / 6;
1899                 reg18 |= 0x20;  /* ring_se23 = 1 */
1900                 reg19 |= 0x00;  /* ring_seldiv = 0 */
1901                 reg1f |= 0x03;  /* pw_ring 11 */
1902                 break;
1903         case 4:
1904                 ring_freq = ring_vco / 4;
1905                 reg18 |= 0x00;  /* ring_se23 = 0 */
1906                 reg19 |= 0x00;  /* ring_seldiv = 0 */
1907                 reg1f |= 0x01;  /* pw_ring 01 */
1908                 break;
1909         default:
1910                 ring_freq = ring_vco / 4;
1911                 reg18 |= 0x00;  /* ring_se23 = 0 */
1912                 reg19 |= 0x00;  /* ring_seldiv = 0 */
1913                 reg1f |= 0x01;  /* pw_ring 01 */
1914                 break;
1915         }
1916
1917
1918         /* write pw_ring, n_ring, ringdiv2 registers */
1919
1920         /* n_ring, ring_se23 */
1921         rc = r820t_write_reg(priv, 0x18, reg18);
1922         if (rc < 0)
1923                 return rc;
1924
1925         /* ring_sediv */
1926         rc = r820t_write_reg(priv, 0x19, reg19);
1927         if (rc < 0)
1928                 return rc;
1929
1930         /* pw_ring */
1931         rc = r820t_write_reg(priv, 0x1f, reg1f);
1932         if (rc < 0)
1933                 return rc;
1934
1935         /* mux input freq ~ rf_in freq */
1936         rc = r820t_set_mux(priv, (ring_freq - 5300) * 1000);
1937         if (rc < 0)
1938                 return rc;
1939
1940         rc = r820t_set_pll(priv, V4L2_TUNER_DIGITAL_TV,
1941                            (ring_freq - 5300) * 1000);
1942         if (!priv->has_lock)
1943                 rc = -EINVAL;
1944         if (rc < 0)
1945                 return rc;
1946
1947         if (im_flag) {
1948                 rc = r820t_iq(priv, &imr_point);
1949         } else {
1950                 imr_point.gain_x  = priv->imr_data[3].gain_x;
1951                 imr_point.phase_y = priv->imr_data[3].phase_y;
1952                 imr_point.value   = priv->imr_data[3].value;
1953
1954                 rc = r820t_f_imr(priv, &imr_point);
1955         }
1956         if (rc < 0)
1957                 return rc;
1958
1959         /* save IMR value */
1960         switch (imr_mem) {
1961         case 0:
1962                 priv->imr_data[0].gain_x  = imr_point.gain_x;
1963                 priv->imr_data[0].phase_y = imr_point.phase_y;
1964                 priv->imr_data[0].value   = imr_point.value;
1965                 break;
1966         case 1:
1967                 priv->imr_data[1].gain_x  = imr_point.gain_x;
1968                 priv->imr_data[1].phase_y = imr_point.phase_y;
1969                 priv->imr_data[1].value   = imr_point.value;
1970                 break;
1971         case 2:
1972                 priv->imr_data[2].gain_x  = imr_point.gain_x;
1973                 priv->imr_data[2].phase_y = imr_point.phase_y;
1974                 priv->imr_data[2].value   = imr_point.value;
1975                 break;
1976         case 3:
1977                 priv->imr_data[3].gain_x  = imr_point.gain_x;
1978                 priv->imr_data[3].phase_y = imr_point.phase_y;
1979                 priv->imr_data[3].value   = imr_point.value;
1980                 break;
1981         case 4:
1982                 priv->imr_data[4].gain_x  = imr_point.gain_x;
1983                 priv->imr_data[4].phase_y = imr_point.phase_y;
1984                 priv->imr_data[4].value   = imr_point.value;
1985                 break;
1986         default:
1987                 priv->imr_data[4].gain_x  = imr_point.gain_x;
1988                 priv->imr_data[4].phase_y = imr_point.phase_y;
1989                 priv->imr_data[4].value   = imr_point.value;
1990                 break;
1991         }
1992
1993         return 0;
1994 }
1995
1996 static int r820t_imr_callibrate(struct r820t_priv *priv)
1997 {
1998         int rc, i;
1999         int xtal_cap = 0;
2000
2001         if (priv->init_done)
2002                 return 0;
2003
2004         /* Detect Xtal capacitance */
2005         if ((priv->cfg->rafael_chip == CHIP_R820T) ||
2006             (priv->cfg->rafael_chip == CHIP_R828S) ||
2007             (priv->cfg->rafael_chip == CHIP_R820C)) {
2008                 priv->xtal_cap_sel = XTAL_HIGH_CAP_0P;
2009         } else {
2010                 /* Initialize registers */
2011                 rc = r820t_write(priv, 0x05,
2012                                 r820t_init_array, sizeof(r820t_init_array));
2013                 if (rc < 0)
2014                         return rc;
2015                 for (i = 0; i < 3; i++) {
2016                         rc = r820t_xtal_check(priv);
2017                         if (rc < 0)
2018                                 return rc;
2019                         if (!i || rc > xtal_cap)
2020                                 xtal_cap = rc;
2021                 }
2022                 priv->xtal_cap_sel = xtal_cap;
2023         }
2024
2025         /*
2026          * Disables IMR callibration. That emulates the same behaviour
2027          * as what is done by rtl-sdr userspace library. Useful for testing
2028          */
2029         if (no_imr_cal) {
2030                 priv->init_done = true;
2031
2032                 return 0;
2033         }
2034
2035         /* Initialize registers */
2036         rc = r820t_write(priv, 0x05,
2037                          r820t_init_array, sizeof(r820t_init_array));
2038         if (rc < 0)
2039                 return rc;
2040
2041         rc = r820t_imr_prepare(priv);
2042         if (rc < 0)
2043                 return rc;
2044
2045         rc = r820t_imr(priv, 3, true);
2046         if (rc < 0)
2047                 return rc;
2048         rc = r820t_imr(priv, 1, false);
2049         if (rc < 0)
2050                 return rc;
2051         rc = r820t_imr(priv, 0, false);
2052         if (rc < 0)
2053                 return rc;
2054         rc = r820t_imr(priv, 2, false);
2055         if (rc < 0)
2056                 return rc;
2057         rc = r820t_imr(priv, 4, false);
2058         if (rc < 0)
2059                 return rc;
2060
2061         priv->init_done = true;
2062         priv->imr_done = true;
2063
2064         return 0;
2065 }
2066
2067 #if 0
2068 /* Not used, for now */
2069 static int r820t_gpio(struct r820t_priv *priv, bool enable)
2070 {
2071         return r820t_write_reg_mask(priv, 0x0f, enable ? 1 : 0, 0x01);
2072 }
2073 #endif
2074
2075 /*
2076  *  r820t frontend operations and tuner attach code
2077  *
2078  * All driver locks and i2c control are only in this part of the code
2079  */
2080
2081 static int r820t_init(struct dvb_frontend *fe)
2082 {
2083         struct r820t_priv *priv = fe->tuner_priv;
2084         int rc;
2085
2086         tuner_dbg("%s:\n", __func__);
2087
2088         mutex_lock(&priv->lock);
2089         if (fe->ops.i2c_gate_ctrl)
2090                 fe->ops.i2c_gate_ctrl(fe, 1);
2091
2092         rc = r820t_imr_callibrate(priv);
2093         if (rc < 0)
2094                 goto err;
2095
2096         /* Initialize registers */
2097         rc = r820t_write(priv, 0x05,
2098                          r820t_init_array, sizeof(r820t_init_array));
2099
2100 err:
2101         if (fe->ops.i2c_gate_ctrl)
2102                 fe->ops.i2c_gate_ctrl(fe, 0);
2103         mutex_unlock(&priv->lock);
2104
2105         if (rc < 0)
2106                 tuner_dbg("%s: failed=%d\n", __func__, rc);
2107         return rc;
2108 }
2109
2110 static int r820t_sleep(struct dvb_frontend *fe)
2111 {
2112         struct r820t_priv *priv = fe->tuner_priv;
2113         int rc;
2114
2115         tuner_dbg("%s:\n", __func__);
2116
2117         mutex_lock(&priv->lock);
2118         if (fe->ops.i2c_gate_ctrl)
2119                 fe->ops.i2c_gate_ctrl(fe, 1);
2120
2121         rc = r820t_standby(priv);
2122
2123         if (fe->ops.i2c_gate_ctrl)
2124                 fe->ops.i2c_gate_ctrl(fe, 0);
2125         mutex_unlock(&priv->lock);
2126
2127         tuner_dbg("%s: failed=%d\n", __func__, rc);
2128         return rc;
2129 }
2130
2131 static int r820t_set_analog_freq(struct dvb_frontend *fe,
2132                                  struct analog_parameters *p)
2133 {
2134         struct r820t_priv *priv = fe->tuner_priv;
2135         unsigned bw;
2136         int rc;
2137
2138         tuner_dbg("%s called\n", __func__);
2139
2140         /* if std is not defined, choose one */
2141         if (!p->std)
2142                 p->std = V4L2_STD_MN;
2143
2144         if ((p->std == V4L2_STD_PAL_M) || (p->std == V4L2_STD_NTSC))
2145                 bw = 6;
2146         else
2147                 bw = 8;
2148
2149         mutex_lock(&priv->lock);
2150         if (fe->ops.i2c_gate_ctrl)
2151                 fe->ops.i2c_gate_ctrl(fe, 1);
2152
2153         rc = generic_set_freq(fe, 62500l * p->frequency, bw,
2154                               V4L2_TUNER_ANALOG_TV, p->std, SYS_UNDEFINED);
2155
2156         if (fe->ops.i2c_gate_ctrl)
2157                 fe->ops.i2c_gate_ctrl(fe, 0);
2158         mutex_unlock(&priv->lock);
2159
2160         return rc;
2161 }
2162
2163 static int r820t_set_params(struct dvb_frontend *fe)
2164 {
2165         struct r820t_priv *priv = fe->tuner_priv;
2166         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2167         int rc;
2168         unsigned bw;
2169
2170         tuner_dbg("%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n",
2171                 __func__, c->delivery_system, c->frequency, c->bandwidth_hz);
2172
2173         mutex_lock(&priv->lock);
2174         if (fe->ops.i2c_gate_ctrl)
2175                 fe->ops.i2c_gate_ctrl(fe, 1);
2176
2177         bw = (c->bandwidth_hz + 500000) / 1000000;
2178         if (!bw)
2179                 bw = 8;
2180
2181         rc = generic_set_freq(fe, c->frequency, bw,
2182                               V4L2_TUNER_DIGITAL_TV, 0, c->delivery_system);
2183
2184         if (fe->ops.i2c_gate_ctrl)
2185                 fe->ops.i2c_gate_ctrl(fe, 0);
2186         mutex_unlock(&priv->lock);
2187
2188         if (rc)
2189                 tuner_dbg("%s: failed=%d\n", __func__, rc);
2190         return rc;
2191 }
2192
2193 static int r820t_signal(struct dvb_frontend *fe, u16 *strength)
2194 {
2195         struct r820t_priv *priv = fe->tuner_priv;
2196         int rc = 0;
2197
2198         mutex_lock(&priv->lock);
2199         if (fe->ops.i2c_gate_ctrl)
2200                 fe->ops.i2c_gate_ctrl(fe, 1);
2201
2202         if (priv->has_lock) {
2203                 rc = r820t_read_gain(priv);
2204                 if (rc < 0)
2205                         goto err;
2206
2207                 /* A higher gain at LNA means a lower signal strength */
2208                 *strength = (45 - rc) << 4 | 0xff;
2209                 if (*strength == 0xff)
2210                         *strength = 0;
2211         } else {
2212                 *strength = 0;
2213         }
2214
2215 err:
2216         if (fe->ops.i2c_gate_ctrl)
2217                 fe->ops.i2c_gate_ctrl(fe, 0);
2218         mutex_unlock(&priv->lock);
2219
2220         tuner_dbg("%s: %s, gain=%d strength=%d\n",
2221                   __func__,
2222                   priv->has_lock ? "PLL locked" : "no signal",
2223                   rc, *strength);
2224
2225         return 0;
2226 }
2227
2228 static int r820t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
2229 {
2230         struct r820t_priv *priv = fe->tuner_priv;
2231
2232         tuner_dbg("%s:\n", __func__);
2233
2234         *frequency = priv->int_freq;
2235
2236         return 0;
2237 }
2238
2239 static int r820t_release(struct dvb_frontend *fe)
2240 {
2241         struct r820t_priv *priv = fe->tuner_priv;
2242
2243         tuner_dbg("%s:\n", __func__);
2244
2245         mutex_lock(&r820t_list_mutex);
2246
2247         if (priv)
2248                 hybrid_tuner_release_state(priv);
2249
2250         mutex_unlock(&r820t_list_mutex);
2251
2252         fe->tuner_priv = NULL;
2253
2254         kfree(fe->tuner_priv);
2255
2256         return 0;
2257 }
2258
2259 static const struct dvb_tuner_ops r820t_tuner_ops = {
2260         .info = {
2261                 .name           = "Rafael Micro R820T",
2262                 .frequency_min  =   42000000,
2263                 .frequency_max  = 1002000000,
2264         },
2265         .init = r820t_init,
2266         .release = r820t_release,
2267         .sleep = r820t_sleep,
2268         .set_params = r820t_set_params,
2269         .set_analog_params = r820t_set_analog_freq,
2270         .get_if_frequency = r820t_get_if_frequency,
2271         .get_rf_strength = r820t_signal,
2272 };
2273
2274 struct dvb_frontend *r820t_attach(struct dvb_frontend *fe,
2275                                   struct i2c_adapter *i2c,
2276                                   const struct r820t_config *cfg)
2277 {
2278         struct r820t_priv *priv;
2279         int rc = -ENODEV;
2280         u8 data[5];
2281         int instance;
2282
2283         mutex_lock(&r820t_list_mutex);
2284
2285         instance = hybrid_tuner_request_state(struct r820t_priv, priv,
2286                                               hybrid_tuner_instance_list,
2287                                               i2c, cfg->i2c_addr,
2288                                               "r820t");
2289         switch (instance) {
2290         case 0:
2291                 /* memory allocation failure */
2292                 goto err_no_gate;
2293                 break;
2294         case 1:
2295                 /* new tuner instance */
2296                 priv->cfg = cfg;
2297
2298                 mutex_init(&priv->lock);
2299
2300                 fe->tuner_priv = priv;
2301                 break;
2302         case 2:
2303                 /* existing tuner instance */
2304                 fe->tuner_priv = priv;
2305                 break;
2306         }
2307
2308         memcpy(&fe->ops.tuner_ops, &r820t_tuner_ops, sizeof(r820t_tuner_ops));
2309
2310         if (fe->ops.i2c_gate_ctrl)
2311                 fe->ops.i2c_gate_ctrl(fe, 1);
2312
2313         /* check if the tuner is there */
2314         rc = r820t_read(priv, 0x00, data, sizeof(data));
2315         if (rc < 0)
2316                 goto err;
2317
2318         rc = r820t_sleep(fe);
2319         if (rc < 0)
2320                 goto err;
2321
2322         tuner_info("Rafael Micro r820t successfully identified\n");
2323
2324         fe->tuner_priv = priv;
2325         memcpy(&fe->ops.tuner_ops, &r820t_tuner_ops,
2326                         sizeof(struct dvb_tuner_ops));
2327
2328         if (fe->ops.i2c_gate_ctrl)
2329                 fe->ops.i2c_gate_ctrl(fe, 0);
2330
2331         mutex_unlock(&r820t_list_mutex);
2332
2333         return fe;
2334 err:
2335         if (fe->ops.i2c_gate_ctrl)
2336                 fe->ops.i2c_gate_ctrl(fe, 0);
2337
2338 err_no_gate:
2339         mutex_unlock(&r820t_list_mutex);
2340
2341         tuner_info("%s: failed=%d\n", __func__, rc);
2342         r820t_release(fe);
2343         return NULL;
2344 }
2345 EXPORT_SYMBOL_GPL(r820t_attach);
2346
2347 MODULE_DESCRIPTION("Rafael Micro r820t silicon tuner driver");
2348 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
2349 MODULE_LICENSE("GPL");