drivers/media/sprd_dcam/sc8830/dcam_drv.h

   1 /*
   2  * Copyright (C) 2012 Spreadtrum Communications Inc.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #ifndef _DCAM_DRV_8830_H_
  15 #define _DCAM_DRV_8830_H_
  16
  17 #include <linux/types.h>
  18 #include "dcam_reg.h"
  19 #include "parse_hwinfo.h"
  20
  21 //#define DCAM_DEBUG
  22
  23 #ifdef DCAM_DEBUG
  24         #define DCAM_TRACE             printk
  25 #else
  26         #define DCAM_TRACE             pr_debug
  27 #endif
  28
  29 #define DCAM_WAIT_FOREVER                        0xFFFFFFFF
  30 #define DCAM_PATH_1_FRM_CNT_MAX                  8
  31 #define DCAM_PATH_2_FRM_CNT_MAX                  8
  32 #define DCAM_PATH_0_FRM_CNT_MAX                  8
  33 #define DCAM_FRM_CNT_MAX                         8  /* max between path_1_frm_cnt and path_2_frm_cnt */
  34 #define DCAM_HEIGHT_MIN                          4
  35 #define DCAM_JPEG_LENGTH_MIN                     30720 /*640X480  div 10*/
  36
  37 enum dcam_swtich_status {
  38         DCAM_SWITCH_IDLE = 0,
  39         DCAM_SWITCH_PAUSE,
  40         DCAM_SWITCH_DONE,
  41         DCAM_SWITCH_MAX
  42 };
  43
  44 enum dcam_drv_rtn {
  45         DCAM_RTN_SUCCESS = 0,
  46         DCAM_RTN_PARA_ERR = 0x10,
  47         DCAM_RTN_IO_ID_ERR,
  48         DCAM_RTN_ISR_ID_ERR,
  49         DCAM_RTN_MASTER_SEL_ERR,
  50         DCAM_RTN_MODE_ERR,
  51         DCAM_RTN_TIMEOUT,
  52
  53         DCAM_RTN_CAP_FRAME_SEL_ERR = 0x20,
  54         DCAM_RTN_CAP_IN_FORMAT_ERR,
  55         DCAM_RTN_CAP_IN_BITS_ERR,
  56         DCAM_RTN_CAP_IN_YUV_ERR,
  57         DCAM_RTN_CAP_SYNC_POL_ERR,
  58         DCAM_RTN_CAP_SKIP_FRAME_ERR,
  59         DCAM_RTN_CAP_FRAME_DECI_ERR,
  60         DCAM_RTN_CAP_XY_DECI_ERR,
  61         DCAM_RTN_CAP_FRAME_SIZE_ERR,
  62         DCAM_RTN_CAP_SENSOR_MODE_ERR,
  63         DCAM_RTN_CAP_JPEG_BUF_LEN_ERR,
  64         DCAM_RTN_CAP_IF_MODE_ERR,
  65
  66         DCAM_RTN_PATH_SRC_SIZE_ERR = 0x30,
  67         DCAM_RTN_PATH_TRIM_SIZE_ERR,
  68         DCAM_RTN_PATH_DES_SIZE_ERR,
  69         DCAM_RTN_PATH_IN_FMT_ERR,
  70         DCAM_RTN_PATH_OUT_FMT_ERR,
  71         DCAM_RTN_PATH_SC_ERR,
  72         DCAM_RTN_PATH_SUB_SAMPLE_ERR,
  73         DCAM_RTN_PATH_ADDR_ERR,
  74         DCAM_RTN_PATH_FRAME_TOO_MANY,
  75         DCAM_RTN_PATH_FRAME_LOCKED,
  76         DCAM_RTN_PATH_NO_MEM,
  77         DCAM_RTN_PATH_GEN_COEFF_ERR,
  78         DCAM_RTN_PATH_SRC_ERR,
  79         DCAM_RTN_PATH_ENDIAN_ERR,
  80         DCAM_RTN_PATH_FRM_DECI_ERR,
  81         DCAM_RTN_MAX
  82 };
  83
  84 enum dcam_rst_mode {
  85         DCAM_RST_ALL = 0,
  86         DCAM_RST_PATH0,
  87         DCAM_RST_PATH1,
  88         DCAM_RST_PATH2
  89 };
  90
  91 enum dcam_path_index {
  92         DCAM_PATH_IDX_NONE = 0,
  93         DCAM_PATH_IDX_0 = 1,
  94         DCAM_PATH_IDX_1 = 2,
  95         DCAM_PATH_IDX_2 = 4,
  96         DCAM_PATH_IDX_ALL  = 7,
  97 };
  98
  99
 100 enum dcam_fmt {
 101         DCAM_YUV422 = 0,
 102         DCAM_YUV420,
 103         DCAM_YUV420_3FRAME,
 104         DCAM_YUV400,
 105         DCAM_RGB565,
 106         DCAM_RGB888,
 107         DCAM_RAWRGB,
 108         DCAM_JPEG,
 109         DCAM_FTM_MAX
 110 };
 111
 112 enum dcam_cap_pattern {
 113         DCAM_YUYV  = 0,
 114         DCAM_YVYU,
 115         DCAM_UYVY,
 116         DCAM_VYUY,
 117         DCAM_PATTERN_MAX
 118 };
 119
 120 enum dcam_capture_mode {
 121         DCAM_CAPTURE_MODE_SINGLE = 0,
 122         DCAM_CAPTURE_MODE_MULTIPLE,
 123         DCAM_CAPTURE_MODE_MAX
 124 };
 125
 126
 127 enum dcam_irq_id {
 128         DCAM_SN_SOF = 0,
 129         DCAM_SN_EOF,
 130         DCAM_CAP_SOF,
 131         DCAM_CAP_EOF,
 132         DCAM_PATH0_DONE,
 133         DCAM_PATH0_OV,
 134         DCAM_PATH1_DONE,
 135         DCAM_PATH1_OV,
 136         DCAM_PATH2_DONE,
 137         DCAM_PATH2_OV,
 138         DCAM_SN_LINE_ERR,
 139         DCAM_SN_FRAME_ERR,
 140         DCAM_JPEG_BUF_OV,
 141         DCAM_ISP_OV,
 142         DCAM_MIPI_OV,
 143         DCAM_ROT_DONE,
 144         DCAM_PATH1_SLICE_DONE,
 145         DCAM_PATH2_SLICE_DONE,
 146         DCAM_RAW_SLICE_DONE,
 147         DCAM_PATH1_SOF,
 148         DCAM_PATH2_SOF,
 149         DCAM_IRQ_NUMBER
 150 };
 151
 152 enum dcam_cfg_id {
 153         DCAM_CAP_SYNC_POL = 0,
 154         DCAM_CAP_DATA_BITS,
 155         DCAM_CAP_DATA_PACKET,
 156         DCAM_CAP_YUV_TYPE,
 157         DCAM_CAP_PRE_SKIP_CNT,
 158         DCAM_CAP_FRM_DECI,
 159         DCAM_CAP_FRM_COUNT_CLR,
 160         DCAM_CAP_FRM_COUNT_GET,
 161         DCAM_CAP_INPUT_RECT,
 162         DCAM_CAP_IMAGE_XY_DECI,
 163         DCAM_CAP_JPEG_GET_LENGTH,
 164         DCAM_CAP_JPEG_SET_BUF_LEN,
 165         DCAM_CAP_TO_ISP,
 166         DCAM_CAP_SAMPLE_MODE,
 167         DCAM_CAP_ZOOM_MODE,
 168
 169         DCAM_PATH_INPUT_SIZE,
 170         DCAM_PATH_INPUT_RECT,
 171         DCAM_PATH_INPUT_ADDR,
 172         DCAM_PATH_OUTPUT_SIZE,
 173         DCAM_PATH_OUTPUT_FORMAT,
 174         DCAM_PATH_OUTPUT_ADDR,
 175         DCAM_PATH_FRAME_BASE_ID,
 176         DCAM_PATH_SWAP_BUFF,
 177         DCAM_PATH_SUB_SAMPLE_EN_X,
 178         DCAM_PATH_SUB_SAMPLE_EN_Y,
 179         DCAM_PATH_SUB_SAMPLE_MOD,
 180         DCAM_PATH_SLICE_SCALE_EN,
 181         DCAM_PATH_SLICE_SCALE_HEIGHT,
 182         DCAM_PATH_DITHER_EN,
 183         DCAM_PATH_IS_IN_SCALE_RANGE,
 184         DCAM_PATH_IS_SCALE_EN,
 185         DCAM_PATH_SLICE_OUT_HEIGHT,
 186         DCAM_PATH_DATA_ENDIAN,
 187         DCAM_PATH_SRC_SEL,
 188         DCAM_PATH_ENABLE,
 189         DCAM_PATH_FRAME_TYPE,
 190         DCAM_PATH_ROT_MODE,
 191         DCAM_PATH_FRM_DECI,
 192         DCAM_PATH_SHRINK,
 193         DCAM_CFG_ID_E_MAX
 194 };
 195
 196 /*
 197 enum dcam_sub_sample_mode
 198 {
 199         DCAM_SUB_2  = 0,
 200         DCAM_SUB_4,
 201         DCAM_SUB_8,
 202         DCAM_SUB_16,
 203         DCAM_SUB_MAX
 204 };
 205
 206 enum dcam_ahb_frm
 207 {
 208         DCAM_AHB_FRAME_SRC,
 209         DCAM_AHB_FRAME_PATH1_DST,
 210         DCAM_AHB_FRAME_PATH2_DST,
 211         DCAM_AHB_FRAME_SWAP,
 212         DCAM_AHB_FRAME_LINE,
 213         DCAM_AHB_FRAME_MAX
 214 };
 215 */
 216 enum iram_owner {
 217         IRAM_FOR_DCAM = 0,
 218         IRAM_FOR_ARM
 219 };
 220
 221 enum dcam_clk_sel {
 222         DCAM_CLK_256M = 0,
 223         DCAM_CLK_128M,
 224         DCAM_CLK_76M8,
 225         DCAM_CLK_48M,
 226         DCAM_CLK_NONE
 227 };
 228
 229 enum dcam_cap_if_mode {
 230         DCAM_CAP_IF_CCIR = 0,
 231         DCAM_CAP_IF_CSI2,
 232         DCAM_CAP_IF_MODE_MAX
 233 };
 234
 235 enum dcam_path_src_sel {
 236         DCAM_PATH_FROM_CAP = 0,
 237         DCAM_PATH_FROM_ISP,
 238         DCAM_PATH_FROM_NONE
 239 };
 240
 241 enum dcam_cap_sensor_mode {
 242         DCAM_CAP_MODE_YUV = 0,
 243         DCAM_CAP_MODE_SPI,
 244         DCAM_CAP_MODE_JPEG,
 245         DCAM_CAP_MODE_RAWRGB,
 246         DCAM_CAP_MODE_MAX
 247 };
 248
 249 enum dcam_cap_data_bits {
 250         DCAM_CAP_12_BITS = 12,
 251         DCAM_CAP_10_BITS = 10,
 252         DCAM_CAP_8_BITS = 8,
 253         DCAM_CAP_4_BITS = 4,
 254         DCAM_CAP_2_BITS = 2,
 255         DCAM_CAP_1_BITS = 1,
 256         DCAM_CAP_BITS_MAX = 0xFF
 257 };
 258
 259 enum dcam_data_endian {
 260         DCAM_ENDIAN_BIG = 0,
 261         DCAM_ENDIAN_LITTLE,
 262         DCAM_ENDIAN_HALFBIG,
 263         DCAM_ENDIAN_HALFLITTLE,
 264         DCAM_ENDIAN_MAX
 265 };
 266
 267 enum dcam_output_mode {
 268         DCAM_OUTPUT_WORD = 0,
 269         DCAM_OUTPUT_HALF_WORD,
 270 };
 271
 272 enum dcam_glb_reg_id {
 273         DCAM_CFG_REG = 0,
 274         DCAM_CONTROL_REG,
 275         DCAM_INIT_MASK_REG,
 276         DCAM_INIT_CLR_REG,
 277         DCAM_AHBM_STS_REG,
 278         DCAM_ENDIAN_REG,
 279         DCAM_REG_MAX
 280 };
 281
 282 enum dcam_v4l2_wtite_cmd_id {
 283         DCAM_V4L2_WRITE_STOP = 0x5AA5,
 284         DCAM_V4L2_WRITE_FREE_FRAME = 0xA55A,
 285         DCAM_V4L2_WRITE_MAX
 286 };
 287
 288 struct dcam_cap_sync_pol {
 289         uint8_t               vsync_pol;
 290         uint8_t               hsync_pol;
 291         uint8_t               pclk_pol;
 292         uint8_t               need_href;
 293         uint8_t               pclk_src;
 294         uint8_t               reserved[3];
 295 };
 296
 297 struct dcam_endian_sel {
 298         uint8_t               y_endian;
 299         uint8_t               uv_endian;
 300         uint8_t               reserved0;
 301         uint8_t               reserved1;
 302 };
 303
 304 struct dcam_cap_dec {
 305         uint8_t                x_factor;
 306         uint8_t                y_factor;
 307         uint8_t                x_mode;
 308         uint8_t                reserved;
 309 };
 310
 311 struct dcam_path_dec {
 312         uint8_t                x_factor;
 313         uint8_t                y_factor;
 314         uint8_t                reserved[2];
 315 };
 316
 317 struct dcam_size {
 318         uint32_t               w;
 319         uint32_t               h;
 320 };
 321
 322 struct dcam_rect {
 323         uint32_t               x;
 324         uint32_t               y;
 325         uint32_t               w;
 326         uint32_t               h;
 327 };
 328
 329 struct dcam_addr {
 330         uint32_t               yaddr;
 331         uint32_t               uaddr;
 332         uint32_t               vaddr;
 333 };
 334
 335 struct dcam_sc_tap {
 336         uint32_t               y_tap;
 337         uint32_t               uv_tap;
 338 };
 339
 340 struct dcam_deci {
 341         uint32_t               deci_x_en;
 342         uint32_t               deci_x;
 343         uint32_t               deci_y_en;
 344         uint32_t               deci_y;
 345 };
 346
 347 struct dcam_frame {
 348         uint32_t               type;
 349         uint32_t               lock;
 350         uint32_t               flags;
 351         uint32_t               fid;
 352         uint32_t               width;
 353         uint32_t               height;
 354         uint32_t               yaddr;
 355         uint32_t               uaddr;
 356         uint32_t               vaddr;
 357         struct dcam_frame      *prev;
 358         struct dcam_frame      *next;
 359 };
 360
 361 struct dcam_get_path_id {
 362         uint32_t               fourcc;
 363         uint32_t               is_path_work[DCAM_PATH_MAX];
 364         uint32_t               need_isp_tool;
 365         uint32_t               need_isp;
 366         uint32_t               need_shrink;
 367         struct dcam_size       input_size;
 368         struct dcam_rect       input_trim;
 369         struct dcam_size       output_size;
 370 };
 371
 372 typedef int (*dcam_isr_func)(struct dcam_frame* frame, void* u_data);
 373
 374 int32_t    dcam_module_init(enum dcam_cap_if_mode if_mode,
 375                         enum dcam_cap_sensor_mode sn_mode);
 376 int32_t    dcam_module_deinit(enum dcam_cap_if_mode if_mode,
 377                         enum dcam_cap_sensor_mode sn_mode);
 378 int32_t    dcam_module_en(struct device_node *dn);
 379 int32_t    dcam_module_dis(struct device_node *dn);
 380 int32_t    dcam_mipi_clk_en(struct device_node *dn);
 381 int32_t    dcam_mipi_clk_dis(struct device_node *dn);
 382 int32_t    dcam_ccir_clk_en(void);
 383 int32_t    dcam_ccir_clk_dis(void);
 384 int32_t    dcam_reset(enum dcam_rst_mode reset_mode, uint32_t is_isr);
 385 int32_t    dcam_set_clk(struct device_node *dn, enum dcam_clk_sel clk_sel);
 386 int32_t    dcam_update_path(enum dcam_path_index path_index, struct dcam_size *in_size,
 387                         struct dcam_rect *in_rect, struct dcam_size *out_size);
 388 int32_t    dcam_start_path(enum dcam_path_index path_index);
 389 int32_t    dcam_start(void);
 390 int32_t    dcam_stop_path(enum dcam_path_index path_index);
 391 int32_t    dcam_stop(void);
 392 int32_t    dcam_resume(void);
 393 int32_t    dcam_pause(void);
 394 int32_t    dcam_reg_isr(enum dcam_irq_id id, dcam_isr_func user_func, void* u_data);
 395 int32_t    dcam_cap_cfg(enum dcam_cfg_id id, void *param);
 396 int32_t    dcam_cap_get_info(enum dcam_cfg_id id, void *param);
 397 int32_t    dcam_path0_cfg(enum dcam_cfg_id id, void *param);
 398 int32_t    dcam_path1_cfg(enum dcam_cfg_id id, void *param);
 399 int32_t    dcam_path2_cfg(enum dcam_cfg_id id, void *param);
 400 int32_t    dcam_get_resizer(uint32_t wait_opt);
 401 int32_t    dcam_rel_resizer(void);
 402 void       dcam_int_en(void);
 403 void       dcam_int_dis(void);
 404 int32_t    dcam_frame_is_locked(struct dcam_frame *frame);
 405 int32_t    dcam_frame_lock(struct dcam_frame *frame);
 406 int32_t    dcam_frame_unlock(struct dcam_frame *frame);
 407 int32_t    dcam_read_registers(uint32_t* reg_buf, uint32_t *buf_len);
 408 int32_t    dcam_resize_start(void);
 409 int32_t    dcam_resize_end(void);
 410 int32_t    dcam_stop_cap(void);
 411 void       dcam_glb_reg_awr(uint32_t addr, uint32_t val, uint32_t reg_id);
 412 void       dcam_glb_reg_owr(uint32_t addr, uint32_t val, uint32_t reg_id);
 413 void       dcam_glb_reg_mwr(uint32_t addr, uint32_t mask, uint32_t val, uint32_t reg_id);
 414 int        dcam_scale_coeff_alloc(void);
 415 void       dcam_scale_coeff_free(void);
 416 int32_t    dcam_rotation_start(void);
 417 int32_t    dcam_rotation_end(void);
 418 int32_t    dcam_get_path_id(struct dcam_get_path_id *path_id, uint32_t *channel_id);
 419 int32_t    dcam_stop_sc_coeff(void);
 420 #endif //_DCAM_DRV_8830_H_