drivers/media/sprd_dcam/pike/dcam_drv.h

   1 /*
   2  * Copyright (C) 2012 Spreadtrum Communications Inc.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #ifndef _DCAM_DRV_8830_H_
  15 #define _DCAM_DRV_8830_H_
  16
  17 #include <linux/types.h>
  18 #include "dcam_reg.h"
  19 #include "parse_hwinfo.h"
  20
  21 //#define DCAM_DEBUG
  22
  23 #ifdef DCAM_DEBUG
  24         #define DCAM_TRACE             printk
  25 #else
  26         #define DCAM_TRACE             pr_debug
  27 #endif
  28
  29 #define DCAM_WAIT_FOREVER                        0xFFFFFFFF
  30 #define DCAM_PATH_1_FRM_CNT_MAX                  10
  31 #define DCAM_PATH_2_FRM_CNT_MAX                  10/*4*/
  32 #define DCAM_PATH_0_FRM_CNT_MAX                  10
  33 #define DCAM_FRM_CNT_MAX                         10  /* max between path_1_frm_cnt and path_2_frm_cnt */
  34 #define DCAM_HEIGHT_MIN                          4
  35 #define DCAM_JPEG_LENGTH_MIN                     30720 /*640X480  div 10*/
  36
  37 enum dcam_swtich_status {
  38         DCAM_SWITCH_IDLE = 0,
  39         DCAM_SWITCH_PAUSE,
  40         DCAM_SWITCH_DONE,
  41         DCAM_SWITCH_MAX
  42 };
  43
  44 enum dcam_drv_rtn {
  45         DCAM_RTN_SUCCESS = 0,
  46         DCAM_RTN_PARA_ERR = 0x10,
  47         DCAM_RTN_IO_ID_ERR,
  48         DCAM_RTN_ISR_ID_ERR,
  49         DCAM_RTN_MASTER_SEL_ERR,
  50         DCAM_RTN_MODE_ERR,
  51         DCAM_RTN_TIMEOUT,
  52
  53         DCAM_RTN_CAP_FRAME_SEL_ERR = 0x20,
  54         DCAM_RTN_CAP_IN_FORMAT_ERR,
  55         DCAM_RTN_CAP_IN_BITS_ERR,
  56         DCAM_RTN_CAP_IN_YUV_ERR,
  57         DCAM_RTN_CAP_SYNC_POL_ERR,
  58         DCAM_RTN_CAP_SKIP_FRAME_ERR,
  59         DCAM_RTN_CAP_FRAME_DECI_ERR,
  60         DCAM_RTN_CAP_XY_DECI_ERR,
  61         DCAM_RTN_CAP_FRAME_SIZE_ERR,
  62         DCAM_RTN_CAP_SENSOR_MODE_ERR,
  63         DCAM_RTN_CAP_JPEG_BUF_LEN_ERR,
  64         DCAM_RTN_CAP_IF_MODE_ERR,
  65
  66         DCAM_RTN_PATH_SRC_SIZE_ERR = 0x30,
  67         DCAM_RTN_PATH_TRIM_SIZE_ERR,
  68         DCAM_RTN_PATH_DES_SIZE_ERR,
  69         DCAM_RTN_PATH_IN_FMT_ERR,
  70         DCAM_RTN_PATH_OUT_FMT_ERR,
  71         DCAM_RTN_PATH_SC_ERR,
  72         DCAM_RTN_PATH_SUB_SAMPLE_ERR,
  73         DCAM_RTN_PATH_ADDR_ERR,
  74         DCAM_RTN_PATH_FRAME_TOO_MANY,
  75         DCAM_RTN_PATH_FRAME_LOCKED,
  76         DCAM_RTN_PATH_NO_MEM,
  77         DCAM_RTN_PATH_GEN_COEFF_ERR,
  78         DCAM_RTN_PATH_SRC_ERR,
  79         DCAM_RTN_PATH_ENDIAN_ERR,
  80         DCAM_RTN_PATH_FRM_DECI_ERR,
  81         DCAM_RTN_MAX
  82 };
  83
  84 enum dcam_rst_mode {
  85         DCAM_RST_ALL = 0,
  86         DCAM_RST_PATH0,
  87         DCAM_RST_PATH1,
  88         DCAM_RST_PATH2
  89 };
  90
  91 enum dcam_path_index {
  92         DCAM_PATH_IDX_NONE = 0,
  93         DCAM_PATH_IDX_0 = 1,
  94         DCAM_PATH_IDX_1 = 2,
  95         DCAM_PATH_IDX_2 = 4,
  96         DCAM_PATH_IDX_ALL  = 7,
  97 };
  98
  99
 100 enum dcam_fmt {
 101         DCAM_YUV422 = 0,
 102         DCAM_YUV420,
 103         DCAM_YUV420_3FRAME,
 104         DCAM_YUV400,
 105         DCAM_RGB565,
 106         DCAM_RGB888,
 107         DCAM_RAWRGB,
 108         DCAM_JPEG,
 109         DCAM_FTM_MAX
 110 };
 111
 112 enum dcam_cap_pattern {
 113         DCAM_YUYV  = 0,
 114         DCAM_YVYU,
 115         DCAM_UYVY,
 116         DCAM_VYUY,
 117         DCAM_PATTERN_MAX
 118 };
 119
 120 enum dcam_capture_mode {
 121         DCAM_CAPTURE_MODE_SINGLE = 0,
 122         DCAM_CAPTURE_MODE_MULTIPLE,
 123         DCAM_CAPTURE_MODE_MAX
 124 };
 125
 126
 127 enum dcam_irq_id {
 128         DCAM_SN_SOF = 0,
 129         DCAM_SN_EOF,
 130         DCAM_CAP_SOF,
 131         DCAM_CAP_EOF,
 132         DCAM_PATH0_DONE,
 133         DCAM_PATH0_OV,
 134         DCAM_PATH1_DONE,
 135         DCAM_PATH1_OV,
 136         DCAM_PATH2_DONE,
 137         DCAM_PATH2_OV,
 138         DCAM_SN_LINE_ERR,
 139         DCAM_SN_FRAME_ERR,
 140         DCAM_JPEG_BUF_OV,
 141         DCAM_ISP_OV,
 142         DCAM_MIPI_OV,
 143         DCAM_ROT_DONE,
 144         DCAM_PATH1_SLICE_DONE,
 145         DCAM_PATH2_SLICE_DONE,
 146         DCAM_RAW_SLICE_DONE,
 147         DCAM_PATH1_SOF,
 148         DCAM_PATH2_SOF,
 149         DCAM_IRQ_NUMBER
 150 };
 151
 152 enum dcam_cfg_id {
 153         DCAM_CAP_SYNC_POL = 0,
 154         DCAM_CAP_DATA_BITS,
 155         DCAM_CAP_DATA_PACKET,
 156         DCAM_CAP_YUV_TYPE,
 157         DCAM_CAP_PRE_SKIP_CNT,
 158         DCAM_CAP_FRM_DECI,
 159         DCAM_CAP_FRM_COUNT_CLR,
 160         DCAM_CAP_FRM_COUNT_GET,
 161         DCAM_CAP_INPUT_RECT,
 162         DCAM_CAP_IMAGE_XY_DECI,
 163         DCAM_CAP_JPEG_GET_LENGTH,
 164         DCAM_CAP_JPEG_SET_BUF_LEN,
 165         DCAM_CAP_TO_ISP,
 166         DCAM_CAP_SAMPLE_MODE,
 167         DCAM_CAP_ZOOM_MODE,
 168
 169         DCAM_PATH_INPUT_SIZE,
 170         DCAM_PATH_INPUT_RECT,
 171         DCAM_PATH_INPUT_ADDR,
 172         DCAM_PATH_OUTPUT_SIZE,
 173         DCAM_PATH_OUTPUT_FORMAT,
 174         DCAM_PATH_OUTPUT_ADDR,
 175         DCAM_PATH_OUTPUT_RESERVED_ADDR,
 176         DCAM_PATH_FRAME_BASE_ID,
 177         DCAM_PATH_SWAP_BUFF,
 178         DCAM_PATH_SUB_SAMPLE_EN_X,
 179         DCAM_PATH_SUB_SAMPLE_EN_Y,
 180         DCAM_PATH_SUB_SAMPLE_MOD,
 181         DCAM_PATH_SLICE_SCALE_EN,
 182         DCAM_PATH_SLICE_SCALE_HEIGHT,
 183         DCAM_PATH_DITHER_EN,
 184         DCAM_PATH_IS_IN_SCALE_RANGE,
 185         DCAM_PATH_IS_SCALE_EN,
 186         DCAM_PATH_SLICE_OUT_HEIGHT,
 187         DCAM_PATH_DATA_ENDIAN,
 188         DCAM_PATH_SRC_SEL,
 189         DCAM_PATH_ENABLE,
 190         DCAM_PATH_FRAME_TYPE,
 191         DCAM_PATH_ROT_MODE,
 192         DCAM_PATH_FRM_DECI,
 193         DCAM_PATH_SHRINK,
 194         DCAM_CFG_ID_E_MAX
 195 };
 196
 197 /*
 198 enum dcam_sub_sample_mode
 199 {
 200         DCAM_SUB_2  = 0,
 201         DCAM_SUB_4,
 202         DCAM_SUB_8,
 203         DCAM_SUB_16,
 204         DCAM_SUB_MAX
 205 };
 206
 207 enum dcam_ahb_frm
 208 {
 209         DCAM_AHB_FRAME_SRC,
 210         DCAM_AHB_FRAME_PATH1_DST,
 211         DCAM_AHB_FRAME_PATH2_DST,
 212         DCAM_AHB_FRAME_SWAP,
 213         DCAM_AHB_FRAME_LINE,
 214         DCAM_AHB_FRAME_MAX
 215 };
 216 */
 217 enum iram_owner {
 218         IRAM_FOR_DCAM = 0,
 219         IRAM_FOR_ARM
 220 };
 221
 222 enum dcam_clk_sel {
 223         DCAM_CLK_312M = 0,
 224         DCAM_CLK_256M,
 225         DCAM_CLK_128M,
 226         DCAM_CLK_76M8,
 227         DCAM_CLK_NONE
 228 };
 229
 230 enum dcam_cap_if_mode {
 231         DCAM_CAP_IF_CCIR = 0,
 232         DCAM_CAP_IF_CSI2,
 233         DCAM_CAP_IF_MODE_MAX
 234 };
 235
 236 enum dcam_path_src_sel {
 237         DCAM_PATH_FROM_CAP = 0,
 238         DCAM_PATH_FROM_ISP,
 239         DCAM_PATH_FROM_NONE
 240 };
 241
 242 enum dcam_cap_sensor_mode {
 243         DCAM_CAP_MODE_YUV = 0,
 244         DCAM_CAP_MODE_SPI,
 245         DCAM_CAP_MODE_JPEG,
 246         DCAM_CAP_MODE_RAWRGB,
 247         DCAM_CAP_MODE_MAX
 248 };
 249
 250 enum dcam_cap_data_bits {
 251         DCAM_CAP_12_BITS = 12,
 252         DCAM_CAP_10_BITS = 10,
 253         DCAM_CAP_8_BITS = 8,
 254         DCAM_CAP_4_BITS = 4,
 255         DCAM_CAP_2_BITS = 2,
 256         DCAM_CAP_1_BITS = 1,
 257         DCAM_CAP_BITS_MAX = 0xFF
 258 };
 259
 260 enum dcam_data_endian {
 261         DCAM_ENDIAN_BIG = 0,
 262         DCAM_ENDIAN_LITTLE,
 263         DCAM_ENDIAN_HALFBIG,
 264         DCAM_ENDIAN_HALFLITTLE,
 265         DCAM_ENDIAN_MAX
 266 };
 267
 268 enum dcam_output_mode {
 269         DCAM_OUTPUT_WORD = 0,
 270         DCAM_OUTPUT_HALF_WORD,
 271         DCAM_OUTPUT_YVYU_1FRAME,
 272         DCAM_OUTPUT_YUV420,
 273 };
 274
 275 enum dcam_glb_reg_id {
 276         DCAM_CFG_REG = 0,
 277         DCAM_CONTROL_REG,
 278         DCAM_INIT_MASK_REG,
 279         DCAM_INIT_CLR_REG,
 280         DCAM_AHBM_STS_REG,
 281         DCAM_ENDIAN_REG,
 282         DCAM_REG_MAX
 283 };
 284
 285 enum dcam_v4l2_wtite_cmd_id {
 286         DCAM_V4L2_WRITE_STOP = 0x5AA5,
 287         DCAM_V4L2_WRITE_FREE_FRAME = 0xA55A,
 288         DCAM_V4L2_WRITE_MAX
 289 };
 290
 291 struct dcam_cap_sync_pol {
 292         uint8_t               vsync_pol;
 293         uint8_t               hsync_pol;
 294         uint8_t               pclk_pol;
 295         uint8_t               need_href;
 296         uint8_t               pclk_src;
 297         uint8_t               reserved[3];
 298 };
 299
 300 struct dcam_endian_sel {
 301         uint8_t               y_endian;
 302         uint8_t               uv_endian;
 303         uint8_t               reserved0;
 304         uint8_t               reserved1;
 305 };
 306
 307 struct dcam_cap_dec {
 308         uint8_t                x_factor;
 309         uint8_t                y_factor;
 310         uint8_t                x_mode;
 311         uint8_t                reserved;
 312 };
 313
 314 struct dcam_path_dec {
 315         uint8_t                x_factor;
 316         uint8_t                y_factor;
 317         uint8_t                reserved[2];
 318 };
 319
 320 struct dcam_size {
 321         uint32_t               w;
 322         uint32_t               h;
 323 };
 324
 325 struct dcam_rect {
 326         uint32_t               x;
 327         uint32_t               y;
 328         uint32_t               w;
 329         uint32_t               h;
 330 };
 331
 332 struct dcam_addr {
 333         uint32_t               yaddr;
 334         uint32_t               uaddr;
 335         uint32_t               vaddr;
 336         uint32_t               yaddr_vir;
 337         uint32_t               uaddr_vir;
 338         uint32_t               vaddr_vir;
 339
 340 };
 341
 342 struct dcam_sc_tap {
 343         uint32_t               y_tap;
 344         uint32_t               uv_tap;
 345 };
 346
 347 struct dcam_deci {
 348         uint32_t               deci_x_en;
 349         uint32_t               deci_x;
 350         uint32_t               deci_y_en;
 351         uint32_t               deci_y;
 352 };
 353
 354 struct dcam_frame {
 355         uint32_t               type;
 356         uint32_t               lock;
 357         uint32_t               flags;
 358         uint32_t               fid;
 359         uint32_t               width;
 360         uint32_t               height;
 361         uint32_t               yaddr;
 362         uint32_t               uaddr;
 363         uint32_t               vaddr;
 364         uint32_t               yaddr_vir;
 365         uint32_t               uaddr_vir;
 366         uint32_t               vaddr_vir;
 367         struct dcam_frame      *prev;
 368         struct dcam_frame      *next;
 369 };
 370
 371 struct dcam_get_path_id {
 372         uint32_t               fourcc;
 373         uint32_t               is_path_work[DCAM_PATH_MAX];
 374         uint32_t               need_isp_tool;
 375         uint32_t               need_isp;
 376         uint32_t               need_shrink;
 377         struct dcam_size       input_size;
 378         struct dcam_rect       input_trim;
 379         struct dcam_size       output_size;
 380 };
 381
 382 struct dcam_path_info {
 383         uint32_t               line_buf;
 384         uint32_t               support_yuv;
 385         uint32_t               support_raw;
 386         uint32_t               support_jpeg;
 387         uint32_t               support_scaling;
 388         uint32_t               support_trim;
 389         uint32_t               is_scaleing_path;
 390 };
 391
 392 struct dcam_path_capability {
 393         uint32_t               count;
 394         struct dcam_path_info  path_info[DCAM_PATH_MAX];
 395 };
 396
 397
 398 typedef int (*dcam_isr_func)(struct dcam_frame* frame, void* u_data);
 399
 400 int32_t    dcam_module_init(enum dcam_cap_if_mode if_mode,
 401                         enum dcam_cap_sensor_mode sn_mode);
 402 int32_t    dcam_module_deinit(enum dcam_cap_if_mode if_mode,
 403                         enum dcam_cap_sensor_mode sn_mode);
 404 int32_t    dcam_module_en(struct device_node *dn);
 405 int32_t    dcam_module_dis(struct device_node *dn);
 406 int32_t    dcam_mipi_clk_en(struct device_node *dn);
 407 int32_t    dcam_mipi_clk_dis(struct device_node *dn);
 408 int32_t    dcam_ccir_clk_en(void);
 409 int32_t    dcam_ccir_clk_dis(void);
 410 int32_t    dcam_reset(enum dcam_rst_mode reset_mode, uint32_t is_isr);
 411 int32_t    dcam_set_clk(struct device_node *dn, enum dcam_clk_sel clk_sel);
 412 int32_t    dcam_update_path(enum dcam_path_index path_index, struct dcam_size *in_size,
 413                         struct dcam_rect *in_rect, struct dcam_size *out_size);
 414 int32_t    dcam_start_path(enum dcam_path_index path_index);
 415 int32_t    dcam_start(void);
 416 int32_t    dcam_stop_path(enum dcam_path_index path_index);
 417 int32_t    dcam_stop(void);
 418 int32_t    dcam_resume(void);
 419 int32_t    dcam_pause(void);
 420 int32_t    dcam_reg_isr(enum dcam_irq_id id, dcam_isr_func user_func, void* u_data);
 421 int32_t    dcam_cap_cfg(enum dcam_cfg_id id, void *param);
 422 int32_t    dcam_cap_get_info(enum dcam_cfg_id id, void *param);
 423 int32_t    dcam_path0_cfg(enum dcam_cfg_id id, void *param);
 424 int32_t    dcam_path1_cfg(enum dcam_cfg_id id, void *param);
 425 int32_t    dcam_path2_cfg(enum dcam_cfg_id id, void *param);
 426 int32_t    dcam_get_resizer(uint32_t wait_opt);
 427 int32_t    dcam_rel_resizer(void);
 428 void       dcam_int_en(void);
 429 void       dcam_int_dis(void);
 430 int32_t    dcam_frame_is_locked(struct dcam_frame *frame);
 431 int32_t    dcam_frame_lock(struct dcam_frame *frame);
 432 int32_t    dcam_frame_unlock(struct dcam_frame *frame);
 433 int32_t    dcam_read_registers(uint32_t* reg_buf, uint32_t *buf_len);
 434 int32_t    dcam_resize_start(void);
 435 int32_t    dcam_resize_end(void);
 436 int32_t    dcam_stop_cap(void);
 437 void       dcam_glb_reg_awr(uint32_t addr, uint32_t val, uint32_t reg_id);
 438 void       dcam_glb_reg_owr(uint32_t addr, uint32_t val, uint32_t reg_id);
 439 void       dcam_glb_reg_mwr(uint32_t addr, uint32_t mask, uint32_t val, uint32_t reg_id);
 440 int        dcam_scale_coeff_alloc(void);
 441 void       dcam_scale_coeff_free(void);
 442 int32_t    dcam_rotation_start(void);
 443 int32_t    dcam_rotation_end(void);
 444 int32_t    dcam_get_path_id(struct dcam_get_path_id *path_id, uint32_t *channel_id);
 445 int32_t    dcam_stop_sc_coeff(void);
 446 int32_t    dcam_get_path_capability(struct dcam_path_capability *capacity);
 447
 448 #endif //_DCAM_DRV_8830_H_